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gerrit-public.fairphone.software / toolchain / llvm-project / 98f9389f65e630a7243f9c99717009107758d492 / . / llvm / test / CodeGen / RISCV / vararg.ll
blob: c930f7d1af67800fc61bec5db9ff2c009c662c2c [file] [log] [blame]
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]3; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
5; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]6
7declare void @llvm.va_start(i8*)
8declare void @llvm.va_end(i8*)
9
10declare void @notdead(i8*)
11
12; Although frontends are recommended to not generate va_arg due to the lack of
13; support for aggregate types, we test simple cases here to ensure they are
14; lowered correctly
15
16define i32 @va1(i8* %fmt, ...) nounwind {
17; RV32I-LABEL: va1:
18; RV32I: # %bb.0:
19; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]20; RV32I-NEXT: sw a1, 20(sp)
21; RV32I-NEXT: sw a7, 44(sp)
22; RV32I-NEXT: sw a6, 40(sp)
23; RV32I-NEXT: sw a5, 36(sp)
24; RV32I-NEXT: sw a4, 32(sp)
25; RV32I-NEXT: sw a3, 28(sp)
26; RV32I-NEXT: sw a2, 24(sp)
27; RV32I-NEXT: addi a0, sp, 24
28; RV32I-NEXT: sw a0, 12(sp)
29; RV32I-NEXT: lw a0, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]30; RV32I-NEXT: addi sp, sp, 48
31; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]32; RV32I-FPELIM-LABEL: va1:
33; RV32I-FPELIM: # %bb.0:
34; RV32I-FPELIM-NEXT: addi sp, sp, -48
35; RV32I-FPELIM-NEXT: sw a1, 20(sp)
36; RV32I-FPELIM-NEXT: sw a7, 44(sp)
37; RV32I-FPELIM-NEXT: sw a6, 40(sp)
38; RV32I-FPELIM-NEXT: sw a5, 36(sp)
39; RV32I-FPELIM-NEXT: sw a4, 32(sp)
40; RV32I-FPELIM-NEXT: sw a3, 28(sp)
41; RV32I-FPELIM-NEXT: sw a2, 24(sp)
42; RV32I-FPELIM-NEXT: addi a0, sp, 24
43; RV32I-FPELIM-NEXT: sw a0, 12(sp)
44; RV32I-FPELIM-NEXT: lw a0, 20(sp)
45; RV32I-FPELIM-NEXT: addi sp, sp, 48
46; RV32I-FPELIM-NEXT: ret
47;
48; RV32I-WITHFP-LABEL: va1:
49; RV32I-WITHFP: # %bb.0:
50; RV32I-WITHFP-NEXT: addi sp, sp, -48
51; RV32I-WITHFP-NEXT: sw ra, 12(sp)
52; RV32I-WITHFP-NEXT: sw s0, 8(sp)
53; RV32I-WITHFP-NEXT: addi s0, sp, 16
54; RV32I-WITHFP-NEXT: sw a1, 4(s0)
55; RV32I-WITHFP-NEXT: sw a7, 28(s0)
56; RV32I-WITHFP-NEXT: sw a6, 24(s0)
57; RV32I-WITHFP-NEXT: sw a5, 20(s0)
58; RV32I-WITHFP-NEXT: sw a4, 16(s0)
59; RV32I-WITHFP-NEXT: sw a3, 12(s0)
60; RV32I-WITHFP-NEXT: sw a2, 8(s0)
61; RV32I-WITHFP-NEXT: addi a0, s0, 8
62; RV32I-WITHFP-NEXT: sw a0, -12(s0)
63; RV32I-WITHFP-NEXT: lw a0, 4(s0)
64; RV32I-WITHFP-NEXT: lw s0, 8(sp)
65; RV32I-WITHFP-NEXT: lw ra, 12(sp)
66; RV32I-WITHFP-NEXT: addi sp, sp, 48
67; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]68 %va = alloca i8*, align 4
69 %1 = bitcast i8** %va to i8*
70 call void @llvm.va_start(i8* %1)
71 %argp.cur = load i8*, i8** %va, align 4
72 %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
73 store i8* %argp.next, i8** %va, align 4
74 %2 = bitcast i8* %argp.cur to i32*
75 %3 = load i32, i32* %2, align 4
76 call void @llvm.va_end(i8* %1)
77 ret i32 %3
78}
79
80define i32 @va1_va_arg(i8* %fmt, ...) nounwind {
81; RV32I-LABEL: va1_va_arg:
82; RV32I: # %bb.0:
83; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]84; RV32I-NEXT: sw a1, 20(sp)
85; RV32I-NEXT: sw a7, 44(sp)
86; RV32I-NEXT: sw a6, 40(sp)
87; RV32I-NEXT: sw a5, 36(sp)
88; RV32I-NEXT: sw a4, 32(sp)
89; RV32I-NEXT: sw a3, 28(sp)
90; RV32I-NEXT: sw a2, 24(sp)
91; RV32I-NEXT: addi a0, sp, 24
92; RV32I-NEXT: sw a0, 12(sp)
93; RV32I-NEXT: lw a0, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]94; RV32I-NEXT: addi sp, sp, 48
95; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]96; RV32I-FPELIM-LABEL: va1_va_arg:
97; RV32I-FPELIM: # %bb.0:
98; RV32I-FPELIM-NEXT: addi sp, sp, -48
99; RV32I-FPELIM-NEXT: sw a1, 20(sp)
100; RV32I-FPELIM-NEXT: sw a7, 44(sp)
101; RV32I-FPELIM-NEXT: sw a6, 40(sp)
102; RV32I-FPELIM-NEXT: sw a5, 36(sp)
103; RV32I-FPELIM-NEXT: sw a4, 32(sp)
104; RV32I-FPELIM-NEXT: sw a3, 28(sp)
105; RV32I-FPELIM-NEXT: sw a2, 24(sp)
106; RV32I-FPELIM-NEXT: addi a0, sp, 24
107; RV32I-FPELIM-NEXT: sw a0, 12(sp)
108; RV32I-FPELIM-NEXT: lw a0, 20(sp)
109; RV32I-FPELIM-NEXT: addi sp, sp, 48
110; RV32I-FPELIM-NEXT: ret
111;
112; RV32I-WITHFP-LABEL: va1_va_arg:
113; RV32I-WITHFP: # %bb.0:
114; RV32I-WITHFP-NEXT: addi sp, sp, -48
115; RV32I-WITHFP-NEXT: sw ra, 12(sp)
116; RV32I-WITHFP-NEXT: sw s0, 8(sp)
117; RV32I-WITHFP-NEXT: addi s0, sp, 16
118; RV32I-WITHFP-NEXT: sw a1, 4(s0)
119; RV32I-WITHFP-NEXT: sw a7, 28(s0)
120; RV32I-WITHFP-NEXT: sw a6, 24(s0)
121; RV32I-WITHFP-NEXT: sw a5, 20(s0)
122; RV32I-WITHFP-NEXT: sw a4, 16(s0)
123; RV32I-WITHFP-NEXT: sw a3, 12(s0)
124; RV32I-WITHFP-NEXT: sw a2, 8(s0)
125; RV32I-WITHFP-NEXT: addi a0, s0, 8
126; RV32I-WITHFP-NEXT: sw a0, -12(s0)
127; RV32I-WITHFP-NEXT: lw a0, 4(s0)
128; RV32I-WITHFP-NEXT: lw s0, 8(sp)
129; RV32I-WITHFP-NEXT: lw ra, 12(sp)
130; RV32I-WITHFP-NEXT: addi sp, sp, 48
131; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]132 %va = alloca i8*, align 4
133 %1 = bitcast i8** %va to i8*
134 call void @llvm.va_start(i8* %1)
135 %2 = va_arg i8** %va, i32
136 call void @llvm.va_end(i8* %1)
137 ret i32 %2
138}
139
140; Ensure the adjustment when restoring the stack pointer using the frame
141; pointer is correct
142define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind {
143; RV32I-LABEL: va1_va_arg_alloca:
144; RV32I: # %bb.0:
145; RV32I-NEXT: addi sp, sp, -48
146; RV32I-NEXT: sw ra, 12(sp)
147; RV32I-NEXT: sw s0, 8(sp)
148; RV32I-NEXT: sw s1, 4(sp)
149; RV32I-NEXT: addi s0, sp, 16
150; RV32I-NEXT: sw a1, 4(s0)
151; RV32I-NEXT: sw a7, 28(s0)
152; RV32I-NEXT: sw a6, 24(s0)
153; RV32I-NEXT: sw a5, 20(s0)
154; RV32I-NEXT: sw a4, 16(s0)
155; RV32I-NEXT: sw a3, 12(s0)
156; RV32I-NEXT: sw a2, 8(s0)
157; RV32I-NEXT: addi a0, s0, 8
158; RV32I-NEXT: sw a0, -16(s0)
159; RV32I-NEXT: lw s1, 4(s0)
160; RV32I-NEXT: addi a0, s1, 15
161; RV32I-NEXT: andi a0, a0, -16
162; RV32I-NEXT: sub a0, sp, a0
163; RV32I-NEXT: mv sp, a0
164; RV32I-NEXT: lui a1, %hi(notdead)
165; RV32I-NEXT: addi a1, a1, %lo(notdead)
166; RV32I-NEXT: jalr a1
167; RV32I-NEXT: mv a0, s1
168; RV32I-NEXT: addi sp, s0, -16
169; RV32I-NEXT: lw s1, 4(sp)
170; RV32I-NEXT: lw s0, 8(sp)
171; RV32I-NEXT: lw ra, 12(sp)
172; RV32I-NEXT: addi sp, sp, 48
173; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]174; RV32I-FPELIM-LABEL: va1_va_arg_alloca:
175; RV32I-FPELIM: # %bb.0:
176; RV32I-FPELIM-NEXT: addi sp, sp, -48
177; RV32I-FPELIM-NEXT: sw ra, 12(sp)
178; RV32I-FPELIM-NEXT: sw s0, 8(sp)
179; RV32I-FPELIM-NEXT: sw s1, 4(sp)
180; RV32I-FPELIM-NEXT: addi s0, sp, 16
181; RV32I-FPELIM-NEXT: sw a1, 4(s0)
182; RV32I-FPELIM-NEXT: sw a7, 28(s0)
183; RV32I-FPELIM-NEXT: sw a6, 24(s0)
184; RV32I-FPELIM-NEXT: sw a5, 20(s0)
185; RV32I-FPELIM-NEXT: sw a4, 16(s0)
186; RV32I-FPELIM-NEXT: sw a3, 12(s0)
187; RV32I-FPELIM-NEXT: sw a2, 8(s0)
188; RV32I-FPELIM-NEXT: addi a0, s0, 8
189; RV32I-FPELIM-NEXT: sw a0, -16(s0)
190; RV32I-FPELIM-NEXT: lw s1, 4(s0)
191; RV32I-FPELIM-NEXT: addi a0, s1, 15
192; RV32I-FPELIM-NEXT: andi a0, a0, -16
193; RV32I-FPELIM-NEXT: sub a0, sp, a0
194; RV32I-FPELIM-NEXT: mv sp, a0
195; RV32I-FPELIM-NEXT: lui a1, %hi(notdead)
196; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead)
197; RV32I-FPELIM-NEXT: jalr a1
198; RV32I-FPELIM-NEXT: mv a0, s1
199; RV32I-FPELIM-NEXT: addi sp, s0, -16
200; RV32I-FPELIM-NEXT: lw s1, 4(sp)
201; RV32I-FPELIM-NEXT: lw s0, 8(sp)
202; RV32I-FPELIM-NEXT: lw ra, 12(sp)
203; RV32I-FPELIM-NEXT: addi sp, sp, 48
204; RV32I-FPELIM-NEXT: ret
205;
206; RV32I-WITHFP-LABEL: va1_va_arg_alloca:
207; RV32I-WITHFP: # %bb.0:
208; RV32I-WITHFP-NEXT: addi sp, sp, -48
209; RV32I-WITHFP-NEXT: sw ra, 12(sp)
210; RV32I-WITHFP-NEXT: sw s0, 8(sp)
211; RV32I-WITHFP-NEXT: sw s1, 4(sp)
212; RV32I-WITHFP-NEXT: addi s0, sp, 16
213; RV32I-WITHFP-NEXT: sw a1, 4(s0)
214; RV32I-WITHFP-NEXT: sw a7, 28(s0)
215; RV32I-WITHFP-NEXT: sw a6, 24(s0)
216; RV32I-WITHFP-NEXT: sw a5, 20(s0)
217; RV32I-WITHFP-NEXT: sw a4, 16(s0)
218; RV32I-WITHFP-NEXT: sw a3, 12(s0)
219; RV32I-WITHFP-NEXT: sw a2, 8(s0)
220; RV32I-WITHFP-NEXT: addi a0, s0, 8
221; RV32I-WITHFP-NEXT: sw a0, -16(s0)
222; RV32I-WITHFP-NEXT: lw s1, 4(s0)
223; RV32I-WITHFP-NEXT: addi a0, s1, 15
224; RV32I-WITHFP-NEXT: andi a0, a0, -16
225; RV32I-WITHFP-NEXT: sub a0, sp, a0
226; RV32I-WITHFP-NEXT: mv sp, a0
227; RV32I-WITHFP-NEXT: lui a1, %hi(notdead)
228; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead)
229; RV32I-WITHFP-NEXT: jalr a1
230; RV32I-WITHFP-NEXT: mv a0, s1
231; RV32I-WITHFP-NEXT: addi sp, s0, -16
232; RV32I-WITHFP-NEXT: lw s1, 4(sp)
233; RV32I-WITHFP-NEXT: lw s0, 8(sp)
234; RV32I-WITHFP-NEXT: lw ra, 12(sp)
235; RV32I-WITHFP-NEXT: addi sp, sp, 48
236; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]237 %va = alloca i8*, align 4
238 %1 = bitcast i8** %va to i8*
239 call void @llvm.va_start(i8* %1)
240 %2 = va_arg i8** %va, i32
241 %3 = alloca i8, i32 %2
242 call void @notdead(i8* %3)
243 call void @llvm.va_end(i8* %1)
244 ret i32 %2
245}
246
247define void @va1_caller() nounwind {
248; RV32I-LABEL: va1_caller:
249; RV32I: # %bb.0:
250; RV32I-NEXT: addi sp, sp, -16
251; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]252; RV32I-NEXT: lui a0, 261888
253; RV32I-NEXT: mv a3, a0
254; RV32I-NEXT: lui a0, %hi(va1)
255; RV32I-NEXT: addi a0, a0, %lo(va1)
256; RV32I-NEXT: addi a4, zero, 2
257; RV32I-NEXT: mv a2, zero
258; RV32I-NEXT: jalr a0
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]259; RV32I-NEXT: lw ra, 12(sp)
260; RV32I-NEXT: addi sp, sp, 16
261; RV32I-NEXT: ret
262; Pass a double, as a float would be promoted by a C/C++ frontend
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]263; RV32I-FPELIM-LABEL: va1_caller:
264; RV32I-FPELIM: # %bb.0:
265; RV32I-FPELIM-NEXT: addi sp, sp, -16
266; RV32I-FPELIM-NEXT: sw ra, 12(sp)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]267; RV32I-FPELIM-NEXT: lui a0, %hi(va1)
268; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1)
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]269; RV32I-FPELIM-NEXT: lui a3, 261888
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]270; RV32I-FPELIM-NEXT: addi a4, zero, 2
271; RV32I-FPELIM-NEXT: mv a2, zero
272; RV32I-FPELIM-NEXT: jalr a0
273; RV32I-FPELIM-NEXT: lw ra, 12(sp)
274; RV32I-FPELIM-NEXT: addi sp, sp, 16
275; RV32I-FPELIM-NEXT: ret
276;
277; RV32I-WITHFP-LABEL: va1_caller:
278; RV32I-WITHFP: # %bb.0:
279; RV32I-WITHFP-NEXT: addi sp, sp, -16
280; RV32I-WITHFP-NEXT: sw ra, 12(sp)
281; RV32I-WITHFP-NEXT: sw s0, 8(sp)
282; RV32I-WITHFP-NEXT: addi s0, sp, 16
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]283; RV32I-WITHFP-NEXT: lui a0, %hi(va1)
284; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1)
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]285; RV32I-WITHFP-NEXT: lui a3, 261888
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]286; RV32I-WITHFP-NEXT: addi a4, zero, 2
287; RV32I-WITHFP-NEXT: mv a2, zero
288; RV32I-WITHFP-NEXT: jalr a0
289; RV32I-WITHFP-NEXT: lw s0, 8(sp)
290; RV32I-WITHFP-NEXT: lw ra, 12(sp)
291; RV32I-WITHFP-NEXT: addi sp, sp, 16
292; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]293 %1 = call i32 (i8*, ...) @va1(i8* undef, double 1.0, i32 2)
294 ret void
295}
296
297; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
298; register pair (where the first register is even-numbered).
299
300define double @va2(i8 *%fmt, ...) nounwind {
301; RV32I-LABEL: va2:
302; RV32I: # %bb.0:
303; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]304; RV32I-NEXT: sw a7, 44(sp)
305; RV32I-NEXT: sw a6, 40(sp)
306; RV32I-NEXT: sw a5, 36(sp)
307; RV32I-NEXT: sw a4, 32(sp)
308; RV32I-NEXT: sw a3, 28(sp)
309; RV32I-NEXT: sw a2, 24(sp)
310; RV32I-NEXT: sw a1, 20(sp)
311; RV32I-NEXT: addi a0, sp, 35
312; RV32I-NEXT: sw a0, 12(sp)
313; RV32I-NEXT: addi a0, sp, 27
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]314; RV32I-NEXT: andi a1, a0, -8
315; RV32I-NEXT: lw a0, 0(a1)
316; RV32I-NEXT: ori a1, a1, 4
317; RV32I-NEXT: lw a1, 0(a1)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]318; RV32I-NEXT: addi sp, sp, 48
319; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]320; RV32I-FPELIM-LABEL: va2:
321; RV32I-FPELIM: # %bb.0:
322; RV32I-FPELIM-NEXT: addi sp, sp, -48
323; RV32I-FPELIM-NEXT: sw a7, 44(sp)
324; RV32I-FPELIM-NEXT: sw a6, 40(sp)
325; RV32I-FPELIM-NEXT: sw a5, 36(sp)
326; RV32I-FPELIM-NEXT: sw a4, 32(sp)
327; RV32I-FPELIM-NEXT: sw a3, 28(sp)
328; RV32I-FPELIM-NEXT: sw a2, 24(sp)
329; RV32I-FPELIM-NEXT: sw a1, 20(sp)
330; RV32I-FPELIM-NEXT: addi a0, sp, 35
331; RV32I-FPELIM-NEXT: sw a0, 12(sp)
332; RV32I-FPELIM-NEXT: addi a0, sp, 27
333; RV32I-FPELIM-NEXT: andi a1, a0, -8
334; RV32I-FPELIM-NEXT: lw a0, 0(a1)
335; RV32I-FPELIM-NEXT: ori a1, a1, 4
336; RV32I-FPELIM-NEXT: lw a1, 0(a1)
337; RV32I-FPELIM-NEXT: addi sp, sp, 48
338; RV32I-FPELIM-NEXT: ret
339;
340; RV32I-WITHFP-LABEL: va2:
341; RV32I-WITHFP: # %bb.0:
342; RV32I-WITHFP-NEXT: addi sp, sp, -48
343; RV32I-WITHFP-NEXT: sw ra, 12(sp)
344; RV32I-WITHFP-NEXT: sw s0, 8(sp)
345; RV32I-WITHFP-NEXT: addi s0, sp, 16
346; RV32I-WITHFP-NEXT: sw a7, 28(s0)
347; RV32I-WITHFP-NEXT: sw a6, 24(s0)
348; RV32I-WITHFP-NEXT: sw a5, 20(s0)
349; RV32I-WITHFP-NEXT: sw a4, 16(s0)
350; RV32I-WITHFP-NEXT: sw a3, 12(s0)
351; RV32I-WITHFP-NEXT: sw a2, 8(s0)
352; RV32I-WITHFP-NEXT: sw a1, 4(s0)
353; RV32I-WITHFP-NEXT: addi a0, s0, 19
354; RV32I-WITHFP-NEXT: sw a0, -12(s0)
355; RV32I-WITHFP-NEXT: addi a0, s0, 11
356; RV32I-WITHFP-NEXT: andi a1, a0, -8
357; RV32I-WITHFP-NEXT: lw a0, 0(a1)
358; RV32I-WITHFP-NEXT: ori a1, a1, 4
359; RV32I-WITHFP-NEXT: lw a1, 0(a1)
360; RV32I-WITHFP-NEXT: lw s0, 8(sp)
361; RV32I-WITHFP-NEXT: lw ra, 12(sp)
362; RV32I-WITHFP-NEXT: addi sp, sp, 48
363; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]364 %va = alloca i8*, align 4
365 %1 = bitcast i8** %va to i8*
366 call void @llvm.va_start(i8* %1)
367 %2 = bitcast i8** %va to i32*
368 %argp.cur = load i32, i32* %2, align 4
369 %3 = add i32 %argp.cur, 7
370 %4 = and i32 %3, -8
371 %argp.cur.aligned = inttoptr i32 %3 to i8*
372 %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 8
373 store i8* %argp.next, i8** %va, align 4
374 %5 = inttoptr i32 %4 to double*
375 %6 = load double, double* %5, align 8
376 call void @llvm.va_end(i8* %1)
377 ret double %6
378}
379
380define double @va2_va_arg(i8 *%fmt, ...) nounwind {
381; RV32I-LABEL: va2_va_arg:
382; RV32I: # %bb.0:
383; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]384; RV32I-NEXT: sw a7, 44(sp)
385; RV32I-NEXT: sw a6, 40(sp)
386; RV32I-NEXT: sw a5, 36(sp)
387; RV32I-NEXT: sw a4, 32(sp)
388; RV32I-NEXT: sw a3, 28(sp)
389; RV32I-NEXT: sw a2, 24(sp)
390; RV32I-NEXT: sw a1, 20(sp)
391; RV32I-NEXT: addi a0, sp, 27
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]392; RV32I-NEXT: andi a0, a0, -8
393; RV32I-NEXT: ori a1, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]394; RV32I-NEXT: sw a1, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]395; RV32I-NEXT: lw a0, 0(a0)
396; RV32I-NEXT: addi a2, a1, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]397; RV32I-NEXT: sw a2, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]398; RV32I-NEXT: lw a1, 0(a1)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]399; RV32I-NEXT: addi sp, sp, 48
400; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]401; RV32I-FPELIM-LABEL: va2_va_arg:
402; RV32I-FPELIM: # %bb.0:
403; RV32I-FPELIM-NEXT: addi sp, sp, -48
404; RV32I-FPELIM-NEXT: sw a7, 44(sp)
405; RV32I-FPELIM-NEXT: sw a6, 40(sp)
406; RV32I-FPELIM-NEXT: sw a5, 36(sp)
407; RV32I-FPELIM-NEXT: sw a4, 32(sp)
408; RV32I-FPELIM-NEXT: sw a3, 28(sp)
409; RV32I-FPELIM-NEXT: sw a2, 24(sp)
410; RV32I-FPELIM-NEXT: sw a1, 20(sp)
411; RV32I-FPELIM-NEXT: addi a0, sp, 27
412; RV32I-FPELIM-NEXT: andi a0, a0, -8
413; RV32I-FPELIM-NEXT: ori a1, a0, 4
414; RV32I-FPELIM-NEXT: sw a1, 12(sp)
415; RV32I-FPELIM-NEXT: lw a0, 0(a0)
416; RV32I-FPELIM-NEXT: addi a2, a1, 4
417; RV32I-FPELIM-NEXT: sw a2, 12(sp)
418; RV32I-FPELIM-NEXT: lw a1, 0(a1)
419; RV32I-FPELIM-NEXT: addi sp, sp, 48
420; RV32I-FPELIM-NEXT: ret
421;
422; RV32I-WITHFP-LABEL: va2_va_arg:
423; RV32I-WITHFP: # %bb.0:
424; RV32I-WITHFP-NEXT: addi sp, sp, -48
425; RV32I-WITHFP-NEXT: sw ra, 12(sp)
426; RV32I-WITHFP-NEXT: sw s0, 8(sp)
427; RV32I-WITHFP-NEXT: addi s0, sp, 16
428; RV32I-WITHFP-NEXT: sw a7, 28(s0)
429; RV32I-WITHFP-NEXT: sw a6, 24(s0)
430; RV32I-WITHFP-NEXT: sw a5, 20(s0)
431; RV32I-WITHFP-NEXT: sw a4, 16(s0)
432; RV32I-WITHFP-NEXT: sw a3, 12(s0)
433; RV32I-WITHFP-NEXT: sw a2, 8(s0)
434; RV32I-WITHFP-NEXT: sw a1, 4(s0)
435; RV32I-WITHFP-NEXT: addi a0, s0, 11
436; RV32I-WITHFP-NEXT: andi a0, a0, -8
437; RV32I-WITHFP-NEXT: ori a1, a0, 4
438; RV32I-WITHFP-NEXT: sw a1, -12(s0)
439; RV32I-WITHFP-NEXT: lw a0, 0(a0)
440; RV32I-WITHFP-NEXT: addi a2, a1, 4
441; RV32I-WITHFP-NEXT: sw a2, -12(s0)
442; RV32I-WITHFP-NEXT: lw a1, 0(a1)
443; RV32I-WITHFP-NEXT: lw s0, 8(sp)
444; RV32I-WITHFP-NEXT: lw ra, 12(sp)
445; RV32I-WITHFP-NEXT: addi sp, sp, 48
446; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]447 %va = alloca i8*, align 4
448 %1 = bitcast i8** %va to i8*
449 call void @llvm.va_start(i8* %1)
450 %2 = va_arg i8** %va, double
451 call void @llvm.va_end(i8* %1)
452 ret double %2
453}
454
455define void @va2_caller() nounwind {
456; RV32I-LABEL: va2_caller:
457; RV32I: # %bb.0:
458; RV32I-NEXT: addi sp, sp, -16
459; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]460; RV32I-NEXT: lui a0, 261888
461; RV32I-NEXT: mv a3, a0
462; RV32I-NEXT: lui a0, %hi(va2)
463; RV32I-NEXT: addi a0, a0, %lo(va2)
464; RV32I-NEXT: mv a2, zero
465; RV32I-NEXT: jalr a0
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]466; RV32I-NEXT: lw ra, 12(sp)
467; RV32I-NEXT: addi sp, sp, 16
468; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]469; RV32I-FPELIM-LABEL: va2_caller:
470; RV32I-FPELIM: # %bb.0:
471; RV32I-FPELIM-NEXT: addi sp, sp, -16
472; RV32I-FPELIM-NEXT: sw ra, 12(sp)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]473; RV32I-FPELIM-NEXT: lui a0, %hi(va2)
474; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2)
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]475; RV32I-FPELIM-NEXT: lui a3, 261888
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]476; RV32I-FPELIM-NEXT: mv a2, zero
477; RV32I-FPELIM-NEXT: jalr a0
478; RV32I-FPELIM-NEXT: lw ra, 12(sp)
479; RV32I-FPELIM-NEXT: addi sp, sp, 16
480; RV32I-FPELIM-NEXT: ret
481;
482; RV32I-WITHFP-LABEL: va2_caller:
483; RV32I-WITHFP: # %bb.0:
484; RV32I-WITHFP-NEXT: addi sp, sp, -16
485; RV32I-WITHFP-NEXT: sw ra, 12(sp)
486; RV32I-WITHFP-NEXT: sw s0, 8(sp)
487; RV32I-WITHFP-NEXT: addi s0, sp, 16
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]488; RV32I-WITHFP-NEXT: lui a0, %hi(va2)
489; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2)
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]490; RV32I-WITHFP-NEXT: lui a3, 261888
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]491; RV32I-WITHFP-NEXT: mv a2, zero
492; RV32I-WITHFP-NEXT: jalr a0
493; RV32I-WITHFP-NEXT: lw s0, 8(sp)
494; RV32I-WITHFP-NEXT: lw ra, 12(sp)
495; RV32I-WITHFP-NEXT: addi sp, sp, 16
496; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]497 %1 = call double (i8*, ...) @va2(i8* undef, double 1.000000e+00)
498 ret void
499}
500
501; Ensure a named double argument is passed in a1 and a2, while the vararg
502; double is passed in a4 and a5 (rather than a3 and a4)
503
504define double @va3(i32 %a, double %b, ...) nounwind {
505; RV32I-LABEL: va3:
506; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]507; RV32I-NEXT: addi sp, sp, -32
508; RV32I-NEXT: sw ra, 4(sp)
509; RV32I-NEXT: sw a7, 28(sp)
510; RV32I-NEXT: sw a6, 24(sp)
511; RV32I-NEXT: sw a5, 20(sp)
512; RV32I-NEXT: sw a4, 16(sp)
513; RV32I-NEXT: sw a3, 12(sp)
514; RV32I-NEXT: addi a0, sp, 27
515; RV32I-NEXT: sw a0, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]516; RV32I-NEXT: lui a0, %hi(__adddf3)
517; RV32I-NEXT: addi a5, a0, %lo(__adddf3)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]518; RV32I-NEXT: addi a0, sp, 19
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]519; RV32I-NEXT: andi a0, a0, -8
520; RV32I-NEXT: lw a4, 0(a0)
521; RV32I-NEXT: ori a0, a0, 4
522; RV32I-NEXT: lw a3, 0(a0)
523; RV32I-NEXT: mv a0, a1
524; RV32I-NEXT: mv a1, a2
525; RV32I-NEXT: mv a2, a4
526; RV32I-NEXT: jalr a5
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]527; RV32I-NEXT: lw ra, 4(sp)
528; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]529; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]530; RV32I-FPELIM-LABEL: va3:
531; RV32I-FPELIM: # %bb.0:
532; RV32I-FPELIM-NEXT: addi sp, sp, -32
533; RV32I-FPELIM-NEXT: sw ra, 4(sp)
534; RV32I-FPELIM-NEXT: sw a7, 28(sp)
535; RV32I-FPELIM-NEXT: sw a6, 24(sp)
536; RV32I-FPELIM-NEXT: sw a5, 20(sp)
537; RV32I-FPELIM-NEXT: sw a4, 16(sp)
538; RV32I-FPELIM-NEXT: sw a3, 12(sp)
539; RV32I-FPELIM-NEXT: addi a0, sp, 27
540; RV32I-FPELIM-NEXT: sw a0, 0(sp)
541; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
542; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
543; RV32I-FPELIM-NEXT: addi a0, sp, 19
544; RV32I-FPELIM-NEXT: andi a0, a0, -8
545; RV32I-FPELIM-NEXT: lw a4, 0(a0)
546; RV32I-FPELIM-NEXT: ori a0, a0, 4
547; RV32I-FPELIM-NEXT: lw a3, 0(a0)
548; RV32I-FPELIM-NEXT: mv a0, a1
549; RV32I-FPELIM-NEXT: mv a1, a2
550; RV32I-FPELIM-NEXT: mv a2, a4
551; RV32I-FPELIM-NEXT: jalr a5
552; RV32I-FPELIM-NEXT: lw ra, 4(sp)
553; RV32I-FPELIM-NEXT: addi sp, sp, 32
554; RV32I-FPELIM-NEXT: ret
555;
556; RV32I-WITHFP-LABEL: va3:
557; RV32I-WITHFP: # %bb.0:
558; RV32I-WITHFP-NEXT: addi sp, sp, -48
559; RV32I-WITHFP-NEXT: sw ra, 20(sp)
560; RV32I-WITHFP-NEXT: sw s0, 16(sp)
561; RV32I-WITHFP-NEXT: addi s0, sp, 24
562; RV32I-WITHFP-NEXT: sw a7, 20(s0)
563; RV32I-WITHFP-NEXT: sw a6, 16(s0)
564; RV32I-WITHFP-NEXT: sw a5, 12(s0)
565; RV32I-WITHFP-NEXT: sw a4, 8(s0)
566; RV32I-WITHFP-NEXT: sw a3, 4(s0)
567; RV32I-WITHFP-NEXT: addi a0, s0, 19
568; RV32I-WITHFP-NEXT: sw a0, -12(s0)
569; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
570; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
571; RV32I-WITHFP-NEXT: addi a0, s0, 11
572; RV32I-WITHFP-NEXT: andi a0, a0, -8
573; RV32I-WITHFP-NEXT: lw a4, 0(a0)
574; RV32I-WITHFP-NEXT: ori a0, a0, 4
575; RV32I-WITHFP-NEXT: lw a3, 0(a0)
576; RV32I-WITHFP-NEXT: mv a0, a1
577; RV32I-WITHFP-NEXT: mv a1, a2
578; RV32I-WITHFP-NEXT: mv a2, a4
579; RV32I-WITHFP-NEXT: jalr a5
580; RV32I-WITHFP-NEXT: lw s0, 16(sp)
581; RV32I-WITHFP-NEXT: lw ra, 20(sp)
582; RV32I-WITHFP-NEXT: addi sp, sp, 48
583; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]584 %va = alloca i8*, align 4
585 %1 = bitcast i8** %va to i8*
586 call void @llvm.va_start(i8* %1)
587 %2 = bitcast i8** %va to i32*
588 %argp.cur = load i32, i32* %2, align 4
589 %3 = add i32 %argp.cur, 7
590 %4 = and i32 %3, -8
591 %argp.cur.aligned = inttoptr i32 %3 to i8*
592 %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 8
593 store i8* %argp.next, i8** %va, align 4
594 %5 = inttoptr i32 %4 to double*
595 %6 = load double, double* %5, align 8
596 call void @llvm.va_end(i8* %1)
597 %7 = fadd double %b, %6
598 ret double %7
599}
600
601define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
602; RV32I-LABEL: va3_va_arg:
603; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]604; RV32I-NEXT: addi sp, sp, -32
605; RV32I-NEXT: sw ra, 4(sp)
606; RV32I-NEXT: sw a7, 28(sp)
607; RV32I-NEXT: sw a6, 24(sp)
608; RV32I-NEXT: sw a5, 20(sp)
609; RV32I-NEXT: sw a4, 16(sp)
610; RV32I-NEXT: sw a3, 12(sp)
611; RV32I-NEXT: addi a0, sp, 19
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]612; RV32I-NEXT: andi a0, a0, -8
613; RV32I-NEXT: ori a3, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]614; RV32I-NEXT: sw a3, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]615; RV32I-NEXT: lw a4, 0(a0)
616; RV32I-NEXT: addi a0, a3, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]617; RV32I-NEXT: sw a0, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]618; RV32I-NEXT: lui a0, %hi(__adddf3)
619; RV32I-NEXT: addi a5, a0, %lo(__adddf3)
620; RV32I-NEXT: lw a3, 0(a3)
621; RV32I-NEXT: mv a0, a1
622; RV32I-NEXT: mv a1, a2
623; RV32I-NEXT: mv a2, a4
624; RV32I-NEXT: jalr a5
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]625; RV32I-NEXT: lw ra, 4(sp)
626; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]627; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]628; RV32I-FPELIM-LABEL: va3_va_arg:
629; RV32I-FPELIM: # %bb.0:
630; RV32I-FPELIM-NEXT: addi sp, sp, -32
631; RV32I-FPELIM-NEXT: sw ra, 4(sp)
632; RV32I-FPELIM-NEXT: sw a7, 28(sp)
633; RV32I-FPELIM-NEXT: sw a6, 24(sp)
634; RV32I-FPELIM-NEXT: sw a5, 20(sp)
635; RV32I-FPELIM-NEXT: sw a4, 16(sp)
636; RV32I-FPELIM-NEXT: sw a3, 12(sp)
637; RV32I-FPELIM-NEXT: addi a0, sp, 19
638; RV32I-FPELIM-NEXT: andi a0, a0, -8
639; RV32I-FPELIM-NEXT: ori a3, a0, 4
640; RV32I-FPELIM-NEXT: sw a3, 0(sp)
641; RV32I-FPELIM-NEXT: lw a4, 0(a0)
642; RV32I-FPELIM-NEXT: addi a0, a3, 4
643; RV32I-FPELIM-NEXT: sw a0, 0(sp)
644; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
645; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
646; RV32I-FPELIM-NEXT: lw a3, 0(a3)
647; RV32I-FPELIM-NEXT: mv a0, a1
648; RV32I-FPELIM-NEXT: mv a1, a2
649; RV32I-FPELIM-NEXT: mv a2, a4
650; RV32I-FPELIM-NEXT: jalr a5
651; RV32I-FPELIM-NEXT: lw ra, 4(sp)
652; RV32I-FPELIM-NEXT: addi sp, sp, 32
653; RV32I-FPELIM-NEXT: ret
654;
655; RV32I-WITHFP-LABEL: va3_va_arg:
656; RV32I-WITHFP: # %bb.0:
657; RV32I-WITHFP-NEXT: addi sp, sp, -48
658; RV32I-WITHFP-NEXT: sw ra, 20(sp)
659; RV32I-WITHFP-NEXT: sw s0, 16(sp)
660; RV32I-WITHFP-NEXT: addi s0, sp, 24
661; RV32I-WITHFP-NEXT: sw a7, 20(s0)
662; RV32I-WITHFP-NEXT: sw a6, 16(s0)
663; RV32I-WITHFP-NEXT: sw a5, 12(s0)
664; RV32I-WITHFP-NEXT: sw a4, 8(s0)
665; RV32I-WITHFP-NEXT: sw a3, 4(s0)
666; RV32I-WITHFP-NEXT: addi a0, s0, 11
667; RV32I-WITHFP-NEXT: andi a0, a0, -8
668; RV32I-WITHFP-NEXT: ori a3, a0, 4
669; RV32I-WITHFP-NEXT: sw a3, -12(s0)
670; RV32I-WITHFP-NEXT: lw a4, 0(a0)
671; RV32I-WITHFP-NEXT: addi a0, a3, 4
672; RV32I-WITHFP-NEXT: sw a0, -12(s0)
673; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
674; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
675; RV32I-WITHFP-NEXT: lw a3, 0(a3)
676; RV32I-WITHFP-NEXT: mv a0, a1
677; RV32I-WITHFP-NEXT: mv a1, a2
678; RV32I-WITHFP-NEXT: mv a2, a4
679; RV32I-WITHFP-NEXT: jalr a5
680; RV32I-WITHFP-NEXT: lw s0, 16(sp)
681; RV32I-WITHFP-NEXT: lw ra, 20(sp)
682; RV32I-WITHFP-NEXT: addi sp, sp, 48
683; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]684 %va = alloca i8*, align 4
685 %1 = bitcast i8** %va to i8*
686 call void @llvm.va_start(i8* %1)
687 %2 = va_arg i8** %va, double
688 call void @llvm.va_end(i8* %1)
689 %3 = fadd double %b, %2
690 ret double %3
691}
692
693define void @va3_caller() nounwind {
694; RV32I-LABEL: va3_caller:
695; RV32I: # %bb.0:
696; RV32I-NEXT: addi sp, sp, -16
697; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]698; RV32I-NEXT: lui a0, 261888
699; RV32I-NEXT: mv a2, a0
700; RV32I-NEXT: lui a0, 262144
701; RV32I-NEXT: mv a5, a0
702; RV32I-NEXT: lui a0, %hi(va3)
703; RV32I-NEXT: addi a3, a0, %lo(va3)
704; RV32I-NEXT: addi a0, zero, 2
705; RV32I-NEXT: mv a1, zero
706; RV32I-NEXT: mv a4, zero
707; RV32I-NEXT: jalr a3
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]708; RV32I-NEXT: lw ra, 12(sp)
709; RV32I-NEXT: addi sp, sp, 16
710; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]711; RV32I-FPELIM-LABEL: va3_caller:
712; RV32I-FPELIM: # %bb.0:
713; RV32I-FPELIM-NEXT: addi sp, sp, -16
714; RV32I-FPELIM-NEXT: sw ra, 12(sp)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]715; RV32I-FPELIM-NEXT: lui a0, %hi(va3)
716; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3)
717; RV32I-FPELIM-NEXT: addi a0, zero, 2
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]718; RV32I-FPELIM-NEXT: lui a2, 261888
719; RV32I-FPELIM-NEXT: lui a5, 262144
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]720; RV32I-FPELIM-NEXT: mv a1, zero
721; RV32I-FPELIM-NEXT: mv a4, zero
722; RV32I-FPELIM-NEXT: jalr a3
723; RV32I-FPELIM-NEXT: lw ra, 12(sp)
724; RV32I-FPELIM-NEXT: addi sp, sp, 16
725; RV32I-FPELIM-NEXT: ret
726;
727; RV32I-WITHFP-LABEL: va3_caller:
728; RV32I-WITHFP: # %bb.0:
729; RV32I-WITHFP-NEXT: addi sp, sp, -16
730; RV32I-WITHFP-NEXT: sw ra, 12(sp)
731; RV32I-WITHFP-NEXT: sw s0, 8(sp)
732; RV32I-WITHFP-NEXT: addi s0, sp, 16
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]733; RV32I-WITHFP-NEXT: lui a0, %hi(va3)
734; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3)
735; RV32I-WITHFP-NEXT: addi a0, zero, 2
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]736; RV32I-WITHFP-NEXT: lui a2, 261888
737; RV32I-WITHFP-NEXT: lui a5, 262144
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]738; RV32I-WITHFP-NEXT: mv a1, zero
739; RV32I-WITHFP-NEXT: mv a4, zero
740; RV32I-WITHFP-NEXT: jalr a3
741; RV32I-WITHFP-NEXT: lw s0, 8(sp)
742; RV32I-WITHFP-NEXT: lw ra, 12(sp)
743; RV32I-WITHFP-NEXT: addi sp, sp, 16
744; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]745 %1 = call double (i32, double, ...) @va3(i32 2, double 1.000000e+00, double 2.000000e+00)
746 ret void
747}
748
749declare void @llvm.va_copy(i8*, i8*)
750
751define i32 @va4_va_copy(i32 %argno, ...) nounwind {
752; RV32I-LABEL: va4_va_copy:
753; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]754; RV32I-NEXT: addi sp, sp, -48
755; RV32I-NEXT: sw ra, 12(sp)
756; RV32I-NEXT: sw s1, 8(sp)
757; RV32I-NEXT: sw a1, 20(sp)
758; RV32I-NEXT: sw a7, 44(sp)
759; RV32I-NEXT: sw a6, 40(sp)
760; RV32I-NEXT: sw a5, 36(sp)
761; RV32I-NEXT: sw a4, 32(sp)
762; RV32I-NEXT: sw a3, 28(sp)
763; RV32I-NEXT: sw a2, 24(sp)
764; RV32I-NEXT: addi a0, sp, 24
765; RV32I-NEXT: sw a0, 4(sp)
766; RV32I-NEXT: sw a0, 0(sp)
767; RV32I-NEXT: lw s1, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]768; RV32I-NEXT: lui a1, %hi(notdead)
769; RV32I-NEXT: addi a1, a1, %lo(notdead)
770; RV32I-NEXT: jalr a1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]771; RV32I-NEXT: lw a0, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]772; RV32I-NEXT: addi a0, a0, 3
773; RV32I-NEXT: andi a0, a0, -4
774; RV32I-NEXT: addi a1, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]775; RV32I-NEXT: sw a1, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]776; RV32I-NEXT: lw a1, 0(a0)
777; RV32I-NEXT: addi a0, a0, 7
778; RV32I-NEXT: andi a0, a0, -4
779; RV32I-NEXT: addi a2, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]780; RV32I-NEXT: sw a2, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]781; RV32I-NEXT: lw a2, 0(a0)
782; RV32I-NEXT: addi a0, a0, 7
783; RV32I-NEXT: andi a0, a0, -4
784; RV32I-NEXT: addi a3, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]785; RV32I-NEXT: sw a3, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]786; RV32I-NEXT: add a1, a1, s1
787; RV32I-NEXT: add a1, a1, a2
788; RV32I-NEXT: lw a0, 0(a0)
789; RV32I-NEXT: add a0, a1, a0
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]790; RV32I-NEXT: lw s1, 8(sp)
791; RV32I-NEXT: lw ra, 12(sp)
792; RV32I-NEXT: addi sp, sp, 48
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]793; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]794; RV32I-FPELIM-LABEL: va4_va_copy:
795; RV32I-FPELIM: # %bb.0:
796; RV32I-FPELIM-NEXT: addi sp, sp, -48
797; RV32I-FPELIM-NEXT: sw ra, 12(sp)
798; RV32I-FPELIM-NEXT: sw s1, 8(sp)
799; RV32I-FPELIM-NEXT: sw a1, 20(sp)
800; RV32I-FPELIM-NEXT: sw a7, 44(sp)
801; RV32I-FPELIM-NEXT: sw a6, 40(sp)
802; RV32I-FPELIM-NEXT: sw a5, 36(sp)
803; RV32I-FPELIM-NEXT: sw a4, 32(sp)
804; RV32I-FPELIM-NEXT: sw a3, 28(sp)
805; RV32I-FPELIM-NEXT: sw a2, 24(sp)
806; RV32I-FPELIM-NEXT: addi a0, sp, 24
807; RV32I-FPELIM-NEXT: sw a0, 4(sp)
808; RV32I-FPELIM-NEXT: sw a0, 0(sp)
809; RV32I-FPELIM-NEXT: lw s1, 20(sp)
810; RV32I-FPELIM-NEXT: lui a1, %hi(notdead)
811; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead)
812; RV32I-FPELIM-NEXT: jalr a1
813; RV32I-FPELIM-NEXT: lw a0, 4(sp)
814; RV32I-FPELIM-NEXT: addi a0, a0, 3
815; RV32I-FPELIM-NEXT: andi a0, a0, -4
816; RV32I-FPELIM-NEXT: addi a1, a0, 4
817; RV32I-FPELIM-NEXT: sw a1, 4(sp)
818; RV32I-FPELIM-NEXT: lw a1, 0(a0)
819; RV32I-FPELIM-NEXT: addi a0, a0, 7
820; RV32I-FPELIM-NEXT: andi a0, a0, -4
821; RV32I-FPELIM-NEXT: addi a2, a0, 4
822; RV32I-FPELIM-NEXT: sw a2, 4(sp)
823; RV32I-FPELIM-NEXT: lw a2, 0(a0)
824; RV32I-FPELIM-NEXT: addi a0, a0, 7
825; RV32I-FPELIM-NEXT: andi a0, a0, -4
826; RV32I-FPELIM-NEXT: addi a3, a0, 4
827; RV32I-FPELIM-NEXT: sw a3, 4(sp)
828; RV32I-FPELIM-NEXT: add a1, a1, s1
829; RV32I-FPELIM-NEXT: add a1, a1, a2
830; RV32I-FPELIM-NEXT: lw a0, 0(a0)
831; RV32I-FPELIM-NEXT: add a0, a1, a0
832; RV32I-FPELIM-NEXT: lw s1, 8(sp)
833; RV32I-FPELIM-NEXT: lw ra, 12(sp)
834; RV32I-FPELIM-NEXT: addi sp, sp, 48
835; RV32I-FPELIM-NEXT: ret
836;
837; RV32I-WITHFP-LABEL: va4_va_copy:
838; RV32I-WITHFP: # %bb.0:
839; RV32I-WITHFP-NEXT: addi sp, sp, -64
840; RV32I-WITHFP-NEXT: sw ra, 28(sp)
841; RV32I-WITHFP-NEXT: sw s0, 24(sp)
842; RV32I-WITHFP-NEXT: sw s1, 20(sp)
843; RV32I-WITHFP-NEXT: addi s0, sp, 32
844; RV32I-WITHFP-NEXT: sw a1, 4(s0)
845; RV32I-WITHFP-NEXT: sw a7, 28(s0)
846; RV32I-WITHFP-NEXT: sw a6, 24(s0)
847; RV32I-WITHFP-NEXT: sw a5, 20(s0)
848; RV32I-WITHFP-NEXT: sw a4, 16(s0)
849; RV32I-WITHFP-NEXT: sw a3, 12(s0)
850; RV32I-WITHFP-NEXT: sw a2, 8(s0)
851; RV32I-WITHFP-NEXT: addi a0, s0, 8
852; RV32I-WITHFP-NEXT: sw a0, -16(s0)
853; RV32I-WITHFP-NEXT: sw a0, -20(s0)
854; RV32I-WITHFP-NEXT: lw s1, 4(s0)
855; RV32I-WITHFP-NEXT: lui a1, %hi(notdead)
856; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead)
857; RV32I-WITHFP-NEXT: jalr a1
858; RV32I-WITHFP-NEXT: lw a0, -16(s0)
859; RV32I-WITHFP-NEXT: addi a0, a0, 3
860; RV32I-WITHFP-NEXT: andi a0, a0, -4
861; RV32I-WITHFP-NEXT: addi a1, a0, 4
862; RV32I-WITHFP-NEXT: sw a1, -16(s0)
863; RV32I-WITHFP-NEXT: lw a1, 0(a0)
864; RV32I-WITHFP-NEXT: addi a0, a0, 7
865; RV32I-WITHFP-NEXT: andi a0, a0, -4
866; RV32I-WITHFP-NEXT: addi a2, a0, 4
867; RV32I-WITHFP-NEXT: sw a2, -16(s0)
868; RV32I-WITHFP-NEXT: lw a2, 0(a0)
869; RV32I-WITHFP-NEXT: addi a0, a0, 7
870; RV32I-WITHFP-NEXT: andi a0, a0, -4
871; RV32I-WITHFP-NEXT: addi a3, a0, 4
872; RV32I-WITHFP-NEXT: sw a3, -16(s0)
873; RV32I-WITHFP-NEXT: add a1, a1, s1
874; RV32I-WITHFP-NEXT: add a1, a1, a2
875; RV32I-WITHFP-NEXT: lw a0, 0(a0)
876; RV32I-WITHFP-NEXT: add a0, a1, a0
877; RV32I-WITHFP-NEXT: lw s1, 20(sp)
878; RV32I-WITHFP-NEXT: lw s0, 24(sp)
879; RV32I-WITHFP-NEXT: lw ra, 28(sp)
880; RV32I-WITHFP-NEXT: addi sp, sp, 64
881; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]882 %vargs = alloca i8*, align 4
883 %wargs = alloca i8*, align 4
884 %1 = bitcast i8** %vargs to i8*
885 %2 = bitcast i8** %wargs to i8*
886 call void @llvm.va_start(i8* %1)
887 %3 = va_arg i8** %vargs, i32
888 call void @llvm.va_copy(i8* %2, i8* %1)
889 %4 = load i8*, i8** %wargs, align 4
890 call void @notdead(i8* %4)
891 %5 = va_arg i8** %vargs, i32
892 %6 = va_arg i8** %vargs, i32
893 %7 = va_arg i8** %vargs, i32
894 call void @llvm.va_end(i8* %1)
895 call void @llvm.va_end(i8* %2)
896 %add1 = add i32 %5, %3
897 %add2 = add i32 %add1, %6
898 %add3 = add i32 %add2, %7
899 ret i32 %add3
900}
901
902; Check 2x*xlen values are aligned appropriately when passed on the stack in a vararg call
903
904define i32 @va5_aligned_stack_callee(i32 %a, ...) nounwind {
905; RV32I-LABEL: va5_aligned_stack_callee:
906; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]907; RV32I-NEXT: addi sp, sp, -32
908; RV32I-NEXT: sw a7, 28(sp)
909; RV32I-NEXT: sw a6, 24(sp)
910; RV32I-NEXT: sw a5, 20(sp)
911; RV32I-NEXT: sw a4, 16(sp)
912; RV32I-NEXT: sw a3, 12(sp)
913; RV32I-NEXT: sw a2, 8(sp)
914; RV32I-NEXT: sw a1, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]915; RV32I-NEXT: addi a0, zero, 1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]916; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]917; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]918; RV32I-FPELIM-LABEL: va5_aligned_stack_callee:
919; RV32I-FPELIM: # %bb.0:
920; RV32I-FPELIM-NEXT: addi sp, sp, -32
921; RV32I-FPELIM-NEXT: sw a7, 28(sp)
922; RV32I-FPELIM-NEXT: sw a6, 24(sp)
923; RV32I-FPELIM-NEXT: sw a5, 20(sp)
924; RV32I-FPELIM-NEXT: sw a4, 16(sp)
925; RV32I-FPELIM-NEXT: sw a3, 12(sp)
926; RV32I-FPELIM-NEXT: sw a2, 8(sp)
927; RV32I-FPELIM-NEXT: sw a1, 4(sp)
928; RV32I-FPELIM-NEXT: addi a0, zero, 1
929; RV32I-FPELIM-NEXT: addi sp, sp, 32
930; RV32I-FPELIM-NEXT: ret
931;
932; RV32I-WITHFP-LABEL: va5_aligned_stack_callee:
933; RV32I-WITHFP: # %bb.0:
934; RV32I-WITHFP-NEXT: addi sp, sp, -48
935; RV32I-WITHFP-NEXT: sw ra, 12(sp)
936; RV32I-WITHFP-NEXT: sw s0, 8(sp)
937; RV32I-WITHFP-NEXT: addi s0, sp, 16
938; RV32I-WITHFP-NEXT: sw a7, 28(s0)
939; RV32I-WITHFP-NEXT: sw a6, 24(s0)
940; RV32I-WITHFP-NEXT: sw a5, 20(s0)
941; RV32I-WITHFP-NEXT: sw a4, 16(s0)
942; RV32I-WITHFP-NEXT: sw a3, 12(s0)
943; RV32I-WITHFP-NEXT: sw a2, 8(s0)
944; RV32I-WITHFP-NEXT: sw a1, 4(s0)
945; RV32I-WITHFP-NEXT: addi a0, zero, 1
946; RV32I-WITHFP-NEXT: lw s0, 8(sp)
947; RV32I-WITHFP-NEXT: lw ra, 12(sp)
948; RV32I-WITHFP-NEXT: addi sp, sp, 48
949; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]950 ret i32 1
951}
952
953define void @va5_aligned_stack_caller() nounwind {
954; The double should be 8-byte aligned on the stack, but the two-element array
955; should only be 4-byte aligned
956; RV32I-LABEL: va5_aligned_stack_caller:
957; RV32I: # %bb.0:
958; RV32I-NEXT: addi sp, sp, -64
959; RV32I-NEXT: sw ra, 60(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]960; RV32I-NEXT: addi a0, zero, 17
961; RV32I-NEXT: sw a0, 24(sp)
962; RV32I-NEXT: addi a0, zero, 16
963; RV32I-NEXT: sw a0, 20(sp)
964; RV32I-NEXT: addi a0, zero, 15
965; RV32I-NEXT: sw a0, 16(sp)
966; RV32I-NEXT: lui a0, 262236
967; RV32I-NEXT: addi a0, a0, 655
968; RV32I-NEXT: sw a0, 12(sp)
969; RV32I-NEXT: lui a0, 377487
970; RV32I-NEXT: addi a0, a0, 1475
971; RV32I-NEXT: sw a0, 8(sp)
972; RV32I-NEXT: addi a0, zero, 14
973; RV32I-NEXT: sw a0, 0(sp)
974; RV32I-NEXT: lui a0, 262153
975; RV32I-NEXT: addi a0, a0, 491
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]976; RV32I-NEXT: sw a0, 44(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]977; RV32I-NEXT: lui a0, 545260
978; RV32I-NEXT: addi a0, a0, -1967
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]979; RV32I-NEXT: sw a0, 40(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]980; RV32I-NEXT: lui a0, 964690
981; RV32I-NEXT: addi a0, a0, -328
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]982; RV32I-NEXT: sw a0, 36(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]983; RV32I-NEXT: lui a0, 335544
984; RV32I-NEXT: addi a0, a0, 1311
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]985; RV32I-NEXT: sw a0, 32(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]986; RV32I-NEXT: lui a0, 688509
987; RV32I-NEXT: addi a6, a0, -2048
988; RV32I-NEXT: lui a0, %hi(va5_aligned_stack_callee)
989; RV32I-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
990; RV32I-NEXT: addi a0, zero, 1
991; RV32I-NEXT: addi a1, zero, 11
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]992; RV32I-NEXT: addi a2, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]993; RV32I-NEXT: addi a3, zero, 12
994; RV32I-NEXT: addi a4, zero, 13
995; RV32I-NEXT: addi a7, zero, 4
996; RV32I-NEXT: jalr a5
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]997; RV32I-NEXT: lw ra, 60(sp)
998; RV32I-NEXT: addi sp, sp, 64
999; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1000; RV32I-FPELIM-LABEL: va5_aligned_stack_caller:
1001; RV32I-FPELIM: # %bb.0:
1002; RV32I-FPELIM-NEXT: addi sp, sp, -64
1003; RV32I-FPELIM-NEXT: sw ra, 60(sp)
1004; RV32I-FPELIM-NEXT: addi a0, zero, 17
1005; RV32I-FPELIM-NEXT: sw a0, 24(sp)
1006; RV32I-FPELIM-NEXT: addi a0, zero, 16
1007; RV32I-FPELIM-NEXT: sw a0, 20(sp)
1008; RV32I-FPELIM-NEXT: addi a0, zero, 15
1009; RV32I-FPELIM-NEXT: sw a0, 16(sp)
1010; RV32I-FPELIM-NEXT: lui a0, 262236
1011; RV32I-FPELIM-NEXT: addi a0, a0, 655
1012; RV32I-FPELIM-NEXT: sw a0, 12(sp)
1013; RV32I-FPELIM-NEXT: lui a0, 377487
1014; RV32I-FPELIM-NEXT: addi a0, a0, 1475
1015; RV32I-FPELIM-NEXT: sw a0, 8(sp)
1016; RV32I-FPELIM-NEXT: addi a0, zero, 14
1017; RV32I-FPELIM-NEXT: sw a0, 0(sp)
1018; RV32I-FPELIM-NEXT: lui a0, 262153
1019; RV32I-FPELIM-NEXT: addi a0, a0, 491
1020; RV32I-FPELIM-NEXT: sw a0, 44(sp)
1021; RV32I-FPELIM-NEXT: lui a0, 545260
1022; RV32I-FPELIM-NEXT: addi a0, a0, -1967
1023; RV32I-FPELIM-NEXT: sw a0, 40(sp)
1024; RV32I-FPELIM-NEXT: lui a0, 964690
1025; RV32I-FPELIM-NEXT: addi a0, a0, -328
1026; RV32I-FPELIM-NEXT: sw a0, 36(sp)
1027; RV32I-FPELIM-NEXT: lui a0, 335544
1028; RV32I-FPELIM-NEXT: addi a0, a0, 1311
1029; RV32I-FPELIM-NEXT: sw a0, 32(sp)
Alex Bradbury099c7202018-04-18 19:02:31 +0000[diff] [blame]1030; RV32I-FPELIM-NEXT: lui a0, 688509
1031; RV32I-FPELIM-NEXT: addi a6, a0, -2048
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1032; RV32I-FPELIM-NEXT: lui a0, %hi(va5_aligned_stack_callee)
1033; RV32I-FPELIM-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
1034; RV32I-FPELIM-NEXT: addi a0, zero, 1
1035; RV32I-FPELIM-NEXT: addi a1, zero, 11
1036; RV32I-FPELIM-NEXT: addi a2, sp, 32
1037; RV32I-FPELIM-NEXT: addi a3, zero, 12
1038; RV32I-FPELIM-NEXT: addi a4, zero, 13
1039; RV32I-FPELIM-NEXT: addi a7, zero, 4
1040; RV32I-FPELIM-NEXT: jalr a5
1041; RV32I-FPELIM-NEXT: lw ra, 60(sp)
1042; RV32I-FPELIM-NEXT: addi sp, sp, 64
1043; RV32I-FPELIM-NEXT: ret
1044;
1045; RV32I-WITHFP-LABEL: va5_aligned_stack_caller:
1046; RV32I-WITHFP: # %bb.0:
1047; RV32I-WITHFP-NEXT: addi sp, sp, -64
1048; RV32I-WITHFP-NEXT: sw ra, 60(sp)
1049; RV32I-WITHFP-NEXT: sw s0, 56(sp)
1050; RV32I-WITHFP-NEXT: addi s0, sp, 64
1051; RV32I-WITHFP-NEXT: addi a0, zero, 17
1052; RV32I-WITHFP-NEXT: sw a0, 24(sp)
1053; RV32I-WITHFP-NEXT: addi a0, zero, 16
1054; RV32I-WITHFP-NEXT: sw a0, 20(sp)
1055; RV32I-WITHFP-NEXT: addi a0, zero, 15
1056; RV32I-WITHFP-NEXT: sw a0, 16(sp)
1057; RV32I-WITHFP-NEXT: lui a0, 262236
1058; RV32I-WITHFP-NEXT: addi a0, a0, 655
1059; RV32I-WITHFP-NEXT: sw a0, 12(sp)
1060; RV32I-WITHFP-NEXT: lui a0, 377487
1061; RV32I-WITHFP-NEXT: addi a0, a0, 1475
1062; RV32I-WITHFP-NEXT: sw a0, 8(sp)
1063; RV32I-WITHFP-NEXT: addi a0, zero, 14
1064; RV32I-WITHFP-NEXT: sw a0, 0(sp)
1065; RV32I-WITHFP-NEXT: lui a0, 262153
1066; RV32I-WITHFP-NEXT: addi a0, a0, 491
1067; RV32I-WITHFP-NEXT: sw a0, -20(s0)
1068; RV32I-WITHFP-NEXT: lui a0, 545260
1069; RV32I-WITHFP-NEXT: addi a0, a0, -1967
1070; RV32I-WITHFP-NEXT: sw a0, -24(s0)
1071; RV32I-WITHFP-NEXT: lui a0, 964690
1072; RV32I-WITHFP-NEXT: addi a0, a0, -328
1073; RV32I-WITHFP-NEXT: sw a0, -28(s0)
1074; RV32I-WITHFP-NEXT: lui a0, 335544
1075; RV32I-WITHFP-NEXT: addi a0, a0, 1311
1076; RV32I-WITHFP-NEXT: sw a0, -32(s0)
Alex Bradbury099c7202018-04-18 19:02:31 +0000[diff] [blame]1077; RV32I-WITHFP-NEXT: lui a0, 688509
1078; RV32I-WITHFP-NEXT: addi a6, a0, -2048
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1079; RV32I-WITHFP-NEXT: lui a0, %hi(va5_aligned_stack_callee)
1080; RV32I-WITHFP-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
1081; RV32I-WITHFP-NEXT: addi a0, zero, 1
1082; RV32I-WITHFP-NEXT: addi a1, zero, 11
1083; RV32I-WITHFP-NEXT: addi a2, s0, -32
1084; RV32I-WITHFP-NEXT: addi a3, zero, 12
1085; RV32I-WITHFP-NEXT: addi a4, zero, 13
1086; RV32I-WITHFP-NEXT: addi a7, zero, 4
1087; RV32I-WITHFP-NEXT: jalr a5
1088; RV32I-WITHFP-NEXT: lw s0, 56(sp)
1089; RV32I-WITHFP-NEXT: lw ra, 60(sp)
1090; RV32I-WITHFP-NEXT: addi sp, sp, 64
1091; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1092 %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
1093 fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
1094 i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
1095 ret void
1096}
1097
1098; A function with no fixed arguments is not valid C, but can be
1099; specified in LLVM IR. We must ensure the vararg save area is
1100; still set up correctly.
1101
1102define i32 @va6_no_fixed_args(...) nounwind {
1103; RV32I-LABEL: va6_no_fixed_args:
1104; RV32I: # %bb.0:
1105; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1106; RV32I-NEXT: sw a0, 16(sp)
1107; RV32I-NEXT: sw a7, 44(sp)
1108; RV32I-NEXT: sw a6, 40(sp)
1109; RV32I-NEXT: sw a5, 36(sp)
1110; RV32I-NEXT: sw a4, 32(sp)
1111; RV32I-NEXT: sw a3, 28(sp)
1112; RV32I-NEXT: sw a2, 24(sp)
1113; RV32I-NEXT: sw a1, 20(sp)
1114; RV32I-NEXT: addi a0, sp, 20
1115; RV32I-NEXT: sw a0, 12(sp)
1116; RV32I-NEXT: lw a0, 16(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1117; RV32I-NEXT: addi sp, sp, 48
1118; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1119; RV32I-FPELIM-LABEL: va6_no_fixed_args:
1120; RV32I-FPELIM: # %bb.0:
1121; RV32I-FPELIM-NEXT: addi sp, sp, -48
1122; RV32I-FPELIM-NEXT: sw a0, 16(sp)
1123; RV32I-FPELIM-NEXT: sw a7, 44(sp)
1124; RV32I-FPELIM-NEXT: sw a6, 40(sp)
1125; RV32I-FPELIM-NEXT: sw a5, 36(sp)
1126; RV32I-FPELIM-NEXT: sw a4, 32(sp)
1127; RV32I-FPELIM-NEXT: sw a3, 28(sp)
1128; RV32I-FPELIM-NEXT: sw a2, 24(sp)
1129; RV32I-FPELIM-NEXT: sw a1, 20(sp)
1130; RV32I-FPELIM-NEXT: addi a0, sp, 20
1131; RV32I-FPELIM-NEXT: sw a0, 12(sp)
1132; RV32I-FPELIM-NEXT: lw a0, 16(sp)
1133; RV32I-FPELIM-NEXT: addi sp, sp, 48
1134; RV32I-FPELIM-NEXT: ret
1135;
1136; RV32I-WITHFP-LABEL: va6_no_fixed_args:
1137; RV32I-WITHFP: # %bb.0:
1138; RV32I-WITHFP-NEXT: addi sp, sp, -48
1139; RV32I-WITHFP-NEXT: sw ra, 12(sp)
1140; RV32I-WITHFP-NEXT: sw s0, 8(sp)
1141; RV32I-WITHFP-NEXT: addi s0, sp, 16
1142; RV32I-WITHFP-NEXT: sw a0, 0(s0)
1143; RV32I-WITHFP-NEXT: sw a7, 28(s0)
1144; RV32I-WITHFP-NEXT: sw a6, 24(s0)
1145; RV32I-WITHFP-NEXT: sw a5, 20(s0)
1146; RV32I-WITHFP-NEXT: sw a4, 16(s0)
1147; RV32I-WITHFP-NEXT: sw a3, 12(s0)
1148; RV32I-WITHFP-NEXT: sw a2, 8(s0)
1149; RV32I-WITHFP-NEXT: sw a1, 4(s0)
1150; RV32I-WITHFP-NEXT: addi a0, s0, 4
1151; RV32I-WITHFP-NEXT: sw a0, -12(s0)
1152; RV32I-WITHFP-NEXT: lw a0, 0(s0)
1153; RV32I-WITHFP-NEXT: lw s0, 8(sp)
1154; RV32I-WITHFP-NEXT: lw ra, 12(sp)
1155; RV32I-WITHFP-NEXT: addi sp, sp, 48
1156; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1157 %va = alloca i8*, align 4
1158 %1 = bitcast i8** %va to i8*
1159 call void @llvm.va_start(i8* %1)
1160 %2 = va_arg i8** %va, i32
1161 call void @llvm.va_end(i8* %1)
1162 ret i32 %2
1163}