Tom Stellard | 919bb6b | 2014-04-29 23:12:53 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 2 | |
| 3 | |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 4 | declare i32 @llvm.r600.read.tidig.x() readnone |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 5 | |
| 6 | ; SI-LABEL: @test_i64_vreg: |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 7 | ; SI: V_ADD_I32 |
| 8 | ; SI: V_ADDC_U32 |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 9 | define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) { |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 10 | %tid = call i32 @llvm.r600.read.tidig.x() readnone |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 11 | %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid |
| 12 | %b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid |
| 13 | %a = load i64 addrspace(1)* %a_ptr |
| 14 | %b = load i64 addrspace(1)* %b_ptr |
| 15 | %result = add i64 %a, %b |
| 16 | store i64 %result, i64 addrspace(1)* %out |
| 17 | ret void |
| 18 | } |
| 19 | |
Matt Arsenault | 3a4d86a | 2013-11-18 20:09:55 +0000 | [diff] [blame] | 20 | ; Check that the SGPR add operand is correctly moved to a VGPR. |
| 21 | ; SI-LABEL: @sgpr_operand: |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 22 | ; SI: V_ADD_I32 |
| 23 | ; SI: V_ADDC_U32 |
Matt Arsenault | 3a4d86a | 2013-11-18 20:09:55 +0000 | [diff] [blame] | 24 | define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) { |
Matt Arsenault | 08f7e37 | 2013-11-18 20:09:50 +0000 | [diff] [blame] | 25 | %foo = load i64 addrspace(1)* %in, align 8 |
| 26 | %result = add i64 %foo, %a |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 27 | store i64 %result, i64 addrspace(1)* %out |
| 28 | ret void |
| 29 | } |
| 30 | |
Matt Arsenault | 08f7e37 | 2013-11-18 20:09:50 +0000 | [diff] [blame] | 31 | ; Swap the arguments. Check that the SGPR -> VGPR copy works with the |
| 32 | ; SGPR as other operand. |
| 33 | ; |
Matt Arsenault | 3a4d86a | 2013-11-18 20:09:55 +0000 | [diff] [blame] | 34 | ; SI-LABEL: @sgpr_operand_reversed: |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 35 | ; SI: V_ADD_I32 |
| 36 | ; SI: V_ADDC_U32 |
Matt Arsenault | 3a4d86a | 2013-11-18 20:09:55 +0000 | [diff] [blame] | 37 | define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) { |
| 38 | %foo = load i64 addrspace(1)* %in, align 8 |
| 39 | %result = add i64 %a, %foo |
| 40 | store i64 %result, i64 addrspace(1)* %out |
| 41 | ret void |
| 42 | } |
Matt Arsenault | 08f7e37 | 2013-11-18 20:09:50 +0000 | [diff] [blame] | 43 | |
| 44 | |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 45 | ; SI-LABEL: @test_v2i64_sreg: |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 46 | ; SI: S_ADD_I32 |
| 47 | ; SI: S_ADDC_U32 |
| 48 | ; SI: S_ADD_I32 |
| 49 | ; SI: S_ADDC_U32 |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 50 | define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) { |
| 51 | %result = add <2 x i64> %a, %b |
| 52 | store <2 x i64> %result, <2 x i64> addrspace(1)* %out |
| 53 | ret void |
| 54 | } |
| 55 | |
| 56 | ; SI-LABEL: @test_v2i64_vreg: |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 57 | ; SI: V_ADD_I32 |
| 58 | ; SI: V_ADDC_U32 |
| 59 | ; SI: V_ADD_I32 |
| 60 | ; SI: V_ADDC_U32 |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 61 | define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) { |
Tom Stellard | 1f15bff | 2014-02-25 21:36:18 +0000 | [diff] [blame] | 62 | %tid = call i32 @llvm.r600.read.tidig.x() readnone |
Matt Arsenault | fb826fa | 2013-11-18 20:09:47 +0000 | [diff] [blame] | 63 | %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid |
| 64 | %b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid |
| 65 | %a = load <2 x i64> addrspace(1)* %a_ptr |
| 66 | %b = load <2 x i64> addrspace(1)* %b_ptr |
| 67 | %result = add <2 x i64> %a, %b |
| 68 | store <2 x i64> %result, <2 x i64> addrspace(1)* %out |
| 69 | ret void |
| 70 | } |
Matt Arsenault | b517c81 | 2014-03-27 17:23:31 +0000 | [diff] [blame] | 71 | |
| 72 | ; SI-LABEL: @trunc_i64_add_to_i32 |
Chandler Carruth | 9f4530b | 2014-07-24 22:15:28 +0000 | [diff] [blame^] | 73 | ; SI: S_LOAD_DWORD s[[SREG0:[0-9]+]] |
| 74 | ; SI: S_LOAD_DWORD s[[SREG1:[0-9]+]] |
Tom Stellard | 10ae6a0 | 2014-07-02 20:53:54 +0000 | [diff] [blame] | 75 | ; SI: S_ADD_I32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]] |
Matt Arsenault | b517c81 | 2014-03-27 17:23:31 +0000 | [diff] [blame] | 76 | ; SI-NOT: ADDC |
| 77 | ; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]] |
| 78 | ; SI: BUFFER_STORE_DWORD [[VRESULT]], |
| 79 | define void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) { |
| 80 | %add = add i64 %b, %a |
| 81 | %trunc = trunc i64 %add to i32 |
| 82 | store i32 %trunc, i32 addrspace(1)* %out, align 8 |
| 83 | ret void |
| 84 | } |