Jim Grosbach | 2987c57 | 2012-07-09 18:34:21 +0000 | [diff] [blame] | 1 | // REQUIRES: mips-registered-target |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 2 | // RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s -o - \ |
| 3 | // RUN: | FileCheck %s |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 4 | |
| 5 | typedef int q31; |
| 6 | typedef int i32; |
| 7 | typedef unsigned int ui32; |
| 8 | typedef long long a64; |
| 9 | |
| 10 | typedef signed char v4i8 __attribute__ ((vector_size(4))); |
| 11 | typedef short v2q15 __attribute__ ((vector_size(4))); |
| 12 | |
| 13 | void foo() { |
| 14 | v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c; |
| 15 | v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; |
| 16 | q31 q31_r, q31_a, q31_b, q31_c; |
| 17 | i32 i32_r, i32_a, i32_b, i32_c; |
| 18 | ui32 ui32_r, ui32_a, ui32_b, ui32_c; |
| 19 | a64 a64_r, a64_a, a64_b; |
| 20 | |
| 21 | // MIPS DSP Rev 1 |
| 22 | |
| 23 | v4i8_a = (v4i8) {1, 2, 3, 0xFF}; |
| 24 | v4i8_b = (v4i8) {2, 4, 6, 8}; |
| 25 | v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 26 | // CHECK: call <4 x i8> @llvm.mips.addu.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 27 | v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 28 | // CHECK: call <4 x i8> @llvm.mips.addu.s.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 29 | v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 30 | // CHECK: call <4 x i8> @llvm.mips.subu.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 31 | v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 32 | // CHECK: call <4 x i8> @llvm.mips.subu.s.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 33 | |
| 34 | v2q15_a = (v2q15) {0x0000, 0x8000}; |
| 35 | v2q15_b = (v2q15) {0x8000, 0x8000}; |
| 36 | v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 37 | // CHECK: call <2 x i16> @llvm.mips.addq.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 38 | v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 39 | // CHECK: call <2 x i16> @llvm.mips.addq.s.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 40 | v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 41 | // CHECK: call <2 x i16> @llvm.mips.subq.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 42 | v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 43 | // CHECK: call <2 x i16> @llvm.mips.subq.s.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 44 | |
| 45 | a64_a = 0x12345678; |
| 46 | i32_b = 0x80000000; |
| 47 | i32_c = 0x11112222; |
| 48 | a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 49 | // CHECK: call i64 @llvm.mips.madd |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 50 | a64_a = 0x12345678; |
| 51 | ui32_b = 0x80000000; |
| 52 | ui32_c = 0x11112222; |
| 53 | a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 54 | // CHECK: call i64 @llvm.mips.maddu |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 55 | a64_a = 0x12345678; |
| 56 | i32_b = 0x80000000; |
| 57 | i32_c = 0x11112222; |
| 58 | a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 59 | // CHECK: call i64 @llvm.mips.msub |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 60 | a64_a = 0x12345678; |
| 61 | ui32_b = 0x80000000; |
| 62 | ui32_c = 0x11112222; |
| 63 | a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 64 | // CHECK: call i64 @llvm.mips.msubu |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 65 | |
| 66 | q31_a = 0x12345678; |
| 67 | q31_b = 0x7FFFFFFF; |
| 68 | q31_r = __builtin_mips_addq_s_w(q31_a, q31_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 69 | // CHECK: call i32 @llvm.mips.addq.s.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 70 | q31_r = __builtin_mips_subq_s_w(q31_a, q31_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 71 | // CHECK: call i32 @llvm.mips.subq.s.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 72 | |
| 73 | i32_a = 0xFFFFFFFF; |
| 74 | i32_b = 1; |
| 75 | i32_r = __builtin_mips_addsc(i32_a, i32_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 76 | // CHECK: call i32 @llvm.mips.addsc |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 77 | i32_a = 0; |
| 78 | i32_b = 1; |
| 79 | i32_r = __builtin_mips_addwc(i32_a, i32_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 80 | // CHECK: call i32 @llvm.mips.addwc |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 81 | |
| 82 | i32_a = 20; |
| 83 | i32_b = 0x1402; |
| 84 | i32_r = __builtin_mips_modsub(i32_a, i32_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 85 | // CHECK: call i32 @llvm.mips.modsub |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 86 | |
| 87 | v4i8_a = (v4i8) {1, 2, 3, 4}; |
| 88 | i32_r = __builtin_mips_raddu_w_qb(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 89 | // CHECK: call i32 @llvm.mips.raddu.w.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 90 | |
| 91 | v2q15_a = (v2q15) {0xFFFF, 0x8000}; |
| 92 | v2q15_r = __builtin_mips_absq_s_ph(v2q15_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 93 | // CHECK: call <2 x i16> @llvm.mips.absq.s.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 94 | q31_a = 0x80000000; |
| 95 | q31_r = __builtin_mips_absq_s_w(q31_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 96 | // CHECK: call i32 @llvm.mips.absq.s.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 97 | |
| 98 | v2q15_a = (v2q15) {0x1234, 0x5678}; |
| 99 | v2q15_b = (v2q15) {0x1111, 0x2222}; |
| 100 | v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 101 | // CHECK: call <4 x i8> @llvm.mips.precrq.qb.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 102 | |
| 103 | v2q15_a = (v2q15) {0x7F79, 0xFFFF}; |
| 104 | v2q15_b = (v2q15) {0x7F81, 0x2000}; |
| 105 | v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 106 | // CHECK: call <4 x i8> @llvm.mips.precrqu.s.qb.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 107 | q31_a = 0x12345678; |
| 108 | q31_b = 0x11112222; |
| 109 | v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 110 | // CHECK: call <2 x i16> @llvm.mips.precrq.ph.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 111 | q31_a = 0x7000FFFF; |
| 112 | q31_b = 0x80000000; |
| 113 | v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 114 | // CHECK: call <2 x i16> @llvm.mips.precrq.rs.ph.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 115 | v2q15_a = (v2q15) {0x1234, 0x5678}; |
| 116 | q31_r = __builtin_mips_preceq_w_phl(v2q15_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 117 | // CHECK: call i32 @llvm.mips.preceq.w.phl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 118 | q31_r = __builtin_mips_preceq_w_phr(v2q15_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 119 | // CHECK: call i32 @llvm.mips.preceq.w.phr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 120 | v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; |
| 121 | v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 122 | // CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 123 | v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 124 | // CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 125 | v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 126 | // CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbla |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 127 | v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 128 | // CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbra |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 129 | v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 130 | // CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 131 | v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 132 | // CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 133 | v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 134 | // CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbla |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 135 | v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 136 | // CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbra |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 137 | |
| 138 | v4i8_a = (v4i8) {1, 2, 3, 4}; |
| 139 | v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 140 | // CHECK: call <4 x i8> @llvm.mips.shll.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 141 | v4i8_a = (v4i8) {128, 64, 32, 16}; |
| 142 | v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 143 | // CHECK: call <4 x i8> @llvm.mips.shrl.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 144 | v2q15_a = (v2q15) {0x0001, 0x8000}; |
| 145 | v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 146 | // CHECK: call <2 x i16> @llvm.mips.shll.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 147 | v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 148 | // CHECK: call <2 x i16> @llvm.mips.shll.s.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 149 | v2q15_a = (v2q15) {0x7FFF, 0x8000}; |
| 150 | v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 151 | // CHECK: call <2 x i16> @llvm.mips.shra.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 152 | v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 153 | // CHECK: call <2 x i16> @llvm.mips.shra.r.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 154 | q31_a = 0x70000000; |
| 155 | q31_r = __builtin_mips_shll_s_w(q31_a, 2); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 156 | // CHECK: call i32 @llvm.mips.shll.s.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 157 | q31_a = 0x7FFFFFFF; |
| 158 | q31_r = __builtin_mips_shra_r_w(q31_a, 2); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 159 | // CHECK: call i32 @llvm.mips.shra.r.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 160 | a64_a = 0x1234567887654321LL; |
| 161 | a64_r = __builtin_mips_shilo(a64_a, -8); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 162 | // CHECK: call i64 @llvm.mips.shilo |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 163 | |
| 164 | v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; |
| 165 | v2q15_b = (v2q15) {0x1234, 0x5678}; |
| 166 | v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 167 | // CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 168 | v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 169 | // CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 170 | v2q15_a = (v2q15) {0x7FFF, 0x8000}; |
| 171 | v2q15_b = (v2q15) {0x7FFF, 0x8000}; |
| 172 | v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 173 | // CHECK: call <2 x i16> @llvm.mips.mulq.rs.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 174 | v2q15_a = (v2q15) {0x1234, 0x8000}; |
| 175 | v2q15_b = (v2q15) {0x5678, 0x8000}; |
| 176 | q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 177 | // CHECK: call i32 @llvm.mips.muleq.s.w.phl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 178 | q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 179 | // CHECK: call i32 @llvm.mips.muleq.s.w.phr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 180 | a64_a = 0; |
| 181 | v2q15_a = (v2q15) {0x0001, 0x8000}; |
| 182 | v2q15_b = (v2q15) {0x0002, 0x8000}; |
| 183 | a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 184 | // CHECK: call i64 @llvm.mips.mulsaq.s.w.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 185 | a64_a = 0; |
| 186 | v2q15_b = (v2q15) {0x0001, 0x8000}; |
| 187 | v2q15_c = (v2q15) {0x0002, 0x8000}; |
| 188 | a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 189 | // CHECK: call i64 @llvm.mips.maq.s.w.phl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 190 | a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 191 | // CHECK: call i64 @llvm.mips.maq.s.w.phr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 192 | a64_a = 0x7FFFFFF0; |
| 193 | a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 194 | // CHECK: call i64 @llvm.mips.maq.sa.w.phl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 195 | a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 196 | // CHECK: call i64 @llvm.mips.maq.sa.w.phr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 197 | i32_a = 0x80000000; |
| 198 | i32_b = 0x11112222; |
| 199 | a64_r = __builtin_mips_mult(i32_a, i32_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 200 | // CHECK: call i64 @llvm.mips.mult |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 201 | ui32_a = 0x80000000; |
| 202 | ui32_b = 0x11112222; |
| 203 | a64_r = __builtin_mips_multu(ui32_a, ui32_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 204 | // CHECK: call i64 @llvm.mips.multu |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 205 | |
| 206 | a64_a = 0; |
| 207 | v4i8_b = (v4i8) {1, 2, 3, 4}; |
| 208 | v4i8_c = (v4i8) {4, 5, 6, 7}; |
| 209 | a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 210 | // CHECK: call i64 @llvm.mips.dpau.h.qbl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 211 | a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 212 | // CHECK: call i64 @llvm.mips.dpau.h.qbr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 213 | a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 214 | // CHECK: call i64 @llvm.mips.dpsu.h.qbl |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 215 | a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 216 | // CHECK: call i64 @llvm.mips.dpsu.h.qbr |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 217 | a64_a = 0; |
| 218 | v2q15_b = (v2q15) {0x0001, 0x8000}; |
| 219 | v2q15_c = (v2q15) {0x0002, 0x8000}; |
| 220 | a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 221 | // CHECK: call i64 @llvm.mips.dpaq.s.w.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 222 | a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 223 | // CHECK: call i64 @llvm.mips.dpsq.s.w.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 224 | a64_a = 0; |
| 225 | q31_b = 0x80000000; |
| 226 | q31_c = 0x80000000; |
| 227 | a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 228 | // CHECK: call i64 @llvm.mips.dpaq.sa.l.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 229 | a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 230 | // CHECK: call i64 @llvm.mips.dpsq.sa.l.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 231 | |
| 232 | v4i8_a = (v4i8) {1, 4, 10, 8}; |
| 233 | v4i8_b = (v4i8) {1, 2, 100, 8}; |
| 234 | __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 235 | // CHECK: call void @llvm.mips.cmpu.eq.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 236 | __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 237 | // CHECK: call void @llvm.mips.cmpu.lt.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 238 | __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 239 | // CHECK: call void @llvm.mips.cmpu.le.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 240 | i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 241 | // CHECK: call i32 @llvm.mips.cmpgu.eq.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 242 | i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 243 | // CHECK: call i32 @llvm.mips.cmpgu.lt.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 244 | i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 245 | // CHECK: call i32 @llvm.mips.cmpgu.le.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 246 | v2q15_a = (v2q15) {0x1111, 0x1234}; |
| 247 | v2q15_b = (v2q15) {0x4444, 0x1234}; |
| 248 | __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 249 | // CHECK: call void @llvm.mips.cmp.eq.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 250 | __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 251 | // CHECK: call void @llvm.mips.cmp.lt.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 252 | __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 253 | // CHECK: call void @llvm.mips.cmp.le.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 254 | |
| 255 | a64_a = 0xFFFFF81230000000LL; |
| 256 | i32_r = __builtin_mips_extr_s_h(a64_a, 4); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 257 | // CHECK: call i32 @llvm.mips.extr.s.h |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 258 | a64_a = 0x8123456712345678LL; |
| 259 | i32_r = __builtin_mips_extr_w(a64_a, 31); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 260 | // CHECK: call i32 @llvm.mips.extr.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 261 | i32_r = __builtin_mips_extr_rs_w(a64_a, 31); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 262 | // CHECK: call i32 @llvm.mips.extr.rs.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 263 | i32_r = __builtin_mips_extr_r_w(a64_a, 31); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 264 | // CHECK: call i32 @llvm.mips.extr.r.w |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 265 | a64_a = 0x1234567887654321LL; |
| 266 | i32_r = __builtin_mips_extp(a64_a, 3); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 267 | // CHECK: call i32 @llvm.mips.extp |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 268 | a64_a = 0x123456789ABCDEF0LL; |
| 269 | i32_r = __builtin_mips_extpdp(a64_a, 7); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 270 | // CHECK: call i32 @llvm.mips.extpdp |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 271 | |
| 272 | __builtin_mips_wrdsp(2052, 3); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 273 | // CHECK: call void @llvm.mips.wrdsp |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 274 | i32_r = __builtin_mips_rddsp(3); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 275 | // CHECK: call i32 @llvm.mips.rddsp |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 276 | i32_a = 0xFFFFFFFF; |
| 277 | i32_b = 0x12345678; |
| 278 | __builtin_mips_wrdsp((16<<7) + 4, 3); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 279 | // CHECK: call void @llvm.mips.wrdsp |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 280 | i32_r = __builtin_mips_insv(i32_a, i32_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 281 | // CHECK: call i32 @llvm.mips.insv |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 282 | i32_a = 0x1234; |
| 283 | i32_r = __builtin_mips_bitrev(i32_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 284 | // CHECK: call i32 @llvm.mips.bitrev |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 285 | v2q15_a = (v2q15) {0x1111, 0x2222}; |
| 286 | v2q15_b = (v2q15) {0x3333, 0x4444}; |
| 287 | v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 288 | // CHECK: call <2 x i16> @llvm.mips.packrl.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 289 | i32_a = 100; |
| 290 | v4i8_r = __builtin_mips_repl_qb(i32_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 291 | // CHECK: call <4 x i8> @llvm.mips.repl.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 292 | i32_a = 0x1234; |
| 293 | v2q15_r = __builtin_mips_repl_ph(i32_a); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 294 | // CHECK: call <2 x i16> @llvm.mips.repl.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 295 | v4i8_a = (v4i8) {1, 4, 10, 8}; |
| 296 | v4i8_b = (v4i8) {1, 2, 100, 8}; |
| 297 | __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 298 | // CHECK: call void @llvm.mips.cmpu.eq.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 299 | v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 300 | // CHECK: call <4 x i8> @llvm.mips.pick.qb |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 301 | v2q15_a = (v2q15) {0x1111, 0x1234}; |
| 302 | v2q15_b = (v2q15) {0x4444, 0x1234}; |
| 303 | __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 304 | // CHECK: call void @llvm.mips.cmp.eq.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 305 | v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 306 | // CHECK: call <2 x i16> @llvm.mips.pick.ph |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 307 | a64_a = 0x1234567887654321LL; |
| 308 | i32_b = 0x11112222; |
| 309 | __builtin_mips_wrdsp(0, 1); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 310 | // CHECK: call void @llvm.mips.wrdsp |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 311 | a64_r = __builtin_mips_mthlip(a64_a, i32_b); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 312 | // CHECK: call i64 @llvm.mips.mthlip |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 313 | i32_r = __builtin_mips_bposge32(); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 314 | // CHECK: call i32 @llvm.mips.bposge32 |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 315 | char array_a[100]; |
| 316 | i32_r = __builtin_mips_lbux(array_a, 20); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 317 | // CHECK: call i32 @llvm.mips.lbux |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 318 | short array_b[100]; |
| 319 | i32_r = __builtin_mips_lhx(array_b, 20); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 320 | // CHECK: call i32 @llvm.mips.lhx |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 321 | int array_c[100]; |
| 322 | i32_r = __builtin_mips_lwx(array_c, 20); |
Simon Atanasyan | a1f8c0a | 2012-08-06 19:48:16 +0000 | [diff] [blame^] | 323 | // CHECK: call i32 @llvm.mips.lwx |
Simon Atanasyan | 07ce7d8f | 2012-06-28 18:23:16 +0000 | [diff] [blame] | 324 | } |