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Jim Grosbach2987c572012-07-09 18:34:21 +00001// REQUIRES: mips-registered-target
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +00002// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s -o - \
3// RUN: | FileCheck %s
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +00004
5typedef int q31;
6typedef int i32;
7typedef unsigned int ui32;
8typedef long long a64;
9
10typedef signed char v4i8 __attribute__ ((vector_size(4)));
11typedef short v2q15 __attribute__ ((vector_size(4)));
12
13void foo() {
14 v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c;
15 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c;
16 q31 q31_r, q31_a, q31_b, q31_c;
17 i32 i32_r, i32_a, i32_b, i32_c;
18 ui32 ui32_r, ui32_a, ui32_b, ui32_c;
19 a64 a64_r, a64_a, a64_b;
20
21 // MIPS DSP Rev 1
22
23 v4i8_a = (v4i8) {1, 2, 3, 0xFF};
24 v4i8_b = (v4i8) {2, 4, 6, 8};
25 v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000026// CHECK: call <4 x i8> @llvm.mips.addu.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000027 v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000028// CHECK: call <4 x i8> @llvm.mips.addu.s.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000029 v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000030// CHECK: call <4 x i8> @llvm.mips.subu.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000031 v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000032// CHECK: call <4 x i8> @llvm.mips.subu.s.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000033
34 v2q15_a = (v2q15) {0x0000, 0x8000};
35 v2q15_b = (v2q15) {0x8000, 0x8000};
36 v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000037// CHECK: call <2 x i16> @llvm.mips.addq.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000038 v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000039// CHECK: call <2 x i16> @llvm.mips.addq.s.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000040 v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000041// CHECK: call <2 x i16> @llvm.mips.subq.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000042 v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000043// CHECK: call <2 x i16> @llvm.mips.subq.s.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000044
45 a64_a = 0x12345678;
46 i32_b = 0x80000000;
47 i32_c = 0x11112222;
48 a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000049// CHECK: call i64 @llvm.mips.madd
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000050 a64_a = 0x12345678;
51 ui32_b = 0x80000000;
52 ui32_c = 0x11112222;
53 a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000054// CHECK: call i64 @llvm.mips.maddu
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000055 a64_a = 0x12345678;
56 i32_b = 0x80000000;
57 i32_c = 0x11112222;
58 a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000059// CHECK: call i64 @llvm.mips.msub
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000060 a64_a = 0x12345678;
61 ui32_b = 0x80000000;
62 ui32_c = 0x11112222;
63 a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000064// CHECK: call i64 @llvm.mips.msubu
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000065
66 q31_a = 0x12345678;
67 q31_b = 0x7FFFFFFF;
68 q31_r = __builtin_mips_addq_s_w(q31_a, q31_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000069// CHECK: call i32 @llvm.mips.addq.s.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000070 q31_r = __builtin_mips_subq_s_w(q31_a, q31_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000071// CHECK: call i32 @llvm.mips.subq.s.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000072
73 i32_a = 0xFFFFFFFF;
74 i32_b = 1;
75 i32_r = __builtin_mips_addsc(i32_a, i32_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000076// CHECK: call i32 @llvm.mips.addsc
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000077 i32_a = 0;
78 i32_b = 1;
79 i32_r = __builtin_mips_addwc(i32_a, i32_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000080// CHECK: call i32 @llvm.mips.addwc
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000081
82 i32_a = 20;
83 i32_b = 0x1402;
84 i32_r = __builtin_mips_modsub(i32_a, i32_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000085// CHECK: call i32 @llvm.mips.modsub
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000086
87 v4i8_a = (v4i8) {1, 2, 3, 4};
88 i32_r = __builtin_mips_raddu_w_qb(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000089// CHECK: call i32 @llvm.mips.raddu.w.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000090
91 v2q15_a = (v2q15) {0xFFFF, 0x8000};
92 v2q15_r = __builtin_mips_absq_s_ph(v2q15_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000093// CHECK: call <2 x i16> @llvm.mips.absq.s.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000094 q31_a = 0x80000000;
95 q31_r = __builtin_mips_absq_s_w(q31_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +000096// CHECK: call i32 @llvm.mips.absq.s.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +000097
98 v2q15_a = (v2q15) {0x1234, 0x5678};
99 v2q15_b = (v2q15) {0x1111, 0x2222};
100 v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000101// CHECK: call <4 x i8> @llvm.mips.precrq.qb.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000102
103 v2q15_a = (v2q15) {0x7F79, 0xFFFF};
104 v2q15_b = (v2q15) {0x7F81, 0x2000};
105 v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000106// CHECK: call <4 x i8> @llvm.mips.precrqu.s.qb.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000107 q31_a = 0x12345678;
108 q31_b = 0x11112222;
109 v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000110// CHECK: call <2 x i16> @llvm.mips.precrq.ph.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000111 q31_a = 0x7000FFFF;
112 q31_b = 0x80000000;
113 v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000114// CHECK: call <2 x i16> @llvm.mips.precrq.rs.ph.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000115 v2q15_a = (v2q15) {0x1234, 0x5678};
116 q31_r = __builtin_mips_preceq_w_phl(v2q15_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000117// CHECK: call i32 @llvm.mips.preceq.w.phl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000118 q31_r = __builtin_mips_preceq_w_phr(v2q15_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000119// CHECK: call i32 @llvm.mips.preceq.w.phr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000120 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
121 v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000122// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000123 v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000124// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000125 v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000126// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbla
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000127 v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000128// CHECK: call <2 x i16> @llvm.mips.precequ.ph.qbra
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000129 v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000130// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000131 v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000132// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000133 v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000134// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbla
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000135 v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000136// CHECK: call <2 x i16> @llvm.mips.preceu.ph.qbra
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000137
138 v4i8_a = (v4i8) {1, 2, 3, 4};
139 v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000140// CHECK: call <4 x i8> @llvm.mips.shll.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000141 v4i8_a = (v4i8) {128, 64, 32, 16};
142 v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000143// CHECK: call <4 x i8> @llvm.mips.shrl.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000144 v2q15_a = (v2q15) {0x0001, 0x8000};
145 v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000146// CHECK: call <2 x i16> @llvm.mips.shll.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000147 v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000148// CHECK: call <2 x i16> @llvm.mips.shll.s.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000149 v2q15_a = (v2q15) {0x7FFF, 0x8000};
150 v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000151// CHECK: call <2 x i16> @llvm.mips.shra.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000152 v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000153// CHECK: call <2 x i16> @llvm.mips.shra.r.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000154 q31_a = 0x70000000;
155 q31_r = __builtin_mips_shll_s_w(q31_a, 2);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000156// CHECK: call i32 @llvm.mips.shll.s.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000157 q31_a = 0x7FFFFFFF;
158 q31_r = __builtin_mips_shra_r_w(q31_a, 2);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000159// CHECK: call i32 @llvm.mips.shra.r.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000160 a64_a = 0x1234567887654321LL;
161 a64_r = __builtin_mips_shilo(a64_a, -8);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000162// CHECK: call i64 @llvm.mips.shilo
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000163
164 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7};
165 v2q15_b = (v2q15) {0x1234, 0x5678};
166 v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000167// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000168 v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000169// CHECK: call <2 x i16> @llvm.mips.muleu.s.ph.qbr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000170 v2q15_a = (v2q15) {0x7FFF, 0x8000};
171 v2q15_b = (v2q15) {0x7FFF, 0x8000};
172 v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000173// CHECK: call <2 x i16> @llvm.mips.mulq.rs.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000174 v2q15_a = (v2q15) {0x1234, 0x8000};
175 v2q15_b = (v2q15) {0x5678, 0x8000};
176 q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000177// CHECK: call i32 @llvm.mips.muleq.s.w.phl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000178 q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000179// CHECK: call i32 @llvm.mips.muleq.s.w.phr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000180 a64_a = 0;
181 v2q15_a = (v2q15) {0x0001, 0x8000};
182 v2q15_b = (v2q15) {0x0002, 0x8000};
183 a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000184// CHECK: call i64 @llvm.mips.mulsaq.s.w.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000185 a64_a = 0;
186 v2q15_b = (v2q15) {0x0001, 0x8000};
187 v2q15_c = (v2q15) {0x0002, 0x8000};
188 a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000189// CHECK: call i64 @llvm.mips.maq.s.w.phl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000190 a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000191// CHECK: call i64 @llvm.mips.maq.s.w.phr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000192 a64_a = 0x7FFFFFF0;
193 a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000194// CHECK: call i64 @llvm.mips.maq.sa.w.phl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000195 a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000196// CHECK: call i64 @llvm.mips.maq.sa.w.phr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000197 i32_a = 0x80000000;
198 i32_b = 0x11112222;
199 a64_r = __builtin_mips_mult(i32_a, i32_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000200// CHECK: call i64 @llvm.mips.mult
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000201 ui32_a = 0x80000000;
202 ui32_b = 0x11112222;
203 a64_r = __builtin_mips_multu(ui32_a, ui32_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000204// CHECK: call i64 @llvm.mips.multu
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000205
206 a64_a = 0;
207 v4i8_b = (v4i8) {1, 2, 3, 4};
208 v4i8_c = (v4i8) {4, 5, 6, 7};
209 a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000210// CHECK: call i64 @llvm.mips.dpau.h.qbl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000211 a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000212// CHECK: call i64 @llvm.mips.dpau.h.qbr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000213 a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000214// CHECK: call i64 @llvm.mips.dpsu.h.qbl
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000215 a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000216// CHECK: call i64 @llvm.mips.dpsu.h.qbr
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000217 a64_a = 0;
218 v2q15_b = (v2q15) {0x0001, 0x8000};
219 v2q15_c = (v2q15) {0x0002, 0x8000};
220 a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000221// CHECK: call i64 @llvm.mips.dpaq.s.w.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000222 a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000223// CHECK: call i64 @llvm.mips.dpsq.s.w.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000224 a64_a = 0;
225 q31_b = 0x80000000;
226 q31_c = 0x80000000;
227 a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000228// CHECK: call i64 @llvm.mips.dpaq.sa.l.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000229 a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000230// CHECK: call i64 @llvm.mips.dpsq.sa.l.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000231
232 v4i8_a = (v4i8) {1, 4, 10, 8};
233 v4i8_b = (v4i8) {1, 2, 100, 8};
234 __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000235// CHECK: call void @llvm.mips.cmpu.eq.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000236 __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000237// CHECK: call void @llvm.mips.cmpu.lt.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000238 __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000239// CHECK: call void @llvm.mips.cmpu.le.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000240 i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000241// CHECK: call i32 @llvm.mips.cmpgu.eq.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000242 i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000243// CHECK: call i32 @llvm.mips.cmpgu.lt.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000244 i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000245// CHECK: call i32 @llvm.mips.cmpgu.le.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000246 v2q15_a = (v2q15) {0x1111, 0x1234};
247 v2q15_b = (v2q15) {0x4444, 0x1234};
248 __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000249// CHECK: call void @llvm.mips.cmp.eq.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000250 __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000251// CHECK: call void @llvm.mips.cmp.lt.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000252 __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000253// CHECK: call void @llvm.mips.cmp.le.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000254
255 a64_a = 0xFFFFF81230000000LL;
256 i32_r = __builtin_mips_extr_s_h(a64_a, 4);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000257// CHECK: call i32 @llvm.mips.extr.s.h
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000258 a64_a = 0x8123456712345678LL;
259 i32_r = __builtin_mips_extr_w(a64_a, 31);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000260// CHECK: call i32 @llvm.mips.extr.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000261 i32_r = __builtin_mips_extr_rs_w(a64_a, 31);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000262// CHECK: call i32 @llvm.mips.extr.rs.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000263 i32_r = __builtin_mips_extr_r_w(a64_a, 31);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000264// CHECK: call i32 @llvm.mips.extr.r.w
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000265 a64_a = 0x1234567887654321LL;
266 i32_r = __builtin_mips_extp(a64_a, 3);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000267// CHECK: call i32 @llvm.mips.extp
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000268 a64_a = 0x123456789ABCDEF0LL;
269 i32_r = __builtin_mips_extpdp(a64_a, 7);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000270// CHECK: call i32 @llvm.mips.extpdp
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000271
272 __builtin_mips_wrdsp(2052, 3);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000273// CHECK: call void @llvm.mips.wrdsp
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000274 i32_r = __builtin_mips_rddsp(3);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000275// CHECK: call i32 @llvm.mips.rddsp
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000276 i32_a = 0xFFFFFFFF;
277 i32_b = 0x12345678;
278 __builtin_mips_wrdsp((16<<7) + 4, 3);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000279// CHECK: call void @llvm.mips.wrdsp
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000280 i32_r = __builtin_mips_insv(i32_a, i32_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000281// CHECK: call i32 @llvm.mips.insv
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000282 i32_a = 0x1234;
283 i32_r = __builtin_mips_bitrev(i32_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000284// CHECK: call i32 @llvm.mips.bitrev
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000285 v2q15_a = (v2q15) {0x1111, 0x2222};
286 v2q15_b = (v2q15) {0x3333, 0x4444};
287 v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000288// CHECK: call <2 x i16> @llvm.mips.packrl.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000289 i32_a = 100;
290 v4i8_r = __builtin_mips_repl_qb(i32_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000291// CHECK: call <4 x i8> @llvm.mips.repl.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000292 i32_a = 0x1234;
293 v2q15_r = __builtin_mips_repl_ph(i32_a);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000294// CHECK: call <2 x i16> @llvm.mips.repl.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000295 v4i8_a = (v4i8) {1, 4, 10, 8};
296 v4i8_b = (v4i8) {1, 2, 100, 8};
297 __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000298// CHECK: call void @llvm.mips.cmpu.eq.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000299 v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000300// CHECK: call <4 x i8> @llvm.mips.pick.qb
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000301 v2q15_a = (v2q15) {0x1111, 0x1234};
302 v2q15_b = (v2q15) {0x4444, 0x1234};
303 __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000304// CHECK: call void @llvm.mips.cmp.eq.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000305 v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000306// CHECK: call <2 x i16> @llvm.mips.pick.ph
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000307 a64_a = 0x1234567887654321LL;
308 i32_b = 0x11112222;
309 __builtin_mips_wrdsp(0, 1);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000310// CHECK: call void @llvm.mips.wrdsp
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000311 a64_r = __builtin_mips_mthlip(a64_a, i32_b);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000312// CHECK: call i64 @llvm.mips.mthlip
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000313 i32_r = __builtin_mips_bposge32();
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000314// CHECK: call i32 @llvm.mips.bposge32
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000315 char array_a[100];
316 i32_r = __builtin_mips_lbux(array_a, 20);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000317// CHECK: call i32 @llvm.mips.lbux
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000318 short array_b[100];
319 i32_r = __builtin_mips_lhx(array_b, 20);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000320// CHECK: call i32 @llvm.mips.lhx
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000321 int array_c[100];
322 i32_r = __builtin_mips_lwx(array_c, 20);
Simon Atanasyana1f8c0a2012-08-06 19:48:16 +0000323// CHECK: call i32 @llvm.mips.lwx
Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +0000324}