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gerrit-public.fairphone.software / toolchain / llvm-project / d9ecf1ae7cfde3cd18cdedc4b95b8921a5f81378 / . / llvm / lib / Target / Hexagon / HexagonIntrinsicsV4.td
blob: ae2d463fa68a693fced7c112ff68f2849c3ebb06 [file] [log] [blame]
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]1//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is populated based on the following specs:
10// Hexagon V4 Architecture Extensions
11// Application-Level Specification
12// 80-V9418-12 Rev. A
13// June 15, 2010
14
Colin LeMahieu94c33212015-01-28 19:16:17 +0000[diff] [blame]15// Polynomial multiply words
16// Rdd=pmpyw(Rs,Rt)
17def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
18// Rxx^=pmpyw(Rs,Rt)
19def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
20
21//Rxx^=asr(Rss,Rt)
22def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
23//Rxx^=asl(Rss,Rt)
24def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
25//Rxx^=lsr(Rss,Rt)
26def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
27//Rxx^=lsl(Rss,Rt)
28def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
29
30// Multiply and use upper result
31def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
32def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
33def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
34def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
35def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
36
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]37// Vector reduce add unsigned halfwords
38def : Pat <(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2),
39 (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>;
40
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]41def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
42
43def: T_P_pat <S2_ct0p, int_hexagon_S2_ct0p>;
44def: T_P_pat <S2_ct1p, int_hexagon_S2_ct1p>;
45def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
46def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
47def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
48
Colin LeMahieua749b3e2015-01-29 16:08:43 +0000[diff] [blame]49def : T_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>;
50def : T_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>;
51def : T_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>;
52def : T_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>;
53def : T_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>;
54def : T_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>;
55
56def : T_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>;
57def : T_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>;
58def : T_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>;
59
60def : T_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>;
61def : T_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>;
62def : T_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>;
63
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]64def : T_RP_pat <A4_boundscheck, int_hexagon_A4_boundscheck>;
65
66def : T_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>;
67
Colin LeMahieu94c33212015-01-28 19:16:17 +0000[diff] [blame]68def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
69 IntRegs:$src3),
70 (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
71
72def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
73def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
74def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
75def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
76// Multiply 32x32 and use upper result
77def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
78def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
79
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]80def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
81def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>;
82
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]83// Extract bitfield
84def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
85def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
86def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
87def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
88
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]89// Vector conditional negate
90// Rdd=vcnegh(Rss,Rt)
91def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>;
92
Colin LeMahieufe03c9a2015-01-28 17:37:59 +0000[diff] [blame]93// Shift an immediate left by register amount
94def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
95
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]96// Vector reduce maximum halfwords
97def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>;
98def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>;
99
100// Vector reduce maximum words
101def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>;
102def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>;
103
104// Vector reduce minimum halfwords
105def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>;
106def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>;
107
108// Vector reduce minimum words
109def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>;
110def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>;
111
112// Vector conditional negate
113def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>;
114
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]115// Logical xor with xor accumulation
116def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
117
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]118// ALU64 - Vector min/max byte
119def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>;
120def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>;
121
Colin LeMahieufe03c9a2015-01-28 17:37:59 +0000[diff] [blame]122// Shift and add/sub/and/or
123def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
124def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
125def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
126def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
127def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
128def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>;
129def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
130def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]131
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]132// Split bitfield
133def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
134def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
135
136def: T_RR_pat<S4_parity, int_hexagon_S4_parity>;
137
138def: T_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
139def: T_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
140
141def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>;
142def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
143def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
144
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]145/********************************************************************
146* ALU32/ALU *
147*********************************************************************/
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]148
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]149// ALU32 / ALU / Logical Operations.
150def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
151def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]152
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]153/********************************************************************
154* ALU32/PERM *
155*********************************************************************/
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]156
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]157// Combine Words Into Doublewords.
158def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s8ExtPred>;
159def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
160
161/********************************************************************
162* ALU32/PRED *
163*********************************************************************/
164
Colin LeMahieu860210b2015-01-29 16:55:37 +0000[diff] [blame]165// Compare
166def : T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s10ExtPred>;
167def : T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s10ExtPred>;
168def : T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u9ExtPred>;
169
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]170def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>;
171def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
172
173def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>;
174def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
175
176/********************************************************************
Colin LeMahieu860210b2015-01-29 16:55:37 +0000[diff] [blame]177* CR *
178*********************************************************************/
179
180// CR / Logical Operations On Predicates.
181
182class qi_CRInst_qiqiqi_pat<Intrinsic IntID, InstHexagon Inst> :
183 Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt, IntRegs:$Ru)),
184 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs),
185 (C2_tfrrp IntRegs:$Rt),
186 (C2_tfrrp IntRegs:$Ru))))>;
187
188def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_and, C4_and_and>;
189def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_andn, C4_and_andn>;
190def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_or, C4_and_or>;
191def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_orn, C4_and_orn>;
192def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_and, C4_or_and>;
193def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_andn, C4_or_andn>;
194def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_or, C4_or_or>;
195def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_orn, C4_or_orn>;
196
197/********************************************************************
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]198* XTYPE/ALU *
199*********************************************************************/
200
201// Add And Accumulate.
202
203def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
204def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
205
206
207// XTYPE / ALU / Logical-logical Words.
208def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>;
209def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>;
210def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>;
211def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>;
212def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>;
213def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>;
214def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>;
215def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>;
216def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>;
217def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
218def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
219
220def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
221def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>;
222def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
223
224// Modulo wrap.
225def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
226
227// Arithmetic/Convergent round
228// Rd=[cround|round](Rs,Rt)[:sat]
229// Rd=[cround|round](Rs,#u5)[:sat]
230def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
231def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
232
233def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
234def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
235
236def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
237def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
238
239def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;