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gerrit-public.fairphone.software / toolchain / llvm-project / 39b846ce0f72a9d460725385c8774dba4f707852 / . / llvm / lib / Target / Hexagon / HexagonIntrinsicsV4.td
blob: 894ead691e805f0d06a69cc5ed1e8f74073902f9 [file] [log] [blame]
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]1//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is populated based on the following specs:
10// Hexagon V4 Architecture Extensions
11// Application-Level Specification
12// 80-V9418-12 Rev. A
13// June 15, 2010
14
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame^]15def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
16
17def: T_P_pat <S2_ct0p, int_hexagon_S2_ct0p>;
18def: T_P_pat <S2_ct1p, int_hexagon_S2_ct1p>;
19def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
20def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
21def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
22
23// Extract bitfield
24def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
25def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
26def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
27def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
28
Colin LeMahieufe03c9a2015-01-28 17:37:59 +0000[diff] [blame]29// Shift an immediate left by register amount
30def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
31
32// Shift and add/sub/and/or
33def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
34def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
35def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
36def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
37def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
38def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>;
39def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
40def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]41
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame^]42// Split bitfield
43def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
44def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
45
46def: T_RR_pat<S4_parity, int_hexagon_S4_parity>;
47
48def: T_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
49def: T_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
50
51def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>;
52def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
53def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
54
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]55//
56// ALU 32 types.
57//
58
59class si_ALU32_sisi_not<string opc, Intrinsic IntID>
60 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
61 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
62 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
63
64class di_ALU32_s8si<string opc, Intrinsic IntID>
65 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
66 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
67 [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
68
69class di_ALU32_sis8<string opc, Intrinsic IntID>
70 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
71 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
72 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
73
74class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
75 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
76 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
77 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
78
79class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
80 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
81 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
82 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
83
84class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
85 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
86 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
87 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
88
89class si_neg_ALU32_sisi<string opc, Intrinsic IntID>
90 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
91 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
92 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
93
94class si_neg_ALU32_sis8<string opc, Intrinsic IntID>
95 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
96 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
97 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
98
99class si_ALU32_sis8<string opc, Intrinsic IntID>
100 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
101 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
102 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
103
104
105//
106// SInst Classes.
107//
108class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
109 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
110 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
111 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
112
113class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
114 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
115 IntRegs:$src3),
116 !strconcat("$dst = ", !strconcat(opc ,
117 "($src1, and($src2, !$src3)")),
118 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
119 IntRegs:$src3))]>;
120
121class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
122 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
123 IntRegs:$src3),
124 !strconcat("$dst = ", !strconcat(opc ,
125 "($src1, and($src2, $src3)")),
126 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
127 IntRegs:$src3))]>;
128
129class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
130 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
131 IntRegs:$src3),
132 !strconcat("$dst = ", !strconcat(opc ,
133 "($src1, or($src2, !$src3)")),
134 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
135 IntRegs:$src3))]>;
136
137class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
138 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
139 IntRegs:$src3),
140 !strconcat("$dst = ", !strconcat(opc ,
141 "($src1, or($src2, $src3)")),
142 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
143 IntRegs:$src3))]>;
144
145class si_SInst_si_addsis6<string opc, Intrinsic IntID>
146 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
147 !strconcat("$dst = ", !strconcat(opc ,
148 "($src1, add($src2, #$src3)")),
149 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
150 imm:$src3))]>;
151
152class si_SInst_si_subs6si<string opc, Intrinsic IntID>
153 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
154 !strconcat("$dst = ", !strconcat(opc ,
155 "($src1, sub(#$src2, $src3)")),
156 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
157 IntRegs:$src3))]>;
158
159class di_ALU64_didi_neg<string opc, Intrinsic IntID>
160 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
161 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
162 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
163
164class di_MInst_dididi_xacc<string opc, Intrinsic IntID>
165 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
166 DoubleRegs:$src2),
167 !strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")),
168 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
169 DoubleRegs:$src2))],
170 "$dst2 = $dst">;
171
172class si_MInst_sisisi_and<string opc, Intrinsic IntID>
173 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
174 IntRegs:$src3),
175 !strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")),
176 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
177 IntRegs:$src3))]>;
178
179class si_MInst_sisisi_andn<string opc, Intrinsic IntID>
180 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
181 IntRegs:$src3),
182 !strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")),
183 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
184 IntRegs:$src3))]>;
185
186class si_SInst_sisis10_andi<string opc, Intrinsic IntID>
187 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3),
188 !strconcat("$dst = ", !strconcat(opc ,
189 "($src1, and($src2, #$src3))")),
190 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
191 imm:$src3))]>;
192
193class si_MInst_sisisi_xor<string opc, Intrinsic IntID>
194 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
195 IntRegs:$src3),
196 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
197 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
198 IntRegs:$src3))]>;
199
200class si_MInst_sisisi_xorn<string opc, Intrinsic IntID>
201 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
202 IntRegs:$src3),
203 !strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")),
204 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
205 IntRegs:$src3))]>;
206
207class si_SInst_sisis10_or<string opc, Intrinsic IntID>
208 : SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3),
209 !strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")),
210 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
211 imm:$src3))]>;
212
213class si_MInst_sisisi_or<string opc, Intrinsic IntID>
214 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
215 IntRegs:$src3),
216 !strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")),
217 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
218 IntRegs:$src3))]>;
219
220class si_MInst_sisisi_orn<string opc, Intrinsic IntID>
221 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
222 IntRegs:$src3),
223 !strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")),
224 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
225 IntRegs:$src3))]>;
226
227class si_SInst_siu5_sat<string opc, Intrinsic IntID>
228 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
229 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")),
230 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
231
232
233/********************************************************************
234* ALU32/ALU *
235*********************************************************************/
236
237// ALU32 / ALU / Logical Operations.
238def Hexagon_A4_orn : si_ALU32_sisi_not <"or", int_hexagon_A4_orn>;
239def Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>;
240
241
242/********************************************************************
243* ALU32/PERM *
244*********************************************************************/
245
246// ALU32 / PERM / Combine Words Into Doublewords.
247def Hexagon_A4_combineir : di_ALU32_s8si <"combine", int_hexagon_A4_combineir>;
248def Hexagon_A4_combineri : di_ALU32_sis8 <"combine", int_hexagon_A4_combineri>;
249
250
251/********************************************************************
252* ALU32/PRED *
253*********************************************************************/
254
255// ALU32 / PRED / Conditional Shift Halfword.
256// ALU32 / PRED / Conditional Sign Extend.
257// ALU32 / PRED / Conditional Zero Extend.
258// ALU32 / PRED / Compare.
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]259def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
Sid Manning31f71252014-09-25 13:09:54 +0000[diff] [blame]260def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]261def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>;
Sid Manning31f71252014-09-25 13:09:54 +0000[diff] [blame]262
263def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
264def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
265def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]266
267// ALU32 / PRED / cmpare To General Register.
268def Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>;
269def Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>;
270def Hexagon_A4_rcmpeq : si_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpeq>;
271def Hexagon_A4_rcmpeqi : si_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpeqi>;
272
273
274/********************************************************************
275* CR *
276*********************************************************************/
277
278// CR / Corner Detection Acceleration.
279def Hexagon_C4_fastcorner9:
280 qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
281def Hexagon_C4_fastcorner9_not:
282 qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
283
284// CR / Logical Operations On Predicates.
285def Hexagon_C4_and_andn:
286 qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>;
287def Hexagon_C4_and_and:
288 qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>;
289def Hexagon_C4_and_orn:
290 qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>;
291def Hexagon_C4_and_or:
292 qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>;
293def Hexagon_C4_or_andn:
294 qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>;
295def Hexagon_C4_or_and:
296 qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>;
297def Hexagon_C4_or_orn:
298 qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
299def Hexagon_C4_or_or:
300 qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;
301
302
303/********************************************************************
304* XTYPE/ALU *
305*********************************************************************/
306
307// XTYPE / ALU / Add And Accumulate.
308def Hexagon_S4_addaddi:
309 si_SInst_si_addsis6 <"add", int_hexagon_S4_addaddi>;
310def Hexagon_S4_subaddi:
311 si_SInst_si_subs6si <"add", int_hexagon_S4_subaddi>;
312
313// XTYPE / ALU / Logical Doublewords.
314def Hexagon_S4_andnp:
315 di_ALU64_didi_neg <"and", int_hexagon_A4_andnp>;
316def Hexagon_S4_ornp:
317 di_ALU64_didi_neg <"or", int_hexagon_A4_ornp>;
318
319// XTYPE / ALU / Logical-logical Doublewords.
320def Hexagon_M4_xor_xacc:
321 di_MInst_dididi_xacc <"xor", int_hexagon_M4_xor_xacc>;
322
323// XTYPE / ALU / Logical-logical Words.
324def HEXAGON_M4_and_and:
325 si_MInst_sisisi_and <"and", int_hexagon_M4_and_and>;
326def HEXAGON_M4_and_or:
327 si_MInst_sisisi_and <"or", int_hexagon_M4_and_or>;
328def HEXAGON_M4_and_xor:
329 si_MInst_sisisi_and <"xor", int_hexagon_M4_and_xor>;
330def HEXAGON_M4_and_andn:
331 si_MInst_sisisi_andn <"and", int_hexagon_M4_and_andn>;
332def HEXAGON_M4_xor_and:
333 si_MInst_sisisi_xor <"and", int_hexagon_M4_xor_and>;
334def HEXAGON_M4_xor_or:
335 si_MInst_sisisi_xor <"or", int_hexagon_M4_xor_or>;
336def HEXAGON_M4_xor_andn:
337 si_MInst_sisisi_xorn <"and", int_hexagon_M4_xor_andn>;
338def HEXAGON_M4_or_and:
339 si_MInst_sisisi_or <"and", int_hexagon_M4_or_and>;
340def HEXAGON_M4_or_or:
341 si_MInst_sisisi_or <"or", int_hexagon_M4_or_or>;
342def HEXAGON_M4_or_xor:
343 si_MInst_sisisi_or <"xor", int_hexagon_M4_or_xor>;
344def HEXAGON_M4_or_andn:
345 si_MInst_sisisi_orn <"and", int_hexagon_M4_or_andn>;
346def HEXAGON_S4_or_andix:
347 si_SInst_sisis10_andi <"or", int_hexagon_S4_or_andix>;
348def HEXAGON_S4_or_andi:
349 si_SInst_sisis10_or <"and", int_hexagon_S4_or_andi>;
350def HEXAGON_S4_or_ori:
351 si_SInst_sisis10_or <"or", int_hexagon_S4_or_ori>;
352
353// XTYPE / ALU / Modulo wrap.
354def HEXAGON_A4_modwrapu:
355 si_ALU64_sisi <"modwrap", int_hexagon_A4_modwrapu>;
356
357// XTYPE / ALU / Round.
358def HEXAGON_A4_cround_ri:
359 si_SInst_siu5 <"cround", int_hexagon_A4_cround_ri>;
360def HEXAGON_A4_cround_rr:
361 si_SInst_sisi <"cround", int_hexagon_A4_cround_rr>;
362def HEXAGON_A4_round_ri:
363 si_SInst_siu5 <"round", int_hexagon_A4_round_ri>;
364def HEXAGON_A4_round_rr:
365 si_SInst_sisi <"round", int_hexagon_A4_round_rr>;
366def HEXAGON_A4_round_ri_sat:
367 si_SInst_siu5_sat <"round", int_hexagon_A4_round_ri_sat>;
368def HEXAGON_A4_round_rr_sat:
369 si_SInst_sisi_sat <"round", int_hexagon_A4_round_rr_sat>;
370
371// XTYPE / ALU / Vector reduce add unsigned halfwords.
372// XTYPE / ALU / Vector add bytes.
373// XTYPE / ALU / Vector conditional negate.
374// XTYPE / ALU / Vector maximum bytes.
375// XTYPE / ALU / Vector reduce maximum halfwords.
376// XTYPE / ALU / Vector reduce maximum words.
377// XTYPE / ALU / Vector minimum bytes.
378// XTYPE / ALU / Vector reduce minimum halfwords.
379// XTYPE / ALU / Vector reduce minimum words.
380// XTYPE / ALU / Vector subtract bytes.
381
382
383/********************************************************************
384* XTYPE/BIT *
385*********************************************************************/
386
387// XTYPE / BIT / Count leading.
388// XTYPE / BIT / Count trailing.
389// XTYPE / BIT / Extract bitfield.
390// XTYPE / BIT / Masked parity.
391// XTYPE / BIT / Bit reverse.
392// XTYPE / BIT / Split bitfield.
393
394
395/********************************************************************
396* XTYPE/COMPLEX *
397*********************************************************************/
398
399// XTYPE / COMPLEX / Complex add/sub halfwords.
400// XTYPE / COMPLEX / Complex add/sub words.
401// XTYPE / COMPLEX / Complex multiply 32x16.
402// XTYPE / COMPLEX / Vector reduce complex rotate.
403
404
405/********************************************************************
406* XTYPE/MPY *
407*********************************************************************/
408
409// XTYPE / COMPLEX / Complex add/sub halfwords.