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gerrit-public.fairphone.software / toolchain / llvm-project / 94c33218e3a998a6875255291532e1819a5e4768 / . / llvm / lib / Target / Hexagon / HexagonIntrinsicsV4.td
blob: 95bd397d989eace25ed4a1b9160da92c0265d412 [file] [log] [blame]
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]1//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is populated based on the following specs:
10// Hexagon V4 Architecture Extensions
11// Application-Level Specification
12// 80-V9418-12 Rev. A
13// June 15, 2010
14
Colin LeMahieu94c33212015-01-28 19:16:17 +0000[diff] [blame^]15// Polynomial multiply words
16// Rdd=pmpyw(Rs,Rt)
17def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
18// Rxx^=pmpyw(Rs,Rt)
19def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
20
21//Rxx^=asr(Rss,Rt)
22def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
23//Rxx^=asl(Rss,Rt)
24def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
25//Rxx^=lsr(Rss,Rt)
26def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
27//Rxx^=lsl(Rss,Rt)
28def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
29
30// Multiply and use upper result
31def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
32def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
33def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
34def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
35def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
36
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]37def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
38
39def: T_P_pat <S2_ct0p, int_hexagon_S2_ct0p>;
40def: T_P_pat <S2_ct1p, int_hexagon_S2_ct1p>;
41def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
42def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
43def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
44
Colin LeMahieu94c33212015-01-28 19:16:17 +0000[diff] [blame^]45def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
46 IntRegs:$src3),
47 (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
48
49def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
50def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
51def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
52def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
53// Multiply 32x32 and use upper result
54def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
55def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
56
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]57// Extract bitfield
58def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
59def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
60def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
61def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
62
Colin LeMahieufe03c9a2015-01-28 17:37:59 +0000[diff] [blame]63// Shift an immediate left by register amount
64def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
65
66// Shift and add/sub/and/or
67def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
68def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
69def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
70def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
71def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
72def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>;
73def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
74def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]75
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]76// Split bitfield
77def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
78def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
79
80def: T_RR_pat<S4_parity, int_hexagon_S4_parity>;
81
82def: T_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
83def: T_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
84
85def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>;
86def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
87def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
88
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]89//
90// ALU 32 types.
91//
92
93class si_ALU32_sisi_not<string opc, Intrinsic IntID>
94 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
95 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
96 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
97
98class di_ALU32_s8si<string opc, Intrinsic IntID>
99 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
100 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
101 [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
102
103class di_ALU32_sis8<string opc, Intrinsic IntID>
104 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
105 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
106 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
107
108class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
109 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
110 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
111 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
112
113class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
114 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
115 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
116 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
117
118class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
119 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
120 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
121 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
122
123class si_neg_ALU32_sisi<string opc, Intrinsic IntID>
124 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
125 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
126 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
127
128class si_neg_ALU32_sis8<string opc, Intrinsic IntID>
129 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
130 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
131 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
132
133class si_ALU32_sis8<string opc, Intrinsic IntID>
134 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
135 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
136 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
137
138
139//
140// SInst Classes.
141//
142class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
143 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
144 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
145 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
146
147class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
148 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
149 IntRegs:$src3),
150 !strconcat("$dst = ", !strconcat(opc ,
151 "($src1, and($src2, !$src3)")),
152 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
153 IntRegs:$src3))]>;
154
155class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
156 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
157 IntRegs:$src3),
158 !strconcat("$dst = ", !strconcat(opc ,
159 "($src1, and($src2, $src3)")),
160 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
161 IntRegs:$src3))]>;
162
163class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
164 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
165 IntRegs:$src3),
166 !strconcat("$dst = ", !strconcat(opc ,
167 "($src1, or($src2, !$src3)")),
168 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
169 IntRegs:$src3))]>;
170
171class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
172 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
173 IntRegs:$src3),
174 !strconcat("$dst = ", !strconcat(opc ,
175 "($src1, or($src2, $src3)")),
176 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
177 IntRegs:$src3))]>;
178
179class si_SInst_si_addsis6<string opc, Intrinsic IntID>
180 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
181 !strconcat("$dst = ", !strconcat(opc ,
182 "($src1, add($src2, #$src3)")),
183 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
184 imm:$src3))]>;
185
186class si_SInst_si_subs6si<string opc, Intrinsic IntID>
187 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
188 !strconcat("$dst = ", !strconcat(opc ,
189 "($src1, sub(#$src2, $src3)")),
190 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
191 IntRegs:$src3))]>;
192
193class di_ALU64_didi_neg<string opc, Intrinsic IntID>
194 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
195 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
196 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
197
198class di_MInst_dididi_xacc<string opc, Intrinsic IntID>
199 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
200 DoubleRegs:$src2),
201 !strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")),
202 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
203 DoubleRegs:$src2))],
204 "$dst2 = $dst">;
205
206class si_MInst_sisisi_and<string opc, Intrinsic IntID>
207 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
208 IntRegs:$src3),
209 !strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")),
210 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
211 IntRegs:$src3))]>;
212
213class si_MInst_sisisi_andn<string opc, Intrinsic IntID>
214 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
215 IntRegs:$src3),
216 !strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")),
217 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
218 IntRegs:$src3))]>;
219
220class si_SInst_sisis10_andi<string opc, Intrinsic IntID>
221 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3),
222 !strconcat("$dst = ", !strconcat(opc ,
223 "($src1, and($src2, #$src3))")),
224 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
225 imm:$src3))]>;
226
227class si_MInst_sisisi_xor<string opc, Intrinsic IntID>
228 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
229 IntRegs:$src3),
230 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
231 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
232 IntRegs:$src3))]>;
233
234class si_MInst_sisisi_xorn<string opc, Intrinsic IntID>
235 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
236 IntRegs:$src3),
237 !strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")),
238 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
239 IntRegs:$src3))]>;
240
241class si_SInst_sisis10_or<string opc, Intrinsic IntID>
242 : SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3),
243 !strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")),
244 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
245 imm:$src3))]>;
246
247class si_MInst_sisisi_or<string opc, Intrinsic IntID>
248 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
249 IntRegs:$src3),
250 !strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")),
251 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
252 IntRegs:$src3))]>;
253
254class si_MInst_sisisi_orn<string opc, Intrinsic IntID>
255 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
256 IntRegs:$src3),
257 !strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")),
258 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
259 IntRegs:$src3))]>;
260
261class si_SInst_siu5_sat<string opc, Intrinsic IntID>
262 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
263 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")),
264 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
265
266
267/********************************************************************
268* ALU32/ALU *
269*********************************************************************/
270
271// ALU32 / ALU / Logical Operations.
272def Hexagon_A4_orn : si_ALU32_sisi_not <"or", int_hexagon_A4_orn>;
273def Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>;
274
275
276/********************************************************************
277* ALU32/PERM *
278*********************************************************************/
279
280// ALU32 / PERM / Combine Words Into Doublewords.
281def Hexagon_A4_combineir : di_ALU32_s8si <"combine", int_hexagon_A4_combineir>;
282def Hexagon_A4_combineri : di_ALU32_sis8 <"combine", int_hexagon_A4_combineri>;
283
284
285/********************************************************************
286* ALU32/PRED *
287*********************************************************************/
288
289// ALU32 / PRED / Conditional Shift Halfword.
290// ALU32 / PRED / Conditional Sign Extend.
291// ALU32 / PRED / Conditional Zero Extend.
292// ALU32 / PRED / Compare.
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]293def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
Sid Manning31f71252014-09-25 13:09:54 +0000[diff] [blame]294def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]295def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>;
Sid Manning31f71252014-09-25 13:09:54 +0000[diff] [blame]296
297def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
298def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
299def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]300
301// ALU32 / PRED / cmpare To General Register.
302def Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>;
303def Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>;
304def Hexagon_A4_rcmpeq : si_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpeq>;
305def Hexagon_A4_rcmpeqi : si_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpeqi>;
306
307
308/********************************************************************
309* CR *
310*********************************************************************/
311
312// CR / Corner Detection Acceleration.
313def Hexagon_C4_fastcorner9:
314 qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
315def Hexagon_C4_fastcorner9_not:
316 qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
317
318// CR / Logical Operations On Predicates.
319def Hexagon_C4_and_andn:
320 qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>;
321def Hexagon_C4_and_and:
322 qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>;
323def Hexagon_C4_and_orn:
324 qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>;
325def Hexagon_C4_and_or:
326 qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>;
327def Hexagon_C4_or_andn:
328 qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>;
329def Hexagon_C4_or_and:
330 qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>;
331def Hexagon_C4_or_orn:
332 qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
333def Hexagon_C4_or_or:
334 qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;
335
336
337/********************************************************************
338* XTYPE/ALU *
339*********************************************************************/
340
341// XTYPE / ALU / Add And Accumulate.
342def Hexagon_S4_addaddi:
343 si_SInst_si_addsis6 <"add", int_hexagon_S4_addaddi>;
344def Hexagon_S4_subaddi:
345 si_SInst_si_subs6si <"add", int_hexagon_S4_subaddi>;
346
347// XTYPE / ALU / Logical Doublewords.
348def Hexagon_S4_andnp:
349 di_ALU64_didi_neg <"and", int_hexagon_A4_andnp>;
350def Hexagon_S4_ornp:
351 di_ALU64_didi_neg <"or", int_hexagon_A4_ornp>;
352
353// XTYPE / ALU / Logical-logical Doublewords.
354def Hexagon_M4_xor_xacc:
355 di_MInst_dididi_xacc <"xor", int_hexagon_M4_xor_xacc>;
356
357// XTYPE / ALU / Logical-logical Words.
358def HEXAGON_M4_and_and:
359 si_MInst_sisisi_and <"and", int_hexagon_M4_and_and>;
360def HEXAGON_M4_and_or:
361 si_MInst_sisisi_and <"or", int_hexagon_M4_and_or>;
362def HEXAGON_M4_and_xor:
363 si_MInst_sisisi_and <"xor", int_hexagon_M4_and_xor>;
364def HEXAGON_M4_and_andn:
365 si_MInst_sisisi_andn <"and", int_hexagon_M4_and_andn>;
366def HEXAGON_M4_xor_and:
367 si_MInst_sisisi_xor <"and", int_hexagon_M4_xor_and>;
368def HEXAGON_M4_xor_or:
369 si_MInst_sisisi_xor <"or", int_hexagon_M4_xor_or>;
370def HEXAGON_M4_xor_andn:
371 si_MInst_sisisi_xorn <"and", int_hexagon_M4_xor_andn>;
372def HEXAGON_M4_or_and:
373 si_MInst_sisisi_or <"and", int_hexagon_M4_or_and>;
374def HEXAGON_M4_or_or:
375 si_MInst_sisisi_or <"or", int_hexagon_M4_or_or>;
376def HEXAGON_M4_or_xor:
377 si_MInst_sisisi_or <"xor", int_hexagon_M4_or_xor>;
378def HEXAGON_M4_or_andn:
379 si_MInst_sisisi_orn <"and", int_hexagon_M4_or_andn>;
380def HEXAGON_S4_or_andix:
381 si_SInst_sisis10_andi <"or", int_hexagon_S4_or_andix>;
382def HEXAGON_S4_or_andi:
383 si_SInst_sisis10_or <"and", int_hexagon_S4_or_andi>;
384def HEXAGON_S4_or_ori:
385 si_SInst_sisis10_or <"or", int_hexagon_S4_or_ori>;
386
387// XTYPE / ALU / Modulo wrap.
388def HEXAGON_A4_modwrapu:
389 si_ALU64_sisi <"modwrap", int_hexagon_A4_modwrapu>;
390
391// XTYPE / ALU / Round.
392def HEXAGON_A4_cround_ri:
393 si_SInst_siu5 <"cround", int_hexagon_A4_cround_ri>;
394def HEXAGON_A4_cround_rr:
395 si_SInst_sisi <"cround", int_hexagon_A4_cround_rr>;
396def HEXAGON_A4_round_ri:
397 si_SInst_siu5 <"round", int_hexagon_A4_round_ri>;
398def HEXAGON_A4_round_rr:
399 si_SInst_sisi <"round", int_hexagon_A4_round_rr>;
400def HEXAGON_A4_round_ri_sat:
401 si_SInst_siu5_sat <"round", int_hexagon_A4_round_ri_sat>;
402def HEXAGON_A4_round_rr_sat:
403 si_SInst_sisi_sat <"round", int_hexagon_A4_round_rr_sat>;
404
405// XTYPE / ALU / Vector reduce add unsigned halfwords.
406// XTYPE / ALU / Vector add bytes.
407// XTYPE / ALU / Vector conditional negate.
408// XTYPE / ALU / Vector maximum bytes.
409// XTYPE / ALU / Vector reduce maximum halfwords.
410// XTYPE / ALU / Vector reduce maximum words.
411// XTYPE / ALU / Vector minimum bytes.
412// XTYPE / ALU / Vector reduce minimum halfwords.
413// XTYPE / ALU / Vector reduce minimum words.
414// XTYPE / ALU / Vector subtract bytes.
415
416
417/********************************************************************
418* XTYPE/BIT *
419*********************************************************************/
420
421// XTYPE / BIT / Count leading.
422// XTYPE / BIT / Count trailing.
423// XTYPE / BIT / Extract bitfield.
424// XTYPE / BIT / Masked parity.
425// XTYPE / BIT / Bit reverse.
426// XTYPE / BIT / Split bitfield.
427
428
429/********************************************************************
430* XTYPE/COMPLEX *
431*********************************************************************/
432
433// XTYPE / COMPLEX / Complex add/sub halfwords.
434// XTYPE / COMPLEX / Complex add/sub words.
435// XTYPE / COMPLEX / Complex multiply 32x16.
436// XTYPE / COMPLEX / Vector reduce complex rotate.
437
438
439/********************************************************************
440* XTYPE/MPY *
441*********************************************************************/
442
443// XTYPE / COMPLEX / Complex add/sub halfwords.