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gerrit-public.fairphone.software / toolchain / llvm-project / a69bbe02a2352271e8b14542073f177e24c499c1 / . / llvm / test / CodeGen / PowerPC / testBitReverse.ll
blob: b6c78b4c3151a9b10f1f18c04b744def8fe69e9c [file] [log] [blame]
Tony Jiangc260e0e2017-07-07 16:41:55 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
4declare i32 @llvm.bitreverse.i32(i32)
5define i32 @testBitReverseIntrinsicI32(i32 %arg) {
6; CHECK-LABEL: testBitReverseIntrinsicI32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7; CHECK: # %bb.0:
Tony Jiangc260e0e2017-07-07 16:41:55 +0000[diff] [blame]8; CHECK-NEXT: lis 4, -21846
9; CHECK-NEXT: lis 5, 21845
10; CHECK-NEXT: slwi 6, 3, 1
11; CHECK-NEXT: srwi 3, 3, 1
Tony Jiangc260e0e2017-07-07 16:41:55 +0000[diff] [blame]12; CHECK-NEXT: ori 4, 4, 43690
13; CHECK-NEXT: ori 5, 5, 21845
Tony Jiangc260e0e2017-07-07 16:41:55 +0000[diff] [blame]14; CHECK-NEXT: and 4, 6, 4
Tony Jiangc260e0e2017-07-07 16:41:55 +0000[diff] [blame]15; CHECK-NEXT: and 3, 3, 5
Stefan Pintiliecb4f0c52018-07-04 18:54:25 +0000[diff] [blame]16; CHECK-NEXT: lis 5, 13107
Tony Jiangc260e0e2017-07-07 16:41:55 +0000[diff] [blame]17; CHECK-NEXT: or 3, 3, 4
Stefan Pintiliecb4f0c52018-07-04 18:54:25 +0000[diff] [blame]18; CHECK-NEXT: lis 4, -13108
19; CHECK-NEXT: ori 5, 5, 13107
20; CHECK-NEXT: slwi 6, 3, 2
21; CHECK-NEXT: ori 4, 4, 52428
22; CHECK-NEXT: srwi 3, 3, 2
23; CHECK-NEXT: and 4, 6, 4
24; CHECK-NEXT: and 3, 3, 5
25; CHECK-NEXT: lis 5, 3855
26; CHECK-NEXT: or 3, 3, 4
27; CHECK-NEXT: lis 4, -3856
28; CHECK-NEXT: ori 5, 5, 3855
29; CHECK-NEXT: slwi 6, 3, 4
30; CHECK-NEXT: ori 4, 4, 61680
Tony Jiangc260e0e2017-07-07 16:41:55 +0000[diff] [blame]31; CHECK-NEXT: srwi 3, 3, 4
Stefan Pintiliecb4f0c52018-07-04 18:54:25 +0000[diff] [blame]32; CHECK-NEXT: and 4, 6, 4
Tony Jiangc260e0e2017-07-07 16:41:55 +0000[diff] [blame]33; CHECK-NEXT: and 3, 3, 5
34; CHECK-NEXT: or 3, 3, 4
35; CHECK-NEXT: rotlwi 4, 3, 24
36; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
37; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31
38; CHECK-NEXT: rldicl 3, 4, 0, 32
39; CHECK-NEXT: blr
40 %res = call i32 @llvm.bitreverse.i32(i32 %arg)
41 ret i32 %res
42}
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]43
44declare i64 @llvm.bitreverse.i64(i64)
45define i64 @testBitReverseIntrinsicI64(i64 %arg) {
46; CHECK-LABEL: testBitReverseIntrinsicI64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]47; CHECK: # %bb.0:
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]48; CHECK-NEXT: lis 4, -21846
49; CHECK-NEXT: lis 5, 21845
QingShan Zhangc2b6c542018-09-03 03:14:29 +0000[diff] [blame]50; CHECK-NEXT: lis 7, -13108
51; CHECK-NEXT: lis 8, 13107
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]52; CHECK-NEXT: ori 4, 4, 43690
53; CHECK-NEXT: ori 5, 5, 21845
QingShan Zhangc2b6c542018-09-03 03:14:29 +0000[diff] [blame]54; CHECK-NEXT: ori 7, 7, 52428
55; CHECK-NEXT: ori 8, 8, 13107
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]56; CHECK-NEXT: sldi 4, 4, 32
57; CHECK-NEXT: sldi 5, 5, 32
58; CHECK-NEXT: oris 4, 4, 43690
59; CHECK-NEXT: oris 5, 5, 21845
QingShan Zhangc2b6c542018-09-03 03:14:29 +0000[diff] [blame]60; CHECK-NEXT: sldi 6, 3, 1
61; CHECK-NEXT: rldicl 3, 3, 63, 1
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]62; CHECK-NEXT: ori 4, 4, 43690
63; CHECK-NEXT: ori 5, 5, 21845
QingShan Zhangc2b6c542018-09-03 03:14:29 +0000[diff] [blame]64; CHECK-NEXT: sldi 7, 7, 32
65; CHECK-NEXT: sldi 8, 8, 32
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]66; CHECK-NEXT: and 4, 6, 4
67; CHECK-NEXT: and 3, 3, 5
QingShan Zhangc2b6c542018-09-03 03:14:29 +0000[diff] [blame]68; CHECK-NEXT: lis 5, -3856
69; CHECK-NEXT: oris 6, 7, 52428
70; CHECK-NEXT: oris 7, 8, 13107
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]71; CHECK-NEXT: or 3, 3, 4
QingShan Zhangc2b6c542018-09-03 03:14:29 +0000[diff] [blame]72; CHECK-NEXT: lis 4, 3855
73; CHECK-NEXT: ori 5, 5, 61680
74; CHECK-NEXT: ori 6, 6, 52428
75; CHECK-NEXT: ori 7, 7, 13107
76; CHECK-NEXT: ori 4, 4, 3855
77; CHECK-NEXT: sldi 8, 3, 2
78; CHECK-NEXT: rldicl 3, 3, 62, 2
79; CHECK-NEXT: and 6, 8, 6
80; CHECK-NEXT: and 3, 3, 7
81; CHECK-NEXT: sldi 5, 5, 32
82; CHECK-NEXT: sldi 4, 4, 32
83; CHECK-NEXT: or 3, 3, 6
84; CHECK-NEXT: oris 5, 5, 61680
85; CHECK-NEXT: oris 4, 4, 3855
86; CHECK-NEXT: sldi 6, 3, 4
87; CHECK-NEXT: ori 5, 5, 61680
88; CHECK-NEXT: ori 4, 4, 3855
89; CHECK-NEXT: rldicl 3, 3, 60, 4
90; CHECK-NEXT: and 5, 6, 5
91; CHECK-NEXT: and 3, 3, 4
92; CHECK-NEXT: or 3, 3, 5
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]93; CHECK-NEXT: rldicl 4, 3, 32, 32
Stefan Pintiliecb4f0c52018-07-04 18:54:25 +0000[diff] [blame]94; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
Fangrui Song2696db92017-10-30 16:03:44 +0000[diff] [blame]95; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
96; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
Fangrui Song2696db92017-10-30 16:03:44 +0000[diff] [blame]97; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
Stefan Pintiliecb4f0c52018-07-04 18:54:25 +0000[diff] [blame]98; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
Fangrui Song2696db92017-10-30 16:03:44 +0000[diff] [blame]99; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
100; CHECK-NEXT: sldi 3, 5, 32
101; CHECK-NEXT: or 3, 3, 6
Tony Jiangacefbcf2017-07-10 18:11:23 +0000[diff] [blame]102; CHECK-NEXT: blr
103 %res = call i64 @llvm.bitreverse.i64(i64 %arg)
104 ret i64 %res
105}