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gerrit-public.fairphone.software / toolchain / llvm-project / a7c40ef0224ba21c53d28b90fddbae0d4c5329c2 / . / llvm / lib / Target / Hexagon / HexagonInstrInfo.h
blob: 161db35c632a736777472d740e1cf5dbb5645e4a [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000[diff] [blame^]14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]16
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]17#include "HexagonRegisterInfo.h"
Brendon Cahoon6f358372012-02-08 18:25:47 +0000[diff] [blame]18#include "MCTargetDesc/HexagonBaseInfo.h"
Jyotsna Verma1d297502013-05-02 15:39:30 +0000[diff] [blame]19#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Chandler Carruth8a8cd2b2014-01-07 11:48:04 +0000[diff] [blame]20#include "llvm/Target/TargetFrameLowering.h"
21#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
Patrik Hagglund8d09a6c2014-03-15 09:11:41 +0000[diff] [blame]28struct EVT;
29
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]30class HexagonInstrInfo : public HexagonGenInstrInfo {
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]31 virtual void anchor();
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]32 const HexagonRegisterInfo RI;
Bill Wendling4a7a4082013-06-07 06:19:56 +0000[diff] [blame]33 const HexagonSubtarget &Subtarget;
Jyotsna Verma5ed51812013-05-01 21:37:34 +0000[diff] [blame]34 typedef unsigned Opcode_t;
35
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]36public:
37 explicit HexagonInstrInfo(HexagonSubtarget &ST);
38
39 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
40 /// such, whenever a client has an instance of instruction info, it should
41 /// always be able to get register info as well (through this method).
42 ///
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]43 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]44
45 /// isLoadFromStackSlot - If the specified machine instruction is a direct
46 /// load from a stack slot, return the virtual or physical register number of
47 /// the destination along with the FrameIndex of the loaded stack slot. If
48 /// not, return 0. This predicate must return 0 if the instruction has
49 /// any side effects other than loading from the stack slot.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]50 unsigned isLoadFromStackSlot(const MachineInstr *MI,
51 int &FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]52
53 /// isStoreToStackSlot - If the specified machine instruction is a direct
54 /// store to a stack slot, return the virtual or physical register number of
55 /// the source reg along with the FrameIndex of the loaded stack slot. If
56 /// not, return 0. This predicate must return 0 if the instruction has
57 /// any side effects other than storing to the stack slot.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]58 unsigned isStoreToStackSlot(const MachineInstr *MI,
59 int &FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]60
61
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]62 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
63 MachineBasicBlock *&FBB,
64 SmallVectorImpl<MachineOperand> &Cond,
65 bool AllowModify) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]66
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]67 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]68
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]69 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
70 MachineBasicBlock *FBB,
71 const SmallVectorImpl<MachineOperand> &Cond,
72 DebugLoc DL) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]73
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]74 bool analyzeCompare(const MachineInstr *MI,
75 unsigned &SrcReg, unsigned &SrcReg2,
76 int &Mask, int &Value) const override;
Krzysztof Parzyszekcfe285e2013-02-11 20:04:29 +0000[diff] [blame]77
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]78 void copyPhysReg(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator I, DebugLoc DL,
80 unsigned DestReg, unsigned SrcReg,
81 bool KillSrc) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]82
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]83 void storeRegToStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MBBI,
85 unsigned SrcReg, bool isKill, int FrameIndex,
86 const TargetRegisterClass *RC,
87 const TargetRegisterInfo *TRI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]88
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]89 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
90 SmallVectorImpl<MachineOperand> &Addr,
91 const TargetRegisterClass *RC,
92 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]93
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]94 void loadRegFromStackSlot(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MBBI,
96 unsigned DestReg, int FrameIndex,
97 const TargetRegisterClass *RC,
98 const TargetRegisterInfo *TRI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]99
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]100 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
101 SmallVectorImpl<MachineOperand> &Addr,
102 const TargetRegisterClass *RC,
103 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]104
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]105 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
106 MachineInstr* MI,
107 const SmallVectorImpl<unsigned> &Ops,
108 int FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]109
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]110 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
111 MachineInstr* MI,
112 const SmallVectorImpl<unsigned> &Ops,
113 MachineInstr* LoadMI) const override {
Craig Toppere73658d2014-04-28 04:05:08 +0000[diff] [blame]114 return nullptr;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]115 }
116
117 unsigned createVR(MachineFunction* MF, MVT VT) const;
118
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]119 bool isBranch(const MachineInstr *MI) const;
120 bool isPredicable(MachineInstr *MI) const override;
121 bool PredicateInstruction(MachineInstr *MI,
122 const SmallVectorImpl<MachineOperand> &Cond) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]123
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]124 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
125 unsigned ExtraPredCycles,
126 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]127
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]128 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
129 unsigned NumTCycles, unsigned ExtraTCycles,
130 MachineBasicBlock &FMBB,
131 unsigned NumFCycles, unsigned ExtraFCycles,
132 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]133
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]134 bool isPredicated(const MachineInstr *MI) const override;
135 bool isPredicated(unsigned Opcode) const;
136 bool isPredicatedTrue(const MachineInstr *MI) const;
137 bool isPredicatedTrue(unsigned Opcode) const;
138 bool isPredicatedNew(const MachineInstr *MI) const;
139 bool isPredicatedNew(unsigned Opcode) const;
140 bool DefinesPredicate(MachineInstr *MI,
141 std::vector<MachineOperand> &Pred) const override;
142 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
143 const SmallVectorImpl<MachineOperand> &Pred2) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]144
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]145 bool
146 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]147
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]148 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
149 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]150
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]151 DFAPacketizer*
Andrew Trickd06df962012-02-01 22:13:57 +0000[diff] [blame]152 CreateTargetScheduleState(const TargetMachine *TM,
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]153 const ScheduleDAG *DAG) const override;
Andrew Trickd06df962012-02-01 22:13:57 +0000[diff] [blame]154
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]155 bool isSchedulingBoundary(const MachineInstr *MI,
156 const MachineBasicBlock *MBB,
157 const MachineFunction &MF) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]158 bool isValidOffset(const int Opcode, const int Offset) const;
159 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
160 bool isMemOp(const MachineInstr *MI) const;
161 bool isSpillPredRegOp(const MachineInstr *MI) const;
162 bool isU6_3Immediate(const int value) const;
163 bool isU6_2Immediate(const int value) const;
164 bool isU6_1Immediate(const int value) const;
165 bool isU6_0Immediate(const int value) const;
166 bool isS4_3Immediate(const int value) const;
167 bool isS4_2Immediate(const int value) const;
168 bool isS4_1Immediate(const int value) const;
169 bool isS4_0Immediate(const int value) const;
170 bool isS12_Immediate(const int value) const;
171 bool isU6_Immediate(const int value) const;
172 bool isS8_Immediate(const int value) const;
173 bool isS6_Immediate(const int value) const;
174
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]175 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
176 bool isConditionalTransfer(const MachineInstr* MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000[diff] [blame]177 bool isConditionalALU32 (const MachineInstr* MI) const;
178 bool isConditionalLoad (const MachineInstr* MI) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]179 bool isConditionalStore(const MachineInstr* MI) const;
Jyotsna Vermaf1214a82013-03-05 18:51:42 +0000[diff] [blame]180 bool isNewValueInst(const MachineInstr* MI) const;
Jyotsna Verma84c47102013-05-06 18:49:23 +0000[diff] [blame]181 bool isNewValue(const MachineInstr* MI) const;
Jyotsna Vermaa46059b2013-03-28 19:44:04 +0000[diff] [blame]182 bool isDotNewInst(const MachineInstr* MI) const;
Jyotsna Verma438cec52013-05-10 20:58:11 +0000[diff] [blame]183 int GetDotOldOp(const int opc) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000[diff] [blame]184 int GetDotNewOp(const MachineInstr* MI) const;
Jyotsna Verma00681dc2013-05-09 19:16:07 +0000[diff] [blame]185 int GetDotNewPredOp(MachineInstr *MI,
186 const MachineBranchProbabilityInfo
187 *MBPI) const;
Jyotsna Verma438cec52013-05-10 20:58:11 +0000[diff] [blame]188 bool mayBeNewStore(const MachineInstr* MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]189 bool isDeallocRet(const MachineInstr *MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000[diff] [blame]190 unsigned getInvertedPredicatedOpcode(const int Opc) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]191 bool isExtendable(const MachineInstr* MI) const;
192 bool isExtended(const MachineInstr* MI) const;
193 bool isPostIncrement(const MachineInstr* MI) const;
194 bool isNewValueStore(const MachineInstr* MI) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000[diff] [blame]195 bool isNewValueStore(unsigned Opcode) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]196 bool isNewValueJump(const MachineInstr* MI) const;
Sirish Pande4bd20c52012-05-12 05:10:30 +0000[diff] [blame]197 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]198
Jyotsna Verma84256432013-03-01 17:37:13 +0000[diff] [blame]199
200 void immediateExtend(MachineInstr *MI) const;
201 bool isConstExtended(MachineInstr *MI) const;
Jyotsna Verma1d297502013-05-02 15:39:30 +0000[diff] [blame]202 int getDotNewPredJumpOp(MachineInstr *MI,
203 const MachineBranchProbabilityInfo *MBPI) const;
Jyotsna Verma84256432013-03-01 17:37:13 +0000[diff] [blame]204 unsigned getAddrMode(const MachineInstr* MI) const;
205 bool isOperandExtended(const MachineInstr *MI,
206 unsigned short OperandNum) const;
207 unsigned short getCExtOpNum(const MachineInstr *MI) const;
208 int getMinValue(const MachineInstr *MI) const;
209 int getMaxValue(const MachineInstr *MI) const;
210 bool NonExtEquivalentExists (const MachineInstr *MI) const;
211 short getNonExtOpcode(const MachineInstr *MI) const;
Jyotsna Verma5ed51812013-05-01 21:37:34 +0000[diff] [blame]212 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
213 bool PredOpcodeHasNot(Opcode_t Opcode) const;
214
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]215private:
216 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
217
218};
219
220}
221
222#endif