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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11//
12//===----------------------------------------------------------------------===//
13
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000015#ifndef LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
16#define LLVM_LIB_TARGET_R600_SIMACHINEFUNCTIONINFO_H
Tom Stellard75aadc22012-12-11 21:25:42 +000017
Vincent Lejeuneace6f732013-04-01 21:47:53 +000018#include "AMDGPUMachineFunction.h"
Tom Stellardc149dc02013-11-27 21:23:35 +000019#include <map>
Tom Stellard75aadc22012-12-11 21:25:42 +000020
21namespace llvm {
22
Tom Stellardc149dc02013-11-27 21:23:35 +000023class MachineRegisterInfo;
24
Tom Stellard75aadc22012-12-11 21:25:42 +000025/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
26/// tells the hardware which interpolation parameters to load.
Vincent Lejeuneace6f732013-04-01 21:47:53 +000027class SIMachineFunctionInfo : public AMDGPUMachineFunction {
Craig Topper5656db42014-04-29 07:57:24 +000028 void anchor() override;
Tom Stellard75aadc22012-12-11 21:25:42 +000029public:
Tom Stellardc149dc02013-11-27 21:23:35 +000030
31 struct SpilledReg {
32 unsigned VGPR;
33 int Lane;
34 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
35 SpilledReg() : VGPR(0), Lane(-1) { }
36 bool hasLane() { return Lane != -1;}
37 };
38
39 struct RegSpillTracker {
40 private:
41 unsigned CurrentLane;
42 std::map<unsigned, SpilledReg> SpilledRegisters;
43 public:
44 unsigned LaneVGPR;
45 RegSpillTracker() : CurrentLane(0), SpilledRegisters(), LaneVGPR(0) { }
Tom Stellardeba61072014-05-02 15:41:42 +000046 /// \p NumRegs The number of consecutive registers what need to be spilled.
47 /// This function will ensure that all registers are stored in
48 /// the same VGPR.
49 /// \returns The lane to be used for storing the first register.
50 unsigned reserveLanes(MachineRegisterInfo &MRI, MachineFunction *MF,
51 unsigned NumRegs = 1);
Tom Stellardc149dc02013-11-27 21:23:35 +000052 void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1);
53 const SpilledReg& getSpilledReg(unsigned FrameIndex);
54 bool programSpillsRegisters() { return !SpilledRegisters.empty(); }
55 };
56
57 // SIMachineFunctionInfo definition
58
Tom Stellard75aadc22012-12-11 21:25:42 +000059 SIMachineFunctionInfo(const MachineFunction &MF);
Christian Konig99ee0f42013-03-07 09:04:14 +000060 unsigned PSInputAddr;
Tom Stellardc149dc02013-11-27 21:23:35 +000061 struct RegSpillTracker SpillTracker;
Tom Stellardb02094e2014-07-21 15:45:01 +000062 unsigned NumUserSGPRs;
Tom Stellard75aadc22012-12-11 21:25:42 +000063};
64
65} // End namespace llvm
66
67
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000068#endif