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Tom Stellard75aadc22012-12-11 21:25:42 +00001//=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief AMDGPU specific subclass of TargetSubtarget.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef AMDGPUSUBTARGET_H
16#define AMDGPUSUBTARGET_H
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000017#include "AMDGPU.h"
Eric Christopherac4b69e2014-07-25 22:22:39 +000018#include "AMDGPUFrameLowering.h"
Tom Stellard2e59a452014-06-13 01:32:00 +000019#include "AMDGPUInstrInfo.h"
Eric Christopherac4b69e2014-07-25 22:22:39 +000020#include "AMDGPUIntrinsicInfo.h"
21#include "AMDGPUSubtarget.h"
22#include "R600ISelLowering.h"
23#include "llvm/IR/DataLayout.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000024#include "llvm/ADT/StringExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/Target/TargetSubtargetInfo.h"
27
28#define GET_SUBTARGETINFO_HEADER
29#include "AMDGPUGenSubtargetInfo.inc"
30
31#define MAX_CB_SIZE (1 << 16)
32
33namespace llvm {
34
35class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
Tom Stellard2e59a452014-06-13 01:32:00 +000036
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000037public:
38 enum Generation {
39 R600 = 0,
40 R700,
41 EVERGREEN,
42 NORTHERN_ISLANDS,
Tom Stellard6e1ee472013-10-29 16:37:28 +000043 SOUTHERN_ISLANDS,
44 SEA_ISLANDS
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000045 };
46
Tom Stellard75aadc22012-12-11 21:25:42 +000047private:
Tom Stellard75aadc22012-12-11 21:25:42 +000048 std::string DevName;
49 bool Is64bit;
Tom Stellard75aadc22012-12-11 21:25:42 +000050 bool DumpCode;
51 bool R600ALUInst;
Vincent Lejeunec2991642013-04-30 00:13:39 +000052 bool HasVertexCache;
Vincent Lejeunef9f4e1e2013-05-17 16:49:55 +000053 short TexVTXClauseSize;
Matt Arsenaultd782d052014-06-27 17:57:00 +000054 Generation Gen;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000055 bool FP64;
Matt Arsenaultf171cf22014-07-14 23:40:49 +000056 bool FP64Denormals;
57 bool FP32Denormals;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000058 bool CaymanISA;
Tom Stellarded0ceec2013-10-10 17:11:12 +000059 bool EnableIRStructurizer;
Matt Arsenaultd9a23ab2014-07-13 02:08:26 +000060 bool EnablePromoteAlloca;
Tom Stellard783893a2013-11-18 19:43:33 +000061 bool EnableIfCvt;
Tom Stellard8c347b02014-01-22 21:55:40 +000062 unsigned WavefrontSize;
Tom Stellard348273d2014-01-23 16:18:02 +000063 bool CFALUBug;
Tom Stellard880a80a2014-06-17 16:53:14 +000064 int LocalMemorySize;
Tom Stellard75aadc22012-12-11 21:25:42 +000065
Eric Christopherac4b69e2014-07-25 22:22:39 +000066 const DataLayout DL;
67 AMDGPUFrameLowering FrameLowering;
68 AMDGPUIntrinsicInfo IntrinsicInfo;
69 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
70 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
Tom Stellard75aadc22012-12-11 21:25:42 +000071 InstrItineraryData InstrItins;
72
73public:
Eric Christopherac4b69e2014-07-25 22:22:39 +000074 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
75 AMDGPUSubtarget &initializeSubtargetDependencies(StringRef GPU, StringRef FS);
Tom Stellard75aadc22012-12-11 21:25:42 +000076
Eric Christopherac4b69e2014-07-25 22:22:39 +000077 const AMDGPUFrameLowering *getFrameLowering() const { return &FrameLowering; }
78 const AMDGPUIntrinsicInfo *getIntrinsicInfo() const { return &IntrinsicInfo; }
79 const AMDGPUInstrInfo *getInstrInfo() const { return InstrInfo.get(); }
80 const AMDGPURegisterInfo *getRegisterInfo() const {
81 return &InstrInfo->getRegisterInfo();
Tom Stellard2e59a452014-06-13 01:32:00 +000082 }
Eric Christopherac4b69e2014-07-25 22:22:39 +000083 AMDGPUTargetLowering *getTargetLowering() const { return TLInfo.get(); }
84 const DataLayout *getDataLayout() const { return &DL; }
85 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
Matt Arsenaultd782d052014-06-27 17:57:00 +000086
Craig Topperee7b0f32014-04-30 05:53:27 +000087 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
Tom Stellard75aadc22012-12-11 21:25:42 +000088
Matt Arsenaultd782d052014-06-27 17:57:00 +000089 bool is64bit() const {
90 return Is64bit;
91 }
92
93 bool hasVertexCache() const {
94 return HasVertexCache;
95 }
96
97 short getTexVTXClauseSize() const {
Matt Arsenaultd9a23ab2014-07-13 02:08:26 +000098 return TexVTXClauseSize;
Matt Arsenaultd782d052014-06-27 17:57:00 +000099 }
100
101 Generation getGeneration() const {
102 return Gen;
103 }
104
105 bool hasHWFP64() const {
106 return FP64;
107 }
108
109 bool hasCaymanISA() const {
110 return CaymanISA;
111 }
Matt Arsenaultfae02982014-03-17 18:58:11 +0000112
Matt Arsenaultf171cf22014-07-14 23:40:49 +0000113 bool hasFP32Denormals() const {
114 return FP32Denormals;
115 }
116
117 bool hasFP64Denormals() const {
118 return FP64Denormals;
119 }
120
Matt Arsenaultfae02982014-03-17 18:58:11 +0000121 bool hasBFE() const {
122 return (getGeneration() >= EVERGREEN);
123 }
124
Matt Arsenault6e439652014-06-10 19:00:20 +0000125 bool hasBFI() const {
126 return (getGeneration() >= EVERGREEN);
127 }
128
Matt Arsenaultfae02982014-03-17 18:58:11 +0000129 bool hasBFM() const {
130 return hasBFE();
131 }
132
Matt Arsenault60425062014-06-10 19:18:28 +0000133 bool hasBCNT(unsigned Size) const {
134 if (Size == 32)
135 return (getGeneration() >= EVERGREEN);
136
Matt Arsenault3dd43fc2014-07-18 06:07:13 +0000137 if (Size == 64)
138 return (getGeneration() >= SOUTHERN_ISLANDS);
139
140 return false;
Matt Arsenault60425062014-06-10 19:18:28 +0000141 }
142
Tom Stellard50122a52014-04-07 19:45:41 +0000143 bool hasMulU24() const {
144 return (getGeneration() >= EVERGREEN);
145 }
146
147 bool hasMulI24() const {
148 return (getGeneration() >= SOUTHERN_ISLANDS ||
149 hasCaymanISA());
150 }
151
Jan Vesely6ddb8dd2014-07-15 15:51:09 +0000152 bool hasFFBL() const {
153 return (getGeneration() >= EVERGREEN);
154 }
155
156 bool hasFFBH() const {
157 return (getGeneration() >= EVERGREEN);
158 }
159
Matt Arsenaultd782d052014-06-27 17:57:00 +0000160 bool IsIRStructurizerEnabled() const {
161 return EnableIRStructurizer;
162 }
163
Matt Arsenaultd9a23ab2014-07-13 02:08:26 +0000164 bool isPromoteAllocaEnabled() const {
165 return EnablePromoteAlloca;
166 }
167
Matt Arsenaultd782d052014-06-27 17:57:00 +0000168 bool isIfCvtEnabled() const {
169 return EnableIfCvt;
170 }
171
172 unsigned getWavefrontSize() const {
173 return WavefrontSize;
174 }
175
Tom Stellarda40f9712014-01-22 21:55:43 +0000176 unsigned getStackEntrySize() const;
Matt Arsenaultd782d052014-06-27 17:57:00 +0000177
178 bool hasCFAluBug() const {
179 assert(getGeneration() <= NORTHERN_ISLANDS);
180 return CFALUBug;
181 }
182
183 int getLocalMemorySize() const {
184 return LocalMemorySize;
185 }
Tom Stellard75aadc22012-12-11 21:25:42 +0000186
Craig Topper5656db42014-04-29 07:57:24 +0000187 bool enableMachineScheduler() const override {
Andrew Trick978674b2013-09-20 05:14:41 +0000188 return getGeneration() <= NORTHERN_ISLANDS;
189 }
190
Tom Stellard75aadc22012-12-11 21:25:42 +0000191 // Helper functions to simplify if statements
Matt Arsenaultd782d052014-06-27 17:57:00 +0000192 bool isTargetELF() const {
193 return false;
194 }
Tom Stellard75aadc22012-12-11 21:25:42 +0000195
Matt Arsenaultd782d052014-06-27 17:57:00 +0000196 StringRef getDeviceName() const {
197 return DevName;
198 }
199
200 bool dumpCode() const {
201 return DumpCode;
202 }
203 bool r600ALUEncoding() const {
204 return R600ALUInst;
205 }
Tom Stellard75aadc22012-12-11 21:25:42 +0000206};
207
208} // End namespace llvm
209
210#endif // AMDGPUSUBTARGET_H