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gerrit-public.fairphone.software / toolchain / llvm-project / b10555cc618b4bfda5bd08bb76ebdfdbf817d68d / . / llvm / test / CodeGen / AMDGPU / llvm.AMDGPU.rcp.ll
blob: edd6e9a72f1bc4535cd7b858bcd335853979492f [file] [log] [blame]
Tom Stellard49f8bfd2015-01-06 18:00:21 +0000[diff] [blame]1; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
3; XUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s
Marek Olsak75170772015-01-27 17:27:15 +0000[diff] [blame]4; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
5; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
6; XUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]7
Matt Arsenault9acb9782014-07-24 06:59:24 +0000[diff] [blame]8; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG-SAFE -check-prefix=FUNC %s
9; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
10
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]11declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone
12declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
13
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]14declare float @llvm.sqrt.f32(float) nounwind readnone
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]15
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]16; FUNC-LABEL: {{^}}rcp_f32:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]17; SI: v_rcp_f32_e32
Matt Arsenault9acb9782014-07-24 06:59:24 +0000[diff] [blame]18; EG: RECIP_IEEE
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]19define void @rcp_f32(float addrspace(1)* %out, float %src) nounwind {
20 %rcp = call float @llvm.AMDGPU.rcp.f32(float %src) nounwind readnone
21 store float %rcp, float addrspace(1)* %out, align 4
22 ret void
23}
24
Matt Arsenault9acb9782014-07-24 06:59:24 +0000[diff] [blame]25; FIXME: Evergreen only ever does unsafe fp math.
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]26; FUNC-LABEL: {{^}}rcp_pat_f32:
Matt Arsenault9acb9782014-07-24 06:59:24 +0000[diff] [blame]27
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]28; SI-SAFE: v_rcp_f32_e32
29; XSI-SAFE-SPDENORM-NOT: v_rcp_f32_e32
Matt Arsenault9acb9782014-07-24 06:59:24 +0000[diff] [blame]30
31; EG: RECIP_IEEE
32
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]33define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
34 %rcp = fdiv float 1.0, %src
35 store float %rcp, float addrspace(1)* %out, align 4
36 ret void
37}
38
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]39; FUNC-LABEL: {{^}}rsq_rcp_pat_f32:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]40; SI-UNSAFE: v_rsq_f32_e32
41; SI-SAFE: v_sqrt_f32_e32
42; SI-SAFE: v_rcp_f32_e32
Matt Arsenault9acb9782014-07-24 06:59:24 +0000[diff] [blame]43
44; EG: RECIPSQRT_IEEE
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000[diff] [blame]45define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
46 %sqrt = call float @llvm.sqrt.f32(float %src) nounwind readnone
47 %rcp = call float @llvm.AMDGPU.rcp.f32(float %sqrt) nounwind readnone
48 store float %rcp, float addrspace(1)* %out, align 4
49 ret void
50}