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gerrit-public.fairphone.software / toolchain / llvm-project / b4ddc0845ab5260023e9afa3f7bc71a0bc731ae6 / . / llvm / test / CodeGen / AArch64 / atomic-ops.ll
blob: 36d0eda1e121d5c81b6cb3a3e99b46a44c709374 [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
2; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]3
4
5; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created
6; (i.e. reusing a register for status & data in store exclusive).
7; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], w[[NEW]], [x{{[0-9]+}}]
8; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], x[[NEW]], [x{{[0-9]+}}]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]9
10@var8 = global i8 0
11@var16 = global i16 0
12@var32 = global i32 0
13@var64 = global i64 0
14
15define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]16; CHECK-LABEL: test_atomic_load_add_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]17 %old = atomicrmw add i8* @var8, i8 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]18; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]19; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]20; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]21
22; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]23; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]24 ; w0 below is a reasonable guess but could change: it certainly comes into the
25 ; function there.
26; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]27; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]28; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]29; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]30
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]31; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]32 ret i8 %old
33}
34
35define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]36; CHECK-LABEL: test_atomic_load_add_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]37 %old = atomicrmw add i16* @var16, i16 %offset acquire
38; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]39; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]40; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]41
42; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]43; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]44 ; w0 below is a reasonable guess but could change: it certainly comes into the
45 ; function there.
46; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
47; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]48; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]49; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]50
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]51; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]52 ret i16 %old
53}
54
55define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]56; CHECK-LABEL: test_atomic_load_add_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]57 %old = atomicrmw add i32* @var32, i32 %offset release
58; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]59; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]60; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]61
62; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]63; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]64 ; w0 below is a reasonable guess but could change: it certainly comes into the
65 ; function there.
66; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]67; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]68; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]69; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]70
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]71; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]72 ret i32 %old
73}
74
75define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]76; CHECK-LABEL: test_atomic_load_add_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]77 %old = atomicrmw add i64* @var64, i64 %offset monotonic
78; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]79; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]80; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]81
82; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]83; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]84 ; x0 below is a reasonable guess but could change: it certainly comes into the
85 ; function there.
86; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0
87; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]88; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]89; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]90
91; CHECK: mov x0, x[[OLD]]
92 ret i64 %old
93}
94
95define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]96; CHECK-LABEL: test_atomic_load_sub_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]97 %old = atomicrmw sub i8* @var8, i8 %offset monotonic
98; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]99; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]100; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]101
102; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]103; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]104 ; w0 below is a reasonable guess but could change: it certainly comes into the
105 ; function there.
106; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
107; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]108; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]109; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]110
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]111; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]112 ret i8 %old
113}
114
115define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]116; CHECK-LABEL: test_atomic_load_sub_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]117 %old = atomicrmw sub i16* @var16, i16 %offset release
118; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]119; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]120; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]121
122; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]123; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]124 ; w0 below is a reasonable guess but could change: it certainly comes into the
125 ; function there.
126; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]127; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]128; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]129; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]130
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]131; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]132 ret i16 %old
133}
134
135define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]136; CHECK-LABEL: test_atomic_load_sub_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]137 %old = atomicrmw sub i32* @var32, i32 %offset acquire
138; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]139; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]140; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]141
142; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]143; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]144 ; w0 below is a reasonable guess but could change: it certainly comes into the
145 ; function there.
146; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
147; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]148; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]149; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]150
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]151; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]152 ret i32 %old
153}
154
155define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]156; CHECK-LABEL: test_atomic_load_sub_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]157 %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]158; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]159; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]160; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]161
162; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]163; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]164 ; x0 below is a reasonable guess but could change: it certainly comes into the
165 ; function there.
166; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]167; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]168; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]169; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]170
171; CHECK: mov x0, x[[OLD]]
172 ret i64 %old
173}
174
175define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]176; CHECK-LABEL: test_atomic_load_and_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]177 %old = atomicrmw and i8* @var8, i8 %offset release
178; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]179; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]180; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]181
182; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]183; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]184 ; w0 below is a reasonable guess but could change: it certainly comes into the
185 ; function there.
186; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]187; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]188; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]189; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]190
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]191; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]192 ret i8 %old
193}
194
195define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]196; CHECK-LABEL: test_atomic_load_and_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]197 %old = atomicrmw and i16* @var16, i16 %offset monotonic
198; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]199; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]200; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]201
202; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]203; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]204 ; w0 below is a reasonable guess but could change: it certainly comes into the
205 ; function there.
206; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
207; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]208; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]209; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]210
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]211; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]212 ret i16 %old
213}
214
215define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]216; CHECK-LABEL: test_atomic_load_and_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]217 %old = atomicrmw and i32* @var32, i32 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]218; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]219; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]220; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]221
222; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]223; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]224 ; w0 below is a reasonable guess but could change: it certainly comes into the
225 ; function there.
226; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]227; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]228; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]229; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]230
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]231; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]232 ret i32 %old
233}
234
235define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]236; CHECK-LABEL: test_atomic_load_and_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]237 %old = atomicrmw and i64* @var64, i64 %offset acquire
238; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]239; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]240; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]241
242; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]243; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]244 ; x0 below is a reasonable guess but could change: it certainly comes into the
245 ; function there.
246; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0
247; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]248; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]249; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]250
251; CHECK: mov x0, x[[OLD]]
252 ret i64 %old
253}
254
255define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]256; CHECK-LABEL: test_atomic_load_or_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]257 %old = atomicrmw or i8* @var8, i8 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]258; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]259; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]260; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]261
262; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]263; ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]264 ; w0 below is a reasonable guess but could change: it certainly comes into the
265 ; function there.
266; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]267; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]268; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]269; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]270
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]271; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]272 ret i8 %old
273}
274
275define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]276; CHECK-LABEL: test_atomic_load_or_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]277 %old = atomicrmw or i16* @var16, i16 %offset monotonic
278; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]279; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]280; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]281
282; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]283; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]284 ; w0 below is a reasonable guess but could change: it certainly comes into the
285 ; function there.
286; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
287; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]288; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]289; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]290
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]291; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]292 ret i16 %old
293}
294
295define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]296; CHECK-LABEL: test_atomic_load_or_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]297 %old = atomicrmw or i32* @var32, i32 %offset acquire
298; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]299; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]300; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]301
302; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]303; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]304 ; w0 below is a reasonable guess but could change: it certainly comes into the
305 ; function there.
306; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
307; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]308; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]309; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]310
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]311; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]312 ret i32 %old
313}
314
315define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]316; CHECK-LABEL: test_atomic_load_or_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]317 %old = atomicrmw or i64* @var64, i64 %offset release
318; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]319; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]320; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]321
322; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]323; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]324 ; x0 below is a reasonable guess but could change: it certainly comes into the
325 ; function there.
326; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]327; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]328; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]329; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]330
331; CHECK: mov x0, x[[OLD]]
332 ret i64 %old
333}
334
335define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]336; CHECK-LABEL: test_atomic_load_xor_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]337 %old = atomicrmw xor i8* @var8, i8 %offset acquire
338; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]339; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]340; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]341
342; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]343; ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]344 ; w0 below is a reasonable guess but could change: it certainly comes into the
345 ; function there.
346; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
347; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]348; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]349; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]350
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]351; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]352 ret i8 %old
353}
354
355define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]356; CHECK-LABEL: test_atomic_load_xor_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]357 %old = atomicrmw xor i16* @var16, i16 %offset release
358; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]359; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]360; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]361
362; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]363; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]364 ; w0 below is a reasonable guess but could change: it certainly comes into the
365 ; function there.
366; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]367; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]368; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]369; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]370
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]371; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]372 ret i16 %old
373}
374
375define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]376; CHECK-LABEL: test_atomic_load_xor_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]377 %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]378; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]379; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]380; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]381
382; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]383; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]384 ; w0 below is a reasonable guess but could change: it certainly comes into the
385 ; function there.
386; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]387; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]388; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]389; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]390
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]391; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]392 ret i32 %old
393}
394
395define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]396; CHECK-LABEL: test_atomic_load_xor_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]397 %old = atomicrmw xor i64* @var64, i64 %offset monotonic
398; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]399; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]400; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]401
402; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]403; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]404 ; x0 below is a reasonable guess but could change: it certainly comes into the
405 ; function there.
406; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0
407; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]408; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]409; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]410
411; CHECK: mov x0, x[[OLD]]
412 ret i64 %old
413}
414
415define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]416; CHECK-LABEL: test_atomic_load_xchg_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]417 %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
418; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]419; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]420; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]421
422; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]423; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]424 ; w0 below is a reasonable guess but could change: it certainly comes into the
425 ; function there.
426; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]427; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]428; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]429
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]430; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]431 ret i8 %old
432}
433
434define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]435; CHECK-LABEL: test_atomic_load_xchg_i16:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]436 %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]437; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]438; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]439; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]440
441; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]442; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]443 ; w0 below is a reasonable guess but could change: it certainly comes into the
444 ; function there.
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]445; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]446; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]447; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]448
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]449; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]450 ret i16 %old
451}
452
453define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]454; CHECK-LABEL: test_atomic_load_xchg_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]455 %old = atomicrmw xchg i32* @var32, i32 %offset release
456; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]457; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]458; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]459
460; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]461; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]462 ; w0 below is a reasonable guess but could change: it certainly comes into the
463 ; function there.
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]464; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]465; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]466; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]467
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]468; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]469 ret i32 %old
470}
471
472define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]473; CHECK-LABEL: test_atomic_load_xchg_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]474 %old = atomicrmw xchg i64* @var64, i64 %offset acquire
475; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]476; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]477; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]478
479; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]480; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]481 ; x0 below is a reasonable guess but could change: it certainly comes into the
482 ; function there.
483; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]484; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]485; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]486
487; CHECK: mov x0, x[[OLD]]
488 ret i64 %old
489}
490
491
492define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]493; CHECK-LABEL: test_atomic_load_min_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]494 %old = atomicrmw min i8* @var8, i8 %offset acquire
495; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]496; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]497; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]498
499; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]500; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]501 ; w0 below is a reasonable guess but could change: it certainly comes into the
502 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]503
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]504; CHECK-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
505; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxtb
506; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]507
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]508; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]509; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]510; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]511
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]512; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]513 ret i8 %old
514}
515
516define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]517; CHECK-LABEL: test_atomic_load_min_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]518 %old = atomicrmw min i16* @var16, i16 %offset release
519; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]520; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]521; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]522
523; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]524; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]525 ; w0 below is a reasonable guess but could change: it certainly comes into the
526 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]527
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]528; CHECK-NEXT: sxth w[[OLD_EXT:[0-9]+]], w[[OLD]]
529; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxth
530; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]531
532
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]533; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]534; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]535; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]536
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]537; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]538 ret i16 %old
539}
540
541define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]542; CHECK-LABEL: test_atomic_load_min_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]543 %old = atomicrmw min i32* @var32, i32 %offset monotonic
544; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]545; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]546; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]547
548; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]549; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]550 ; w0 below is a reasonable guess but could change: it certainly comes into the
551 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]552
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]553; CHECK-NEXT: cmp w[[OLD]], w0
554; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]555
556
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]557; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]558; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]559; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]560
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]561; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]562 ret i32 %old
563}
564
565define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]566; CHECK-LABEL: test_atomic_load_min_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]567 %old = atomicrmw min i64* @var64, i64 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]568; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]569; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]570; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]571
572; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]573; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]574 ; x0 below is a reasonable guess but could change: it certainly comes into the
575 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]576
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]577; CHECK-NEXT: cmp x[[OLD]], x0
578; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, le
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]579
580
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]581; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]582; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]583; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]584
585; CHECK: mov x0, x[[OLD]]
586 ret i64 %old
587}
588
589define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]590; CHECK-LABEL: test_atomic_load_max_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]591 %old = atomicrmw max i8* @var8, i8 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]592; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]593; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]594; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]595
596; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]597; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]598 ; w0 below is a reasonable guess but could change: it certainly comes into the
599 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]600
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]601; CHECK-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
602; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxtb
603; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]604
605
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]606; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]607; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]608; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]609
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]610; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]611 ret i8 %old
612}
613
614define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]615; CHECK-LABEL: test_atomic_load_max_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]616 %old = atomicrmw max i16* @var16, i16 %offset acquire
617; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]618; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]619; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]620
621; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]622; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]623 ; w0 below is a reasonable guess but could change: it certainly comes into the
624 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]625
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]626; CHECK-NEXT: sxth w[[OLD_EXT:[0-9]+]], w[[OLD]]
627; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxth
628; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]629
630
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]631; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]632; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]633; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]634
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]635; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]636 ret i16 %old
637}
638
639define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]640; CHECK-LABEL: test_atomic_load_max_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]641 %old = atomicrmw max i32* @var32, i32 %offset release
642; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]643; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]644; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]645
646; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]647; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]648 ; w0 below is a reasonable guess but could change: it certainly comes into the
649 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]650
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]651; CHECK-NEXT: cmp w[[OLD]], w0
652; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]653
654
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]655; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]656; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]657; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]658
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]659; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]660 ret i32 %old
661}
662
663define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]664; CHECK-LABEL: test_atomic_load_max_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]665 %old = atomicrmw max i64* @var64, i64 %offset monotonic
666; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]667; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]668; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]669
670; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]671; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]672 ; x0 below is a reasonable guess but could change: it certainly comes into the
673 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]674
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]675; CHECK-NEXT: cmp x[[OLD]], x0
676; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]677
678
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]679; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]680; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]681; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]682
683; CHECK: mov x0, x[[OLD]]
684 ret i64 %old
685}
686
687define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]688; CHECK-LABEL: test_atomic_load_umin_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]689 %old = atomicrmw umin i8* @var8, i8 %offset monotonic
690; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]691; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]692; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]693
694; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]695; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]696 ; w0 below is a reasonable guess but could change: it certainly comes into the
697 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]698
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]699; CHECK-NEXT: cmp w[[OLD]], w0, uxtb
700; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]701
702
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]703; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]704; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]705; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]706
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]707; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]708 ret i8 %old
709}
710
711define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]712; CHECK-LABEL: test_atomic_load_umin_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]713 %old = atomicrmw umin i16* @var16, i16 %offset acquire
714; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]715; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]716; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]717
718; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]719; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]720 ; w0 below is a reasonable guess but could change: it certainly comes into the
721 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]722
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]723; CHECK-NEXT: cmp w[[OLD]], w0, uxth
724; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]725
726
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]727; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]728; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]729; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]730
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]731; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]732 ret i16 %old
733}
734
735define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]736; CHECK-LABEL: test_atomic_load_umin_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]737 %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]738; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]739; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]740; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]741
742; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]743; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]744 ; w0 below is a reasonable guess but could change: it certainly comes into the
745 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]746
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]747; CHECK-NEXT: cmp w[[OLD]], w0
748; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]749
750
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]751; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]752; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]753; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]754
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]755; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]756 ret i32 %old
757}
758
759define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]760; CHECK-LABEL: test_atomic_load_umin_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]761 %old = atomicrmw umin i64* @var64, i64 %offset acq_rel
762; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]763; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]764; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]765
766; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]767; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]768 ; x0 below is a reasonable guess but could change: it certainly comes into the
769 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]770
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]771; CHECK-NEXT: cmp x[[OLD]], x0
772; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, ls
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]773
774
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]775; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]776; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]777; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]778
779; CHECK: mov x0, x[[OLD]]
780 ret i64 %old
781}
782
783define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]784; CHECK-LABEL: test_atomic_load_umax_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]785 %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
786; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]787; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]788; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]789
790; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]791; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]792 ; w0 below is a reasonable guess but could change: it certainly comes into the
793 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]794
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]795; CHECK-NEXT: cmp w[[OLD]], w0, uxtb
796; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]797
798
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]799; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]800; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]801; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]802
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]803; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]804 ret i8 %old
805}
806
807define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]808; CHECK-LABEL: test_atomic_load_umax_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]809 %old = atomicrmw umax i16* @var16, i16 %offset monotonic
810; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]811; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]812; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]813
814; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]815; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]816 ; w0 below is a reasonable guess but could change: it certainly comes into the
817 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]818
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]819; CHECK-NEXT: cmp w[[OLD]], w0, uxth
820; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]821
822
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]823; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]824; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]825; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]826
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]827; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]828 ret i16 %old
829}
830
831define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]832; CHECK-LABEL: test_atomic_load_umax_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]833 %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]834; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]835; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]836; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]837
838; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]839; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]840 ; w0 below is a reasonable guess but could change: it certainly comes into the
841 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]842
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]843; CHECK-NEXT: cmp w[[OLD]], w0
844; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]845
846
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]847; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]848; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]849; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]850
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]851; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]852 ret i32 %old
853}
854
855define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]856; CHECK-LABEL: test_atomic_load_umax_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]857 %old = atomicrmw umax i64* @var64, i64 %offset release
858; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]859; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]860; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]861
862; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]863; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]864 ; x0 below is a reasonable guess but could change: it certainly comes into the
865 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]866
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]867; CHECK-NEXT: cmp x[[OLD]], x0
868; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]869
870
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]871; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]872; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]873; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]874
875; CHECK: mov x0, x[[OLD]]
876 ret i64 %old
877}
878
879define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]880; CHECK-LABEL: test_atomic_cmpxchg_i8:
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]881 %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]882; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]883; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]884; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]885
886; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]887; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]888 ; w0 below is a reasonable guess but could change: it certainly comes into the
889 ; function there.
890; CHECK-NEXT: cmp w[[OLD]], w0
891; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
Tim Northoverb4ddc082014-05-30 10:09:59 +0000[diff] [blame^]892; CHECK: stxrb [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]893; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]894; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]895
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]896; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]897 ret i8 %old
898}
899
900define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]901; CHECK-LABEL: test_atomic_cmpxchg_i16:
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]902 %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]903; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]904; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]905; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]906
907; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]908; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]909 ; w0 below is a reasonable guess but could change: it certainly comes into the
910 ; function there.
911; CHECK-NEXT: cmp w[[OLD]], w0
912; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
Tim Northoverb4ddc082014-05-30 10:09:59 +0000[diff] [blame^]913; CHECK: stlxrh [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]914; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]915; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]916
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]917; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]918 ret i16 %old
919}
920
921define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]922; CHECK-LABEL: test_atomic_cmpxchg_i32:
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]923 %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release monotonic
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]924; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]925; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]926; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]927
928; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]929; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]930 ; w0 below is a reasonable guess but could change: it certainly comes into the
931 ; function there.
932; CHECK-NEXT: cmp w[[OLD]], w0
933; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
Tim Northoverb4ddc082014-05-30 10:09:59 +0000[diff] [blame^]934; CHECK: stlxr [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]935; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]936; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]937
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]938; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]939 ret i32 %old
940}
941
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]942define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]943; CHECK-LABEL: test_atomic_cmpxchg_i64:
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]944 %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic monotonic
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]945; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]946; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]947; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]948
949; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]950; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]951 ; w0 below is a reasonable guess but could change: it certainly comes into the
952 ; function there.
953; CHECK-NEXT: cmp x[[OLD]], x0
954; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
955 ; As above, w1 is a reasonable guess.
956; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]957; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]958; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]959
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]960; CHECK: str x[[OLD]],
961 store i64 %old, i64* @var64
962 ret void
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]963}
964
965define i8 @test_atomic_load_monotonic_i8() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]966; CHECK-LABEL: test_atomic_load_monotonic_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]967 %val = load atomic i8* @var8 monotonic, align 1
968; CHECK-NOT: dmb
969; CHECK: adrp x[[HIADDR:[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]970; CHECK: ldrb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]971; CHECK-NOT: dmb
972
973 ret i8 %val
974}
975
976define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]977; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]978 %addr_int = add i64 %base, %off
979 %addr = inttoptr i64 %addr_int to i8*
980
981 %val = load atomic i8* %addr monotonic, align 1
982; CHECK-NOT: dmb
983; CHECK: ldrb w0, [x0, x1]
984; CHECK-NOT: dmb
985
986 ret i8 %val
987}
988
989define i8 @test_atomic_load_acquire_i8() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]990; CHECK-LABEL: test_atomic_load_acquire_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]991 %val = load atomic i8* @var8 acquire, align 1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]992; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]993; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]994; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]995; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]996; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]997; CHECK: ldarb w0, [x[[ADDR]]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]998; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]999 ret i8 %val
1000}
1001
1002define i8 @test_atomic_load_seq_cst_i8() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1003; CHECK-LABEL: test_atomic_load_seq_cst_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1004 %val = load atomic i8* @var8 seq_cst, align 1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1005; CHECK-NOT: dmb
1006; CHECK: adrp [[HIADDR:x[0-9]+]], var8
1007; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]1008; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1009; CHECK-NOT: dmb
1010; CHECK: ldarb w0, [x[[ADDR]]]
1011; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1012 ret i8 %val
1013}
1014
1015define i16 @test_atomic_load_monotonic_i16() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1016; CHECK-LABEL: test_atomic_load_monotonic_i16:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1017 %val = load atomic i16* @var16 monotonic, align 2
1018; CHECK-NOT: dmb
1019; CHECK: adrp x[[HIADDR:[0-9]+]], var16
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1020; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]1021; CHECK: ldrh w0, [x[[HIADDR]], {{#?}}:lo12:var16]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1022; CHECK-NOT: dmb
1023
1024 ret i16 %val
1025}
1026
1027define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1028; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1029 %addr_int = add i64 %base, %off
1030 %addr = inttoptr i64 %addr_int to i32*
1031
1032 %val = load atomic i32* %addr monotonic, align 4
1033; CHECK-NOT: dmb
1034; CHECK: ldr w0, [x0, x1]
1035; CHECK-NOT: dmb
1036
1037 ret i32 %val
1038}
1039
1040define i64 @test_atomic_load_seq_cst_i64() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1041; CHECK-LABEL: test_atomic_load_seq_cst_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1042 %val = load atomic i64* @var64 seq_cst, align 8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1043; CHECK-NOT: dmb
1044; CHECK: adrp [[HIADDR:x[0-9]+]], var64
1045; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]1046; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1047; CHECK-NOT: dmb
1048; CHECK: ldar x0, [x[[ADDR]]]
1049; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1050 ret i64 %val
1051}
1052
1053define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1054; CHECK-LABEL: test_atomic_store_monotonic_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1055 store atomic i8 %val, i8* @var8 monotonic, align 1
1056; CHECK: adrp x[[HIADDR:[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]1057; CHECK: strb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1058
1059 ret void
1060}
1061
1062define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1063; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1064
1065 %addr_int = add i64 %base, %off
1066 %addr = inttoptr i64 %addr_int to i8*
1067
1068 store atomic i8 %val, i8* %addr monotonic, align 1
1069; CHECK: strb w2, [x0, x1]
1070
1071 ret void
1072}
1073define void @test_atomic_store_release_i8(i8 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1074; CHECK-LABEL: test_atomic_store_release_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1075 store atomic i8 %val, i8* @var8 release, align 1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1076; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1077; CHECK: adrp [[HIADDR:x[0-9]+]], var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1078; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]1079; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1080; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1081; CHECK: stlrb w0, [x[[ADDR]]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1082; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1083 ret void
1084}
1085
1086define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1087; CHECK-LABEL: test_atomic_store_seq_cst_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1088 store atomic i8 %val, i8* @var8 seq_cst, align 1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1089; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1090; CHECK: adrp [[HIADDR:x[0-9]+]], var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1091; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]1092; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1093; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1094; CHECK: stlrb w0, [x[[ADDR]]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1095; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1096
1097 ret void
1098}
1099
1100define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1101; CHECK-LABEL: test_atomic_store_monotonic_i16:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1102 store atomic i16 %val, i16* @var16 monotonic, align 2
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1103; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1104; CHECK: adrp x[[HIADDR:[0-9]+]], var16
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1105; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]1106; CHECK: strh w0, [x[[HIADDR]], {{#?}}:lo12:var16]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1107; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1108 ret void
1109}
1110
1111define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1112; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1113
1114 %addr_int = add i64 %base, %off
1115 %addr = inttoptr i64 %addr_int to i32*
1116
1117 store atomic i32 %val, i32* %addr monotonic, align 4
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1118; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1119; CHECK: str w2, [x0, x1]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1120; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1121
1122 ret void
1123}
1124
1125define void @test_atomic_store_release_i64(i64 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1126; CHECK-LABEL: test_atomic_store_release_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1127 store atomic i64 %val, i64* @var64 release, align 8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1128; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1129; CHECK: adrp [[HIADDR:x[0-9]+]], var64
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1130; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame]1131; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1132; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1133; CHECK: stlr x0, [x[[ADDR]]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1134; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1135 ret void
1136}