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gerrit-public.fairphone.software / toolchain / llvm-project / b51a70396e5d99bec354085f7cf96d127988f37b / . / clang / test / CodeGen / builtins-ppc-p9vector.c
blob: bfbb815854714ee34cef57f7025bd6448c7144c7 [file] [log] [blame]
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]1// REQUIRES: powerpc-registered-target
Eric Christopher758aad72017-03-21 22:06:18 +0000[diff] [blame]2// RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]3// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s \
Nemanja Ivanovic06d550b2016-10-05 19:11:36 +0000[diff] [blame]4// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]5
Eric Christopher758aad72017-03-21 22:06:18 +0000[diff] [blame]6// RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]7// RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s \
Nemanja Ivanovic06d550b2016-10-05 19:11:36 +0000[diff] [blame]8// RUN: -o - | FileCheck %s
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]9
10#include <altivec.h>
11
12vector signed char vsca, vscb;
13vector unsigned char vuca, vucb;
14vector bool char vbca, vbcb;
15vector signed short vssa, vssb;
16vector unsigned short vusa, vusb;
17vector bool short vbsa, vbsb;
18vector signed int vsia, vsib;
19vector unsigned int vuia, vuib;
20vector bool int vbia, vbib;
21vector signed long long vsla, vslb;
22vector unsigned long long vula, vulb;
23vector bool long long vbla, vblb;
24vector float vfa, vfb;
25vector double vda, vdb;
Nemanja Ivanovic4f69f922016-10-28 19:49:03 +0000[diff] [blame]26vector unsigned __int128 vui128a, vui128b;
27vector signed __int128 vsi128a, vsi128b;
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]28
Zaara Syedac1d29522016-11-15 18:04:13 +0000[diff] [blame]29float f[4] = { 23.4f, 56.7f, 89.0f, 12.3f };
30double d[2] = { 23.4, 56.7 };
31signed char sc[16] = { -8, 9, -10, 11, -12, 13, -14, 15,
32 -0, 1, -2, 3, -4, 5, -6, 7 };
33unsigned char uc[16] = { 8, 9, 10, 11, 12, 13, 14, 15,
34 0, 1, 2, 3, 4, 5, 6, 7 };
35signed short ss[8] = { -1, 2, -3, 4, -5, 6, -7, 8 };
36unsigned short us[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
37signed int si[4] = { -1, 2, -3, 4 };
38unsigned int ui[4] = { 0, 1, 2, 3 };
39signed long sl[2] = { -1L, 2L };
40unsigned long ul[2] = { 1L, 2L };
41signed long long sll[2] = { 1LL, 1LL };
42unsigned long long ull[2] = { -1LL, 1LL };
43signed __int128 sint128[1] = { -1 };
44unsigned __int128 uint128[1] = { 1 };
45
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]46unsigned test1(void) {
47// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
48// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
49// CHECK-BE: extractelement <2 x i64>
50// CHECK-BE: icmp eq i64 {{.*}}, 64
51// CHECK-BE: extractelement <2 x i64>
52// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]53// CHECK-BE: lshr i64 {{.*}}, 3
54// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
55// CHECK: @llvm.cttz.v2i64(<2 x i64>
56// CHECK: extractelement <2 x i64>
57// CHECK: icmp eq i64 {{.*}}, 64
58// CHECK: extractelement <2 x i64>
59// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]60// CHECK: lshr i64 {{.*}}, 3
61 return vec_first_match_index (vsca, vscb);
62}
63unsigned test2(void) {
64// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
65// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
66// CHECK-BE: extractelement <2 x i64>
67// CHECK-BE: icmp eq i64 {{.*}}, 64
68// CHECK-BE: extractelement <2 x i64>
69// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]70// CHECK-BE: lshr i64 {{.*}}, 3
71// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
72// CHECK: @llvm.cttz.v2i64(<2 x i64>
73// CHECK: extractelement <2 x i64>
74// CHECK: icmp eq i64 {{.*}}, 64
75// CHECK: extractelement <2 x i64>
76// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]77// CHECK: lshr i64 {{.*}}, 3
78 return vec_first_match_index (vuca, vucb);
79}
80unsigned test3(void) {
81// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
82// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
83// CHECK-BE: extractelement <2 x i64>
84// CHECK-BE: icmp eq i64 {{.*}}, 64
85// CHECK-BE: extractelement <2 x i64>
86// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]87// CHECK-BE: lshr i64 {{.*}}, 5
88// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
89// CHECK: @llvm.cttz.v2i64(<2 x i64>
90// CHECK: extractelement <2 x i64>
91// CHECK: icmp eq i64 {{.*}}, 64
92// CHECK: extractelement <2 x i64>
93// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]94// CHECK: lshr i64 {{.*}}, 5
95 return vec_first_match_index (vsia, vsib);
96}
97unsigned test4(void) {
98// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
99// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
100// CHECK-BE: extractelement <2 x i64>
101// CHECK-BE: icmp eq i64 {{.*}}, 64
102// CHECK-BE: extractelement <2 x i64>
103// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]104// CHECK-BE: lshr i64 {{.*}}, 5
105// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
106// CHECK: @llvm.cttz.v2i64(<2 x i64>
107// CHECK: extractelement <2 x i64>
108// CHECK: icmp eq i64 {{.*}}, 64
109// CHECK: extractelement <2 x i64>
110// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]111// CHECK: lshr i64 {{.*}}, 5
112 return vec_first_match_index (vuia, vuib);
113}
114unsigned test5(void) {
115// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
116// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
117// CHECK-BE: extractelement <2 x i64>
118// CHECK-BE: icmp eq i64 {{.*}}, 64
119// CHECK-BE: extractelement <2 x i64>
120// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]121// CHECK-BE: lshr i64 {{.*}}, 4
122// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
123// CHECK: @llvm.cttz.v2i64(<2 x i64>
124// CHECK: extractelement <2 x i64>
125// CHECK: icmp eq i64 {{.*}}, 64
126// CHECK: extractelement <2 x i64>
127// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]128// CHECK: lshr i64 {{.*}}, 4
129 return vec_first_match_index (vssa, vssb);
130}
131unsigned test6(void) {
132// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
133// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
134// CHECK-BE: extractelement <2 x i64>
135// CHECK-BE: icmp eq i64 {{.*}}, 64
136// CHECK-BE: extractelement <2 x i64>
137// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]138// CHECK-BE: lshr i64 {{.*}}, 4
139// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
140// CHECK: @llvm.cttz.v2i64(<2 x i64>
141// CHECK: extractelement <2 x i64>
142// CHECK: icmp eq i64 {{.*}}, 64
143// CHECK: extractelement <2 x i64>
144// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]145// CHECK: lshr i64 {{.*}}, 4
146 return vec_first_match_index (vusa, vusb);
147}
148unsigned test7(void) {
149// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
150// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
151// CHECK-BE: or <16 x i8>
152// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
153// CHECK-BE: or <16 x i8>
154// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
155// CHECK-BE: extractelement <2 x i64>
156// CHECK-BE: icmp eq i64 {{.*}}, 64
157// CHECK-BE: extractelement <2 x i64>
158// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]159// CHECK-BE: lshr i64 {{.*}}, 3
160// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
161// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
162// CHECK: or <16 x i8>
163// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
164// CHECK: or <16 x i8>
165// CHECK: @llvm.cttz.v2i64(<2 x i64>
166// CHECK: extractelement <2 x i64>
167// CHECK: icmp eq i64 {{.*}}, 64
168// CHECK: extractelement <2 x i64>
169// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]170// CHECK: lshr i64 {{.*}}, 3
171 return vec_first_match_or_eos_index (vsca, vscb);
172}
173unsigned test8(void) {
174// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
175// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
176// CHECK-BE: or <16 x i8>
177// CHECK-BE: @llvm.ppc.altivec.vcmpequb(<16 x i8>
178// CHECK-BE: or <16 x i8>
179// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
180// CHECK-BE: extractelement <2 x i64>
181// CHECK-BE: icmp eq i64 {{.*}}, 64
182// CHECK-BE: extractelement <2 x i64>
183// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]184// CHECK-BE: lshr i64 {{.*}}, 3
185// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
186// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
187// CHECK: or <16 x i8>
188// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
189// CHECK: or <16 x i8>
190// CHECK: @llvm.cttz.v2i64(<2 x i64>
191// CHECK: extractelement <2 x i64>
192// CHECK: icmp eq i64 {{.*}}, 64
193// CHECK: extractelement <2 x i64>
194// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]195// CHECK: lshr i64 {{.*}}, 3
196 return vec_first_match_or_eos_index (vuca, vucb);
197}
198unsigned test9(void) {
199// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
200// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
201// CHECK-BE: or <4 x i32>
202// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
203// CHECK-BE: or <4 x i32>
204// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
205// CHECK-BE: extractelement <2 x i64>
206// CHECK-BE: icmp eq i64 {{.*}}, 64
207// CHECK-BE: extractelement <2 x i64>
208// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]209// CHECK-BE: lshr i64 {{.*}}, 5
210// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
211// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
212// CHECK: or <4 x i32>
213// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
214// CHECK: or <4 x i32>
215// CHECK: @llvm.cttz.v2i64(<2 x i64>
216// CHECK: extractelement <2 x i64>
217// CHECK: icmp eq i64 {{.*}}, 64
218// CHECK: extractelement <2 x i64>
219// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]220// CHECK: lshr i64 {{.*}}, 5
221 return vec_first_match_or_eos_index (vsia, vsib);
222}
223unsigned test10(void) {
224// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
225// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
226// CHECK-BE: or <4 x i32>
227// CHECK-BE: @llvm.ppc.altivec.vcmpequw(<4 x i32>
228// CHECK-BE: or <4 x i32>
229// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
230// CHECK-BE: extractelement <2 x i64>
231// CHECK-BE: icmp eq i64 {{.*}}, 64
232// CHECK-BE: extractelement <2 x i64>
233// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]234// CHECK-BE: lshr i64 {{.*}}, 5
235// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
236// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
237// CHECK: or <4 x i32>
238// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
239// CHECK: or <4 x i32>
240// CHECK: @llvm.cttz.v2i64(<2 x i64>
241// CHECK: extractelement <2 x i64>
242// CHECK: icmp eq i64 {{.*}}, 64
243// CHECK: extractelement <2 x i64>
244// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]245// CHECK: lshr i64 {{.*}}, 5
246 return vec_first_match_or_eos_index (vuia, vuib);
247}
248unsigned test11(void) {
249// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
250// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
251// CHECK-BE: or <8 x i16>
252// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
253// CHECK-BE: or <8 x i16>
254// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
255// CHECK-BE: extractelement <2 x i64>
256// CHECK-BE: icmp eq i64 {{.*}}, 64
257// CHECK-BE: extractelement <2 x i64>
258// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]259// CHECK-BE: lshr i64 {{.*}}, 4
260// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
261// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
262// CHECK: or <8 x i16>
263// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
264// CHECK: or <8 x i16>
265// CHECK: @llvm.cttz.v2i64(<2 x i64>
266// CHECK: extractelement <2 x i64>
267// CHECK: icmp eq i64 {{.*}}, 64
268// CHECK: extractelement <2 x i64>
269// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]270// CHECK: lshr i64 {{.*}}, 4
271 return vec_first_match_or_eos_index (vssa, vssb);
272}
273unsigned test12(void) {
274// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
275// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
276// CHECK-BE: or <8 x i16>
277// CHECK-BE: @llvm.ppc.altivec.vcmpequh(<8 x i16>
278// CHECK-BE: or <8 x i16>
279// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
280// CHECK-BE: extractelement <2 x i64>
281// CHECK-BE: icmp eq i64 {{.*}}, 64
282// CHECK-BE: extractelement <2 x i64>
283// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]284// CHECK-BE: lshr i64 {{.*}}, 4
285// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
286// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
287// CHECK: or <8 x i16>
288// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
289// CHECK: or <8 x i16>
290// CHECK: @llvm.cttz.v2i64(<2 x i64>
291// CHECK: extractelement <2 x i64>
292// CHECK: icmp eq i64 {{.*}}, 64
293// CHECK: extractelement <2 x i64>
294// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]295// CHECK: lshr i64 {{.*}}, 4
296 return vec_first_match_or_eos_index (vusa, vusb);
297}
298unsigned test13(void) {
299// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
300// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
301// CHECK-BE: extractelement <2 x i64>
302// CHECK-BE: icmp eq i64 {{.*}}, 64
303// CHECK-BE: extractelement <2 x i64>
304// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]305// CHECK-BE: lshr i64 {{.*}}, 3
306// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
307// CHECK: @llvm.cttz.v2i64(<2 x i64>
308// CHECK: extractelement <2 x i64>
309// CHECK: icmp eq i64 {{.*}}, 64
310// CHECK: extractelement <2 x i64>
311// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]312// CHECK: lshr i64 {{.*}}, 3
313 return vec_first_mismatch_index (vsca, vscb);
314}
315unsigned test14(void) {
316// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
317// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
318// CHECK-BE: extractelement <2 x i64>
319// CHECK-BE: icmp eq i64 {{.*}}, 64
320// CHECK-BE: extractelement <2 x i64>
321// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]322// CHECK-BE: lshr i64 {{.*}}, 3
323// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
324// CHECK: @llvm.cttz.v2i64(<2 x i64>
325// CHECK: extractelement <2 x i64>
326// CHECK: icmp eq i64 {{.*}}, 64
327// CHECK: extractelement <2 x i64>
328// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]329// CHECK: lshr i64 {{.*}}, 3
330 return vec_first_mismatch_index (vuca, vucb);
331}
332unsigned test15(void) {
333// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
334// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
335// CHECK-BE: extractelement <2 x i64>
336// CHECK-BE: icmp eq i64 {{.*}}, 64
337// CHECK-BE: extractelement <2 x i64>
338// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]339// CHECK-BE: lshr i64 {{.*}}, 5
340// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
341// CHECK: @llvm.cttz.v2i64(<2 x i64>
342// CHECK: extractelement <2 x i64>
343// CHECK: icmp eq i64 {{.*}}, 64
344// CHECK: extractelement <2 x i64>
345// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]346// CHECK: lshr i64 {{.*}}, 5
347 return vec_first_mismatch_index (vsia, vsib);
348}
349unsigned test16(void) {
350// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
351// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
352// CHECK-BE: extractelement <2 x i64>
353// CHECK-BE: icmp eq i64 {{.*}}, 64
354// CHECK-BE: extractelement <2 x i64>
355// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]356// CHECK-BE: lshr i64 {{.*}}, 5
357// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
358// CHECK: @llvm.cttz.v2i64(<2 x i64>
359// CHECK: extractelement <2 x i64>
360// CHECK: icmp eq i64 {{.*}}, 64
361// CHECK: extractelement <2 x i64>
362// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]363// CHECK: lshr i64 {{.*}}, 5
364 return vec_first_mismatch_index (vuia, vuib);
365}
366unsigned test17(void) {
367// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
368// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
369// CHECK-BE: extractelement <2 x i64>
370// CHECK-BE: icmp eq i64 {{.*}}, 64
371// CHECK-BE: extractelement <2 x i64>
372// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]373// CHECK-BE: lshr i64 {{.*}}, 4
374// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
375// CHECK: @llvm.cttz.v2i64(<2 x i64>
376// CHECK: extractelement <2 x i64>
377// CHECK: icmp eq i64 {{.*}}, 64
378// CHECK: extractelement <2 x i64>
379// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]380// CHECK: lshr i64 {{.*}}, 4
381 return vec_first_mismatch_index (vssa, vssb);
382}
383unsigned test18(void) {
384// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
385// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
386// CHECK-BE: extractelement <2 x i64>
387// CHECK-BE: icmp eq i64 {{.*}}, 64
388// CHECK-BE: extractelement <2 x i64>
389// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]390// CHECK-BE: lshr i64 {{.*}}, 4
391// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
392// CHECK: @llvm.cttz.v2i64(<2 x i64>
393// CHECK: extractelement <2 x i64>
394// CHECK: icmp eq i64 {{.*}}, 64
395// CHECK: extractelement <2 x i64>
396// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]397// CHECK: lshr i64 {{.*}}, 4
398 return vec_first_mismatch_index (vusa, vusb);
399}
400unsigned test19(void) {
401// CHECK-BE: @llvm.ppc.altivec.vcmpnezb(<16 x i8>
402// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
403// CHECK-BE: extractelement <2 x i64>
404// CHECK-BE: icmp eq i64 {{.*}}, 64
405// CHECK-BE: extractelement <2 x i64>
406// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]407// CHECK-BE: lshr i64 {{.*}}, 3
408// CHECK: @llvm.ppc.altivec.vcmpnezb(<16 x i8>
409// CHECK: @llvm.cttz.v2i64(<2 x i64>
410// CHECK: extractelement <2 x i64>
411// CHECK: icmp eq i64 {{.*}}, 64
412// CHECK: extractelement <2 x i64>
413// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]414// CHECK: lshr i64 {{.*}}, 3
415 return vec_first_mismatch_or_eos_index (vsca, vscb);
416}
417unsigned test20(void) {
418// CHECK-BE: @llvm.ppc.altivec.vcmpnezb(<16 x i8>
419// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
420// CHECK-BE: extractelement <2 x i64>
421// CHECK-BE: icmp eq i64 {{.*}}, 64
422// CHECK-BE: extractelement <2 x i64>
423// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]424// CHECK-BE: lshr i64 {{.*}}, 3
425// CHECK: @llvm.ppc.altivec.vcmpnezb(<16 x i8>
426// CHECK: @llvm.cttz.v2i64(<2 x i64>
427// CHECK: extractelement <2 x i64>
428// CHECK: icmp eq i64 {{.*}}, 64
429// CHECK: extractelement <2 x i64>
430// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]431// CHECK: lshr i64 {{.*}}, 3
432 return vec_first_mismatch_or_eos_index (vuca, vucb);
433}
434unsigned test21(void) {
435// CHECK-BE: @llvm.ppc.altivec.vcmpnezw(<4 x i32>
436// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
437// CHECK-BE: extractelement <2 x i64>
438// CHECK-BE: icmp eq i64 {{.*}}, 64
439// CHECK-BE: extractelement <2 x i64>
440// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]441// CHECK-BE: lshr i64 {{.*}}, 5
442// CHECK: @llvm.ppc.altivec.vcmpnezw(<4 x i32>
443// CHECK: @llvm.cttz.v2i64(<2 x i64>
444// CHECK: extractelement <2 x i64>
445// CHECK: icmp eq i64 {{.*}}, 64
446// CHECK: extractelement <2 x i64>
447// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]448// CHECK: lshr i64 {{.*}}, 5
449 return vec_first_mismatch_or_eos_index (vsia, vsib);
450}
451unsigned test22(void) {
452// CHECK-BE: @llvm.ppc.altivec.vcmpnezw(<4 x i32>
453// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
454// CHECK-BE: extractelement <2 x i64>
455// CHECK-BE: icmp eq i64 {{.*}}, 64
456// CHECK-BE: extractelement <2 x i64>
457// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]458// CHECK-BE: lshr i64 {{.*}}, 5
459// CHECK: @llvm.ppc.altivec.vcmpnezw(<4 x i32>
460// CHECK: @llvm.cttz.v2i64(<2 x i64>
461// CHECK: extractelement <2 x i64>
462// CHECK: icmp eq i64 {{.*}}, 64
463// CHECK: extractelement <2 x i64>
464// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]465// CHECK: lshr i64 {{.*}}, 5
466 return vec_first_mismatch_or_eos_index (vuia, vuib);
467}
468unsigned test23(void) {
469// CHECK-BE: @llvm.ppc.altivec.vcmpnezh(<8 x i16>
470// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
471// CHECK-BE: extractelement <2 x i64>
472// CHECK-BE: icmp eq i64 {{.*}}, 64
473// CHECK-BE: extractelement <2 x i64>
474// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]475// CHECK-BE: lshr i64 {{.*}}, 4
476// CHECK: @llvm.ppc.altivec.vcmpnezh(<8 x i16>
477// CHECK: @llvm.cttz.v2i64(<2 x i64>
478// CHECK: extractelement <2 x i64>
479// CHECK: icmp eq i64 {{.*}}, 64
480// CHECK: extractelement <2 x i64>
481// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]482// CHECK: lshr i64 {{.*}}, 4
483 return vec_first_mismatch_or_eos_index (vssa, vssb);
484}
485unsigned test24(void) {
486// CHECK-BE: @llvm.ppc.altivec.vcmpnezh(<8 x i16>
487// CHECK-BE: @llvm.ctlz.v2i64(<2 x i64>
488// CHECK-BE: extractelement <2 x i64>
489// CHECK-BE: icmp eq i64 {{.*}}, 64
490// CHECK-BE: extractelement <2 x i64>
491// CHECK-BE: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]492// CHECK-BE: lshr i64 {{.*}}, 4
493// CHECK: @llvm.ppc.altivec.vcmpnezh(<8 x i16>
494// CHECK: @llvm.cttz.v2i64(<2 x i64>
495// CHECK: extractelement <2 x i64>
496// CHECK: icmp eq i64 {{.*}}, 64
497// CHECK: extractelement <2 x i64>
498// CHECK: add i64 {{.*}}, 64
Nemanja Ivanovic10e2b5d2016-09-27 10:45:22 +0000[diff] [blame]499// CHECK: lshr i64 {{.*}}, 4
500 return vec_first_mismatch_or_eos_index (vusa, vusb);
501}
502vector bool char test25(void) {
503// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
504// CHECK-BE-NEXT: ret <16 x i8>
505// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
506// CHECK-NEXT: ret <16 x i8>
507 return vec_cmpne (vbca, vbcb);
508}
509vector bool char test26(void) {
510// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
511// CHECK-BE-NEXT: ret <16 x i8>
512// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
513// CHECK-NEXT: ret <16 x i8>
514 return vec_cmpne (vsca, vscb);
515}
516vector bool char test27(void) {
517// CHECK-BE: @llvm.ppc.altivec.vcmpneb(<16 x i8>
518// CHECK-BE-NEXT: ret <16 x i8>
519// CHECK: @llvm.ppc.altivec.vcmpneb(<16 x i8>
520// CHECK-NEXT: ret <16 x i8>
521 return vec_cmpne (vuca, vucb);
522}
523vector bool int test28(void) {
524// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
525// CHECK-BE-NEXT: ret <4 x i32>
526// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
527// CHECK-NEXT: ret <4 x i32>
528 return vec_cmpne (vbia, vbib);
529}
530vector bool int test29(void) {
531// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
532// CHECK-BE-NEXT: ret <4 x i32>
533// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
534// CHECK-NEXT: ret <4 x i32>
535 return vec_cmpne (vsia, vsib);
536}
537vector bool int test30(void) {
538// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
539// CHECK-BE-NEXT: ret <4 x i32>
540// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
541// CHECK-NEXT: ret <4 x i32>
542 return vec_cmpne (vuia, vuib);
543}
544vector bool long long test31(void) {
545// CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>
546// CHECK-BE: xor <2 x i64>
547// CHECK-BE-NEXT: ret <2 x i64>
548// CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>
549// CHECK: xor <2 x i64>
550// CHECK-NEXT: ret <2 x i64>
551 return vec_cmpne (vbla, vblb);
552}
553vector bool long long test32(void) {
554// CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>
555// CHECK-BE: xor <2 x i64>
556// CHECK-BE-NEXT: ret <2 x i64>
557// CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>
558// CHECK: xor <2 x i64>
559// CHECK-NEXT: ret <2 x i64>
560 return vec_cmpne (vsla, vslb);
561}
562vector bool long long test33(void) {
563// CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>
564// CHECK-BE: xor <2 x i64>
565// CHECK-BE-NEXT: ret <2 x i64>
566// CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>
567// CHECK: xor <2 x i64>
568// CHECK-NEXT: ret <2 x i64>
569 return vec_cmpne (vula, vulb);
570}
571vector bool short test34(void) {
572// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
573// CHECK-BE-NEXT: ret <8 x i16>
574// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
575// CHECK-NEXT: ret <8 x i16>
576 return vec_cmpne (vbsa, vbsb);
577}
578vector bool short test35(void) {
579// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
580// CHECK-BE-NEXT: ret <8 x i16>
581// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
582// CHECK-NEXT: ret <8 x i16>
583 return vec_cmpne (vssa, vssb);
584}
585vector bool short test36(void) {
586// CHECK-BE: @llvm.ppc.altivec.vcmpneh(<8 x i16>
587// CHECK-BE-NEXT: ret <8 x i16>
588// CHECK: @llvm.ppc.altivec.vcmpneh(<8 x i16>
589// CHECK-NEXT: ret <8 x i16>
590 return vec_cmpne (vusa, vusb);
591}
592vector bool long long test37(void) {
593// CHECK-BE: @llvm.ppc.altivec.vcmpequd(<2 x i64>
594// CHECK-BE: xor <2 x i64>
595// CHECK-BE-NEXT: ret <2 x i64>
596// CHECK: @llvm.ppc.altivec.vcmpequd(<2 x i64>
597// CHECK: xor <2 x i64>
598// CHECK-NEXT: ret <2 x i64>
599 return vec_cmpne (vda, vdb);
600}
601vector bool int test38(void) {
602// CHECK-BE: @llvm.ppc.altivec.vcmpnew(<4 x i32>
603// CHECK-BE-NEXT: ret <4 x i32>
604// CHECK: @llvm.ppc.altivec.vcmpnew(<4 x i32>
605// CHECK-NEXT: ret <4 x i32>
606 return vec_cmpne (vfa, vfb);
607}
608vector signed char test39(void) {
609// CHECK-BE: @llvm.cttz.v16i8(<16 x i8>
610// CHECK-BE-NEXT: ret <16 x i8>
611// CHECK: @llvm.cttz.v16i8(<16 x i8>
612// CHECK-NEXT: ret <16 x i8>
613 return vec_cnttz (vsca);
614}
615vector unsigned char test40(void) {
616// CHECK-BE: @llvm.cttz.v16i8(<16 x i8>
617// CHECK-BE-NEXT: ret <16 x i8>
618// CHECK: @llvm.cttz.v16i8(<16 x i8>
619// CHECK-NEXT: ret <16 x i8>
620 return vec_cnttz (vuca);
621}
622vector signed int test41(void) {
623// CHECK-BE: @llvm.cttz.v4i32(<4 x i32>
624// CHECK-BE-NEXT: ret <4 x i32>
625// CHECK: @llvm.cttz.v4i32(<4 x i32>
626// CHECK-NEXT: ret <4 x i32>
627 return vec_cnttz (vsia);
628}
629vector unsigned int test42(void) {
630// CHECK-BE: @llvm.cttz.v4i32(<4 x i32>
631// CHECK-BE-NEXT: ret <4 x i32>
632// CHECK: @llvm.cttz.v4i32(<4 x i32>
633// CHECK-NEXT: ret <4 x i32>
634 return vec_cnttz (vuia);
635}
636vector signed long long test43(void) {
637// CHECK-BE: @llvm.cttz.v2i64(<2 x i64>
638// CHECK-BE-NEXT: ret <2 x i64>
639// CHECK: @llvm.cttz.v2i64(<2 x i64>
640// CHECK-NEXT: ret <2 x i64>
641 return vec_cnttz (vsla);
642}
643vector unsigned long long test44(void) {
644// CHECK-BE: @llvm.cttz.v2i64(<2 x i64>
645// CHECK-BE-NEXT: ret <2 x i64>
646// CHECK: @llvm.cttz.v2i64(<2 x i64>
647// CHECK-NEXT: ret <2 x i64>
648 return vec_cnttz (vula);
649}
650vector signed short test45(void) {
651// CHECK-BE: @llvm.cttz.v8i16(<8 x i16>
652// CHECK-BE-NEXT: ret <8 x i16>
653// CHECK: @llvm.cttz.v8i16(<8 x i16>
654// CHECK-NEXT: ret <8 x i16>
655 return vec_cnttz (vssa);
656}
657vector unsigned short test46(void) {
658// CHECK-BE: @llvm.cttz.v8i16(<8 x i16>
659// CHECK-BE-NEXT: ret <8 x i16>
660// CHECK: @llvm.cttz.v8i16(<8 x i16>
661// CHECK-NEXT: ret <8 x i16>
662 return vec_cnttz (vusa);
663}
664vector unsigned char test47(void) {
665// CHECK-BE: @llvm.ctpop.v16i8(<16 x i8>
666// CHECK-BE-NEXT: ret <16 x i8>
667// CHECK: @llvm.ctpop.v16i8(<16 x i8>
668// CHECK-NEXT: ret <16 x i8>
669 return vec_popcnt (vsca);
670}
671vector unsigned char test48(void) {
672// CHECK-BE: @llvm.ctpop.v16i8(<16 x i8>
673// CHECK-BE-NEXT: ret <16 x i8>
674// CHECK: @llvm.ctpop.v16i8(<16 x i8>
675// CHECK-NEXT: ret <16 x i8>
676 return vec_popcnt (vuca);
677}
678vector unsigned int test49(void) {
679// CHECK-BE: @llvm.ctpop.v4i32(<4 x i32>
680// CHECK-BE-NEXT: ret <4 x i32>
681// CHECK: @llvm.ctpop.v4i32(<4 x i32>
682// CHECK-NEXT: ret <4 x i32>
683 return vec_popcnt (vsia);
684}
685vector unsigned int test50(void) {
686// CHECK-BE: @llvm.ctpop.v4i32(<4 x i32>
687// CHECK-BE-NEXT: ret <4 x i32>
688// CHECK: @llvm.ctpop.v4i32(<4 x i32>
689// CHECK-NEXT: ret <4 x i32>
690 return vec_popcnt (vuia);
691}
692vector unsigned long long test51(void) {
693// CHECK-BE: @llvm.ctpop.v2i64(<2 x i64>
694// CHECK-BE-NEXT: ret <2 x i64>
695// CHECK: @llvm.ctpop.v2i64(<2 x i64>
696// CHECK-NEXT: ret <2 x i64>
697 return vec_popcnt (vsla);
698}
699vector unsigned long long test52(void) {
700// CHECK-BE: @llvm.ctpop.v2i64(<2 x i64>
701// CHECK-BE-NEXT: ret <2 x i64>
702// CHECK: @llvm.ctpop.v2i64(<2 x i64>
703// CHECK-NEXT: ret <2 x i64>
704 return vec_popcnt (vula);
705}
706vector unsigned short test53(void) {
707// CHECK-BE: @llvm.ctpop.v8i16(<8 x i16>
708// CHECK-BE-NEXT: ret <8 x i16>
709// CHECK: @llvm.ctpop.v8i16(<8 x i16>
710// CHECK-NEXT: ret <8 x i16>
711 return vec_popcnt (vssa);
712}
713vector unsigned short test54(void) {
714// CHECK-BE: @llvm.ctpop.v8i16(<8 x i16>
715// CHECK-BE-NEXT: ret <8 x i16>
716// CHECK: @llvm.ctpop.v8i16(<8 x i16>
717// CHECK-NEXT: ret <8 x i16>
718 return vec_popcnt (vusa);
719}
Nemanja Ivanovice5b62c82016-10-31 19:02:54 +0000[diff] [blame]720vector double test55(void) {
721// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
722// CHECK-BE-NEXT: ret <2 x double>
723// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
724// CHECK-NEXT: ret <2 x double>
725 return vec_insert_exp (vda,vulb);
726}
727vector double test56(void) {
728// CHECK-BE: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
729// CHECK-BE-NEXT: ret <2 x double>
730// CHECK: @llvm.ppc.vsx.xviexpdp(<2 x i64> %{{.+}}, <2 x i64>
731// CHECK-NEXT: ret <2 x double>
732 return vec_insert_exp (vula, vulb);
733}
734vector float test57(void) {
735// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
736// CHECK-BE-NEXT: ret <4 x float>
737// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
738// CHECK-NEXT: ret <4 x float>
739 return vec_insert_exp (vfa,vuib);
740}
741vector float test58(void) {
742// CHECK-BE: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
743// CHECK-BE-NEXT: ret <4 x float>
744// CHECK: @llvm.ppc.vsx.xviexpsp(<4 x i32> %{{.+}}, <4 x i32>
745// CHECK-NEXT: ret <4 x float>
746 return vec_insert_exp (vuia,vuib);
747}
Nemanja Ivanovic4f69f922016-10-28 19:49:03 +0000[diff] [blame]748signed int test59(void) {
749// CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
750// CHECK-BE-NEXT: ret i32
751// CHECK-LE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
752// CHECK-LE-NEXT: ret i32
753 return vec_cntlz_lsbb (vuca);
754}
755signed int test60(void) {
756// CHECK-BE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
757// CHECK-BE-NEXT: ret i32
758// CHECK-LE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
759// CHECK-LE-NEXT: ret i32
760 return vec_cntlz_lsbb (vsca);
761}
762signed int test61(void) {
763// CHECK-BE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
764// CHECK-BE-NEXT: ret i32
765// CHECK-LE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
766// CHECK-LE-NEXT: ret i32
767 return vec_cnttz_lsbb (vsca);
768}
769signed int test62(void) {
770// CHECK-BE: @llvm.ppc.altivec.vctzlsbb(<16 x i8>
771// CHECK-BE-NEXT: ret i32
772// CHECK-LE: @llvm.ppc.altivec.vclzlsbb(<16 x i8>
773// CHECK-LE-NEXT: ret i32
774 return vec_cnttz_lsbb (vuca);
775}
Nemanja Ivanovic4f69f922016-10-28 19:49:03 +0000[diff] [blame]776vector unsigned int test63(void) {
777// CHECK-BE: @llvm.ppc.altivec.vprtybw(<4 x i32>
778// CHECK-BE-NEXT: ret <4 x i32>
779// CHECK: @llvm.ppc.altivec.vprtybw(<4 x i32>
780// CHECK-NEXT: ret <4 x i32>
781 return vec_parity_lsbb (vuia);
782}
Nemanja Ivanovic4f69f922016-10-28 19:49:03 +0000[diff] [blame]783vector unsigned int test64(void) {
784// CHECK-BE: @llvm.ppc.altivec.vprtybw(<4 x i32>
785// CHECK-BE-NEXT: ret <4 x i32>
786// CHECK: @llvm.ppc.altivec.vprtybw(<4 x i32>
787// CHECK-NEXT: ret <4 x i32>
788 return vec_parity_lsbb (vsia);
789}
Nemanja Ivanovic4f69f922016-10-28 19:49:03 +0000[diff] [blame]790vector unsigned long long test65(void) {
791// CHECK-BE: @llvm.ppc.altivec.vprtybd(<2 x i64>
792// CHECK-BE-NEXT: ret <2 x i64>
793// CHECK: @llvm.ppc.altivec.vprtybd(<2 x i64>
794// CHECK-NEXT: ret <2 x i64>
795 return vec_parity_lsbb (vula);
796}
Nemanja Ivanovic4f69f922016-10-28 19:49:03 +0000[diff] [blame]797vector unsigned long long test66(void) {
798// CHECK-BE: @llvm.ppc.altivec.vprtybd(<2 x i64>
799// CHECK-BE-NEXT: ret <2 x i64>
800// CHECK: @llvm.ppc.altivec.vprtybd(<2 x i64>
801// CHECK-NEXT: ret <2 x i64>
802 return vec_parity_lsbb (vsla);
803}
804vector unsigned __int128 test67(void) {
805// CHECK-BE: @llvm.ppc.altivec.vprtybq(<1 x i128>
806// CHECK-BE-NEXT: ret <1 x i128>
807// CHECK: @llvm.ppc.altivec.vprtybq(<1 x i128>
808// CHECK-NEXT: ret <1 x i128>
809 return vec_parity_lsbb (vui128a);
810}
Nemanja Ivanovic4f69f922016-10-28 19:49:03 +0000[diff] [blame]811vector unsigned __int128 test68(void) {
812// CHECK-BE: @llvm.ppc.altivec.vprtybq(<1 x i128>
813// CHECK-BE-NEXT: ret <1 x i128>
814// CHECK: @llvm.ppc.altivec.vprtybq(<1 x i128>
815// CHECK-NEXT: ret <1 x i128>
816 return vec_parity_lsbb (vsi128a);
817}
Nemanja Ivanovic251f6dd2016-11-01 08:39:56 +0000[diff] [blame]818vector unsigned char test69(void) {
819// CHECK-BE: call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> {{.+}}, <16 x i8> {{.+}})
820// CHECK: call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> {{.+}}, <16 x i8> {{.+}})
821 return vec_absd(vuca, vucb);
822}
823vector unsigned short test70(void) {
824// CHECK-BE: call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> {{.+}}, <8 x i16> {{.+}})
825// CHECK: call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> {{.+}}, <8 x i16> {{.+}})
826 return vec_absd(vusa, vusb);
827}
828vector unsigned int test71(void) {
829// CHECK-BE: call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> {{.+}}, <4 x i32> {{.+}})
830// CHECK: call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> {{.+}}, <4 x i32> {{.+}})
831 return vec_absd(vuia, vuib);
832}
Nemanja Ivanovic05ce4ca2016-11-01 14:46:20 +0000[diff] [blame]833vector unsigned char test72(void) {
834// CHECK-BE: @llvm.ppc.altivec.vslv(<16 x i8>
835// CHECK-BE-NEXT: ret <16 x i8>
836// CHECK: @llvm.ppc.altivec.vslv(<16 x i8>
837// CHECK-NEXT: ret <16 x i8>
838 return vec_slv (vuca, vucb);
839}
840vector unsigned char test73(void) {
841// CHECK-BE: @llvm.ppc.altivec.vsrv(<16 x i8>
842// CHECK-BE-NEXT: ret <16 x i8>
843// CHECK: @llvm.ppc.altivec.vsrv(<16 x i8>
844// CHECK-NEXT: ret <16 x i8>
845 return vec_srv (vuca, vucb);
846}
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]847vector unsigned short test74(void) {
848// CHECK-BE: @llvm.ppc.vsx.xvcvsphp(<4 x float>
849// CHECK-BE: @llvm.ppc.vsx.xvcvsphp(<4 x float>
850// CHECK-BE: @llvm.ppc.altivec.vperm
851// CHECK: @llvm.ppc.vsx.xvcvsphp(<4 x float>
852// CHECK: @llvm.ppc.vsx.xvcvsphp(<4 x float>
853// CHECK: @llvm.ppc.altivec.vperm
854 return vec_pack_to_short_fp32(vfa, vfb);
855}
856vector unsigned int test75(void) {
857// CHECK-BE: @llvm.ppc.altivec.vrlwmi(<4 x i32
858// CHECK-BE-NEXT: ret <4 x i32>
859// CHECK: @llvm.ppc.altivec.vrlwmi(<4 x i32
860// CHECK-NEXT: ret <4 x i32>
861 return vec_rlmi(vuia, vuia, vuia);
862}
863vector unsigned long long test76(void) {
864// CHECK-BE: @llvm.ppc.altivec.vrldmi(<2 x i64
865// CHECK-BE-NEXT: ret <2 x i64>
866// CHECK: @llvm.ppc.altivec.vrldmi(<2 x i64
867// CHECK-NEXT: ret <2 x i64>
868 return vec_rlmi(vula, vula, vula);
869}
870vector unsigned int test77(void) {
Tony Jiang974e4c72017-01-11 20:59:42 +0000[diff] [blame]871// CHECK-BE: %[[RES1:.+]] = shl <4 x i32
872// CHECK-BE: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]873// CHECK-BE: @llvm.ppc.altivec.vrlwnm(<4 x i32
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]874// CHECK-BE: ret <4 x i32>
Tony Jiang974e4c72017-01-11 20:59:42 +0000[diff] [blame]875// CHECK: %[[RES1:.+]] = shl <4 x i32
876// CHECK: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]877// CHECK: @llvm.ppc.altivec.vrlwnm(<4 x i32
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]878// CHECK: ret <4 x i32>
879 return vec_rlnm(vuia, vuia, vuia);
880}
881vector unsigned long long test78(void) {
Tony Jiang974e4c72017-01-11 20:59:42 +0000[diff] [blame]882// CHECK-BE: %[[RES1:.+]] = shl <2 x i64
883// CHECK-BE: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]884// CHECK-BE: @llvm.ppc.altivec.vrldnm(<2 x i64
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]885// CHECK-BE-NEXT: ret <2 x i64>
Tony Jiang974e4c72017-01-11 20:59:42 +0000[diff] [blame]886// CHECK: %[[RES1:.+]] = shl <2 x i64
887// CHECK: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]888// CHECK: @llvm.ppc.altivec.vrldnm(<2 x i64
Nemanja Ivanovic4de00112016-11-11 22:34:44 +0000[diff] [blame]889// CHECK-NEXT: ret <2 x i64>
890 return vec_rlnm(vula, vula, vula);
891}
892vector double test79(void) {
893// CHECK-BE: extractelement <4 x float>
894// CHECK-BE: fpext float
895// CHECK-BE: insertelement <2 x double>
896// CHECK-BE: extractelement <4 x float>
897// CHECK-BE: fpext float
898// CHECK-BE: insertelement <2 x double>
899// CHECK: extractelement <4 x float>
900// CHECK: fpext float
901// CHECK: insertelement <2 x double>
902// CHECK: extractelement <4 x float>
903// CHECK: fpext float
904// CHECK: insertelement <2 x double>
905 return vec_unpackh(vfa);
906}
907vector double test80(void) {
908// CHECK-BE: extractelement <4 x float>
909// CHECK-BE: fpext float
910// CHECK-BE: insertelement <2 x double>
911// CHECK-BE: extractelement <4 x float>
912// CHECK-BE: fpext float
913// CHECK-BE: insertelement <2 x double>
914// CHECK: extractelement <4 x float>
915// CHECK: fpext float
916// CHECK: insertelement <2 x double>
917// CHECK: extractelement <4 x float>
918// CHECK: fpext float
919// CHECK: insertelement <2 x double>
920 return vec_unpackl(vfa);
921}
922vector double test81(void) {
923 // CHECK: extractelement <2 x double>
924 // CHECK: fptrunc double
925 // CHECK: insertelement <4 x float>
926 // CHECK: extractelement <2 x double>
927 // CHECK: fptrunc double
928 // CHECK: insertelement <4 x float>
929 // CHECK: extractelement <2 x double>
930 // CHECK: fptrunc double
931 // CHECK: insertelement <4 x float>
932 // CHECK: extractelement <2 x double>
933 // CHECK: fptrunc double
934 // CHECK: insertelement <4 x float>
935 // CHECK-LE: extractelement <2 x double>
936 // CHECK-LE: fptrunc double
937 // CHECK-LE: insertelement <4 x float>
938 // CHECK-LE: extractelement <2 x double>
939 // CHECK-LE: fptrunc double
940 // CHECK-LE: insertelement <4 x float>
941 // CHECK-LE: extractelement <2 x double>
942 // CHECK-LE: fptrunc double
943 // CHECK-LE: insertelement <4 x float>
944 // CHECK-LE: extractelement <2 x double>
945 // CHECK-LE: fptrunc double
946 // CHECK-LE: insertelement <4 x float>
947 return vec_pack(vda, vdb);
948}
Sean Fertile193430f2016-11-14 14:43:27 +0000[diff] [blame]949vector unsigned int test82(void) {
950// CHECK-BE: @llvm.ppc.vsx.xvxexpsp(<4 x float> {{.+}})
951// CHECK-BE-NEXT: ret <4 x i32>
952// CHECK: @llvm.ppc.vsx.xvxexpsp(<4 x float> {{.+}})
953// CHECK-NEXT: ret <4 x i32>
954 return vec_extract_exp(vfa);
955}
956vector unsigned long long test83(void) {
957// CHECK-BE: @llvm.ppc.vsx.xvxexpdp(<2 x double> {{.+}})
958// CHECK-BE-NEXT: ret <2 x i64>
959// CHECK: @llvm.ppc.vsx.xvxexpdp(<2 x double> {{.+}})
960// CHECK-NEXT: ret <2 x i64>
961 return vec_extract_exp(vda);
962}
963vector unsigned int test84(void) {
964// CHECK-BE: @llvm.ppc.vsx.xvxsigsp(<4 x float> {{.+}})
965// CHECK-BE-NEXT: ret <4 x i32>
966// CHECK: @llvm.ppc.vsx.xvxsigsp(<4 x float> {{.+}})
967// CHECK-NEXT: ret <4 x i32>
968 return vec_extract_sig(vfa);
969}
970vector unsigned long long test85(void) {
971// CHECK-BE: @llvm.ppc.vsx.xvxsigdp(<2 x double> {{.+}})
972// CHECK-BE-NEXT: ret <2 x i64>
973// CHECK: @llvm.ppc.vsx.xvxsigdp(<2 x double> {{.+}})
974// CHECK-NEXT: ret <2 x i64>
975 return vec_extract_sig(vda);
976}
977vector bool int test86(void) {
978// CHECK-BE: @llvm.ppc.vsx.xvtstdcsp(<4 x float> {{.+}}, i32 127)
979// CHECK-BE-NEXT: ret <4 x i32>
980// CHECK: @llvm.ppc.vsx.xvtstdcsp(<4 x float> {{.+}}, i32 127)
981// CHECK-NEXT: ret <4 x i32>
982 return vec_test_data_class(vfa, __VEC_CLASS_FP_NOT_NORMAL);
983}
984vector bool long long test87(void) {
985// CHECK-BE: @llvm.ppc.vsx.xvtstdcdp(<2 x double> {{.+}}, i32 127)
Gabor Buellabf591792018-07-04 11:29:21 +0000[diff] [blame]986// CHECK-BE-NEXT: ret <2 x i64>
Sean Fertile193430f2016-11-14 14:43:27 +0000[diff] [blame]987// CHECK: @llvm.ppc.vsx.xvtstdcdp(<2 x double> {{.+}}, i32 127)
988// CHECK-NEXT: ret <2 x i64>
989 return vec_test_data_class(vda, __VEC_CLASS_FP_NOT_NORMAL);
990}
Zaara Syedac1d29522016-11-15 18:04:13 +0000[diff] [blame]991vector unsigned char test88(void) {
992// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
993// CHECK-BE-NEXT-NEXT: ret <16 x i8>
994// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
995// CHECK-NEXT-NEXT: ret <16 x i8>
996 return vec_xl_len(uc,0);
997}
998vector signed char test89(void) {
999// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1000// CHECK-BE-NEXT-NEXT: ret <16 x i8>
1001// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1002// CHECK-NEXT-NEXT: ret <16 x i8>
1003 return vec_xl_len(sc,0);
1004}
1005vector unsigned short test90(void) {
1006// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1007// CHECK-BE-NEXT-NEXT: ret <8 x i16>
1008// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1009// CHECK-NEXT-NEXT: ret <8 x i16>
1010 return vec_xl_len(us,0);
1011}
1012vector signed short test91(void) {
1013// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1014// CHECK-BE-NEXT-NEXT: ret <8 x i16>
1015// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1016// CHECK-NEXT-NEXT: ret <8 x i16>
1017 return vec_xl_len(ss,0);
1018}
1019vector unsigned int test92(void) {
1020// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1021// CHECK-BE-NEXT: ret <4 x i32>
1022// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1023// CHECK-NEXT: ret <4 x i32>
1024 return vec_xl_len(ui,0);
1025}
1026
1027vector signed int test93(void) {
1028// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1029// CHECK-BE-NEXT: ret <4 x i32>
1030// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1031// CHECK-NEXT: ret <4 x i32>
1032 return vec_xl_len(si,0);
1033}
1034
1035vector float test94(void) {
1036// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1037// CHECK-BE-NEXT-NEXT: ret <4 x i32>
1038// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1039// CHECK-NEXT-NEXT: ret <4 x i32>
1040 return vec_xl_len(f,0);
1041}
1042
1043vector unsigned long long test95(void) {
1044// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1045// CHECK-BE-NEXT-NEXT: ret <2 x i64>
1046// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1047// CHECK-NEXT-NEXT: ret <2 x i64>
1048 return vec_xl_len(ull,0);
1049}
1050
1051vector signed long long test96(void) {
1052// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1053// CHECK-BE-NEXT-NEXT: ret <2 x i64>
1054// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1055// CHECK-NEXT-NEXT: ret <2 x i64>
1056 return vec_xl_len(sll,0);
1057}
1058
1059vector double test97(void) {
1060// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1061// CHECK-BE-NEXT-NEXT: ret <2 x i64>
1062// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1063// CHECK-NEXT-NEXT: ret <2 x i64>
1064 return vec_xl_len(d,0);
1065}
1066
1067vector unsigned __int128 test98(void) {
1068// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1069// CHECK-BE-NEXT-NEXT: ret <1 x i128>
1070// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1071// CHECK-NEXT-NEXT: ret <1 x i128>
1072 return vec_xl_len(uint128,0);
1073}
1074
1075vector signed __int128 test99(void) {
1076// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1077// CHECK-BE-NEXT-NEXT: ret <1 x i128>
1078// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
1079// CHECK-NEXT-NEXT: ret <1 x i128>
1080 return vec_xl_len(sint128,0);
1081}
1082
1083void test100(void) {
1084// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1085// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1086 return vec_xst_len(vuca,uc,0);
1087}
1088
1089void test101(void) {
1090// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1091// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1092 return vec_xst_len(vsca,sc,0);
1093}
1094
1095void test102(void) {
1096// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1097// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1098 return vec_xst_len(vusa,us,0);
1099}
1100
1101void test103(void) {
1102// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1103// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1104 return vec_xst_len(vssa,ss,0);
1105}
1106
1107void test104(void) {
1108// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1109// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1110 return vec_xst_len(vuia,ui,0);
1111}
1112
1113void test105(void) {
1114// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1115// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1116 return vec_xst_len(vsia,si,0);
1117}
1118
1119void test106(void) {
1120// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1121// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1122 return vec_xst_len(vfa,f,0);
1123}
1124
1125void test107(void) {
1126// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1127// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1128 return vec_xst_len(vula,ull,0);
1129}
1130
1131void test108(void) {
1132// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1133// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1134 return vec_xst_len(vsla,sll,0);
1135}
1136
1137void test109(void) {
1138// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1139// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1140 return vec_xst_len(vda,d,0);
1141}
1142
1143void test110(void) {
1144// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1145// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1146 return vec_xst_len(vui128a,uint128,0);
1147}
1148
1149void test111(void) {
1150// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1151// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1152 return vec_xst_len(vsi128a,sint128,0);
1153}
1154
1155vector unsigned char test112(void) {
1156// CHECK-BE: @llvm.ppc.vsx.lxvll(i8* %{{.+}}, i64
1157// CHECK: @llvm.ppc.vsx.lxvll(i8* %{{.+}}, i64
1158// CHECK: @llvm.ppc.altivec.lvsr(i8* %{{.+}}
1159// CHECK: @llvm.ppc.altivec.vperm
1160 return vec_xl_len_r(uc,0);
1161}
1162void test113(void) {
1163// CHECK-BE: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1164// CHECK: @llvm.ppc.altivec.lvsl(i8* %{{.+}}
1165// CHECK: @llvm.ppc.altivec.vperm
1166// CHECK: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
1167 return vec_xst_len_r(vuca,uc,0);
1168}
1169vector float test114(void) {
Sean Fertilea9548932016-11-14 18:47:15 +0000[diff] [blame]1170// CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3>
1171// CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
1172// CHECK-BE-NEXT: ret <4 x float>
Sean Fertile96d9e0e2017-01-05 21:43:30 +0000[diff] [blame]1173// CHECK: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef>
1174// CHECK: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
1175// CHECK-NEXT: ret <4 x float>
Sean Fertilea9548932016-11-14 18:47:15 +0000[diff] [blame]1176 return vec_extract_fp32_from_shorth(vusa);
1177}
Zaara Syedac1d29522016-11-15 18:04:13 +0000[diff] [blame]1178vector float test115(void) {
Sean Fertilea9548932016-11-14 18:47:15 +0000[diff] [blame]1179// CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7>
1180// CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
1181// CHECK-BE-NEXT: ret <4 x float>
Sean Fertile96d9e0e2017-01-05 21:43:30 +0000[diff] [blame]1182// CHECK: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef>
1183// CHECK: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
1184// CHECK-NEXT: ret <4 x float>
Sean Fertilea9548932016-11-14 18:47:15 +0000[diff] [blame]1185 return vec_extract_fp32_from_shortl(vusa);
1186}
Sean Fertile96d9e0e2017-01-05 21:43:30 +0000[diff] [blame]1187vector unsigned char test116(void) {
1188// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <2 x i64> {{.+}}, i32 7)
1189// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
1190// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>
1191// CHECK-NEXT: [[T2:%.+]] = bitcast <2 x i64> [[T1]] to <4 x i32>
1192// CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 5)
1193// CHECK-NEXT: bitcast <4 x i32> [[T3]] to <16 x i8>
1194 return vec_insert4b(vuia, vuca, 7);
1195}
1196vector unsigned char test117(void) {
1197// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <2 x i64> {{.+}}, i32 12)
1198// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
1199// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>
1200// CHECK-NEXT: [[T2:%.+]] = bitcast <2 x i64> [[T1]] to <4 x i32>
1201// CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 0)
1202// CHECK-NEXT: bitcast <4 x i32> [[T3]] to <16 x i8>
1203 return vec_insert4b(vuia, vuca, 13);
1204}
1205vector unsigned long long test118(void) {
1206// CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 11)
1207// CHECK-BE-NEXT: ret <2 x i64>
1208// CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 1)
1209// CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0>
1210// CHECK-NEXT: ret <2 x i64>
1211 return vec_extract4b(vuca, 11);
1212}
1213vector unsigned long long test119(void) {
1214// CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 0)
1215// CHECK-BE-NEXT: ret <2 x i64>
1216// CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 12)
1217// CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0>
1218// CHECK-NEXT: ret <2 x i64>
1219 return vec_extract4b(vuca, -5);
1220}
1221