Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 1 | //===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the Mips32/64 implementation of TargetFrameLowering class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "MipsSEFrameLowering.h" |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 15 | #include "MCTargetDesc/MipsBaseInfo.h" |
Chandler Carruth | ed0881b | 2012-12-03 16:50:05 +0000 | [diff] [blame] | 16 | #include "MipsAnalyzeImmediate.h" |
| 17 | #include "MipsMachineFunction.h" |
| 18 | #include "MipsSEInstrInfo.h" |
Eric Christopher | 4cdb3f9 | 2014-07-02 23:29:55 +0000 | [diff] [blame] | 19 | #include "MipsSubtarget.h" |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 21 | #include "llvm/CodeGen/MachineFunction.h" |
| 22 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 23 | #include "llvm/CodeGen/MachineModuleInfo.h" |
| 24 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Akira Hatanaka | 5852e3b | 2012-11-03 00:05:43 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/RegisterScavenging.h" |
Chandler Carruth | 9fb823b | 2013-01-02 11:36:10 +0000 | [diff] [blame] | 26 | #include "llvm/IR/DataLayout.h" |
| 27 | #include "llvm/IR/Function.h" |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 28 | #include "llvm/Support/CommandLine.h" |
Chandler Carruth | ed0881b | 2012-12-03 16:50:05 +0000 | [diff] [blame] | 29 | #include "llvm/Target/TargetOptions.h" |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 30 | |
| 31 | using namespace llvm; |
| 32 | |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 33 | namespace { |
| 34 | typedef MachineBasicBlock::iterator Iter; |
| 35 | |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 36 | static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) { |
| 37 | if (Mips::ACC64RegClass.contains(Src)) |
| 38 | return std::make_pair((unsigned)Mips::PseudoMFHI, |
| 39 | (unsigned)Mips::PseudoMFLO); |
| 40 | |
| 41 | if (Mips::ACC64DSPRegClass.contains(Src)) |
| 42 | return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP); |
| 43 | |
| 44 | if (Mips::ACC128RegClass.contains(Src)) |
| 45 | return std::make_pair((unsigned)Mips::PseudoMFHI64, |
| 46 | (unsigned)Mips::PseudoMFLO64); |
| 47 | |
| 48 | return std::make_pair(0, 0); |
| 49 | } |
| 50 | |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 51 | /// Helper class to expand pseudos. |
| 52 | class ExpandPseudo { |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 53 | public: |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 54 | ExpandPseudo(MachineFunction &MF); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 55 | bool expand(); |
| 56 | |
| 57 | private: |
| 58 | bool expandInstr(MachineBasicBlock &MBB, Iter I); |
Akira Hatanaka | 5705f54 | 2013-05-02 23:07:05 +0000 | [diff] [blame] | 59 | void expandLoadCCond(MachineBasicBlock &MBB, Iter I); |
| 60 | void expandStoreCCond(MachineBasicBlock &MBB, Iter I); |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 61 | void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize); |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 62 | void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, |
| 63 | unsigned MFLoOpc, unsigned RegSize); |
Akira Hatanaka | 4254319 | 2013-04-30 23:22:09 +0000 | [diff] [blame] | 64 | bool expandCopy(MachineBasicBlock &MBB, Iter I); |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 65 | bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, |
| 66 | unsigned MFLoOpc); |
Sasa Stankovic | b976fee | 2014-07-14 09:40:29 +0000 | [diff] [blame^] | 67 | bool expandBuildPairF64(MachineBasicBlock &MBB, |
| 68 | MachineBasicBlock::iterator I, bool FP64) const; |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 69 | |
| 70 | MachineFunction &MF; |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 71 | MachineRegisterInfo &MRI; |
| 72 | }; |
| 73 | } |
| 74 | |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 75 | ExpandPseudo::ExpandPseudo(MachineFunction &MF_) |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 76 | : MF(MF_), MRI(MF.getRegInfo()) {} |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 77 | |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 78 | bool ExpandPseudo::expand() { |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 79 | bool Expanded = false; |
| 80 | |
| 81 | for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end(); |
| 82 | BB != BBEnd; ++BB) |
| 83 | for (Iter I = BB->begin(), End = BB->end(); I != End;) |
| 84 | Expanded |= expandInstr(*BB, I++); |
| 85 | |
| 86 | return Expanded; |
| 87 | } |
| 88 | |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 89 | bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 90 | switch(I->getOpcode()) { |
Akira Hatanaka | 5705f54 | 2013-05-02 23:07:05 +0000 | [diff] [blame] | 91 | case Mips::LOAD_CCOND_DSP: |
Akira Hatanaka | 5705f54 | 2013-05-02 23:07:05 +0000 | [diff] [blame] | 92 | expandLoadCCond(MBB, I); |
| 93 | break; |
| 94 | case Mips::STORE_CCOND_DSP: |
Akira Hatanaka | 5705f54 | 2013-05-02 23:07:05 +0000 | [diff] [blame] | 95 | expandStoreCCond(MBB, I); |
| 96 | break; |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 97 | case Mips::LOAD_ACC64: |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 98 | case Mips::LOAD_ACC64DSP: |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 99 | expandLoadACC(MBB, I, 4); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 100 | break; |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 101 | case Mips::LOAD_ACC128: |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 102 | expandLoadACC(MBB, I, 8); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 103 | break; |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 104 | case Mips::STORE_ACC64: |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 105 | expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4); |
| 106 | break; |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 107 | case Mips::STORE_ACC64DSP: |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 108 | expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 109 | break; |
Akira Hatanaka | 00fcf2e | 2013-08-08 21:54:26 +0000 | [diff] [blame] | 110 | case Mips::STORE_ACC128: |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 111 | expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 112 | break; |
Sasa Stankovic | b976fee | 2014-07-14 09:40:29 +0000 | [diff] [blame^] | 113 | case Mips::BuildPairF64: |
| 114 | if (expandBuildPairF64(MBB, I, false)) |
| 115 | MBB.erase(I); |
| 116 | return false; |
| 117 | case Mips::BuildPairF64_64: |
| 118 | if (expandBuildPairF64(MBB, I, true)) |
| 119 | MBB.erase(I); |
| 120 | return false; |
Akira Hatanaka | 4254319 | 2013-04-30 23:22:09 +0000 | [diff] [blame] | 121 | case TargetOpcode::COPY: |
| 122 | if (!expandCopy(MBB, I)) |
| 123 | return false; |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 124 | break; |
| 125 | default: |
| 126 | return false; |
| 127 | } |
| 128 | |
| 129 | MBB.erase(I); |
| 130 | return true; |
| 131 | } |
| 132 | |
Akira Hatanaka | 5705f54 | 2013-05-02 23:07:05 +0000 | [diff] [blame] | 133 | void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) { |
| 134 | // load $vr, FI |
| 135 | // copy ccond, $vr |
| 136 | |
| 137 | assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); |
| 138 | |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 139 | const MipsSEInstrInfo &TII = |
| 140 | *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); |
| 141 | const MipsRegisterInfo &RegInfo = |
| 142 | *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); |
| 143 | |
Akira Hatanaka | 5705f54 | 2013-05-02 23:07:05 +0000 | [diff] [blame] | 144 | const TargetRegisterClass *RC = RegInfo.intRegClass(4); |
| 145 | unsigned VR = MRI.createVirtualRegister(RC); |
| 146 | unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); |
| 147 | |
| 148 | TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); |
| 149 | BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) |
| 150 | .addReg(VR, RegState::Kill); |
| 151 | } |
| 152 | |
| 153 | void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) { |
| 154 | // copy $vr, ccond |
| 155 | // store $vr, FI |
| 156 | |
| 157 | assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); |
| 158 | |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 159 | const MipsSEInstrInfo &TII = |
| 160 | *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); |
| 161 | const MipsRegisterInfo &RegInfo = |
| 162 | *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); |
| 163 | |
Akira Hatanaka | 5705f54 | 2013-05-02 23:07:05 +0000 | [diff] [blame] | 164 | const TargetRegisterClass *RC = RegInfo.intRegClass(4); |
| 165 | unsigned VR = MRI.createVirtualRegister(RC); |
| 166 | unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); |
| 167 | |
| 168 | BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) |
| 169 | .addReg(Src, getKillRegState(I->getOperand(0).isKill())); |
| 170 | TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); |
| 171 | } |
| 172 | |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 173 | void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 174 | unsigned RegSize) { |
| 175 | // load $vr0, FI |
| 176 | // copy lo, $vr0 |
| 177 | // load $vr1, FI + 4 |
| 178 | // copy hi, $vr1 |
| 179 | |
| 180 | assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); |
| 181 | |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 182 | const MipsSEInstrInfo &TII = |
| 183 | *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); |
| 184 | const MipsRegisterInfo &RegInfo = |
| 185 | *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); |
| 186 | |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 187 | const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); |
| 188 | unsigned VR0 = MRI.createVirtualRegister(RC); |
| 189 | unsigned VR1 = MRI.createVirtualRegister(RC); |
| 190 | unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); |
| 191 | unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); |
| 192 | unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); |
| 193 | DebugLoc DL = I->getDebugLoc(); |
| 194 | const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); |
| 195 | |
| 196 | TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); |
| 197 | BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); |
| 198 | TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); |
| 199 | BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); |
| 200 | } |
| 201 | |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 202 | void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I, |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 203 | unsigned MFHiOpc, unsigned MFLoOpc, |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 204 | unsigned RegSize) { |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 205 | // mflo $vr0, src |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 206 | // store $vr0, FI |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 207 | // mfhi $vr1, src |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 208 | // store $vr1, FI + 4 |
| 209 | |
| 210 | assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); |
| 211 | |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 212 | const MipsSEInstrInfo &TII = |
| 213 | *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); |
| 214 | const MipsRegisterInfo &RegInfo = |
| 215 | *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); |
| 216 | |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 217 | const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); |
| 218 | unsigned VR0 = MRI.createVirtualRegister(RC); |
| 219 | unsigned VR1 = MRI.createVirtualRegister(RC); |
| 220 | unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); |
| 221 | unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 222 | DebugLoc DL = I->getDebugLoc(); |
| 223 | |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 224 | BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 225 | TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0); |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 226 | BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 227 | TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); |
| 228 | } |
| 229 | |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 230 | bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) { |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 231 | unsigned Src = I->getOperand(1).getReg(); |
| 232 | std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src); |
Akira Hatanaka | 4254319 | 2013-04-30 23:22:09 +0000 | [diff] [blame] | 233 | |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 234 | if (!Opcodes.first) |
| 235 | return false; |
Akira Hatanaka | 4254319 | 2013-04-30 23:22:09 +0000 | [diff] [blame] | 236 | |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 237 | return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second); |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 238 | } |
| 239 | |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 240 | bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, |
| 241 | unsigned MFHiOpc, unsigned MFLoOpc) { |
| 242 | // mflo $vr0, src |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 243 | // copy dst_lo, $vr0 |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 244 | // mfhi $vr1, src |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 245 | // copy dst_hi, $vr1 |
| 246 | |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 247 | const MipsSEInstrInfo &TII = |
| 248 | *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); |
| 249 | const MipsRegisterInfo &RegInfo = |
| 250 | *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); |
| 251 | |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 252 | unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg(); |
| 253 | unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2; |
| 254 | const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 255 | unsigned VR0 = MRI.createVirtualRegister(RC); |
| 256 | unsigned VR1 = MRI.createVirtualRegister(RC); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 257 | unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); |
| 258 | unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); |
| 259 | unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 260 | DebugLoc DL = I->getDebugLoc(); |
| 261 | |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 262 | BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 263 | BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) |
| 264 | .addReg(VR0, RegState::Kill); |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 265 | BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 266 | BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) |
| 267 | .addReg(VR1, RegState::Kill); |
Akira Hatanaka | 4254319 | 2013-04-30 23:22:09 +0000 | [diff] [blame] | 268 | return true; |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 269 | } |
| 270 | |
Sasa Stankovic | b976fee | 2014-07-14 09:40:29 +0000 | [diff] [blame^] | 271 | /// This method expands the same instruction that MipsSEInstrInfo:: |
| 272 | /// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is |
| 273 | /// not available. It is implemented here because frame indexes are |
| 274 | /// eliminated before MipsSEInstrInfo::expandBuildPairF64 is called. |
| 275 | bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB, |
| 276 | MachineBasicBlock::iterator I, |
| 277 | bool FP64) const { |
| 278 | // For fpxx and when mthc1 is not available, use: |
| 279 | // spill + reload via ldc1 |
| 280 | // |
| 281 | // The case where dmtc1 is available doesn't need to be handled here |
| 282 | // because it never creates a BuildPairF64 node. |
| 283 | |
| 284 | const TargetMachine &TM = MF.getTarget(); |
| 285 | if (TM.getSubtarget<MipsSubtarget>().isABI_FPXX() |
| 286 | && !TM.getSubtarget<MipsSubtarget>().hasMTHC1()) { |
| 287 | const MipsSEInstrInfo &TII = |
| 288 | *static_cast<const MipsSEInstrInfo*>(TM.getInstrInfo()); |
| 289 | const MipsRegisterInfo &TRI = |
| 290 | *static_cast<const MipsRegisterInfo*>(TM.getRegisterInfo()); |
| 291 | |
| 292 | unsigned DstReg = I->getOperand(0).getReg(); |
| 293 | unsigned LoReg = I->getOperand(1).getReg(); |
| 294 | unsigned HiReg = I->getOperand(2).getReg(); |
| 295 | |
| 296 | // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are |
| 297 | // the cases where mthc1 is not available). |
| 298 | assert(!TM.getSubtarget<MipsSubtarget>().isFP64bit()); |
| 299 | |
| 300 | const TargetRegisterClass *RC = &Mips::GPR32RegClass; |
| 301 | const TargetRegisterClass *RC2 = &Mips::AFGR64RegClass; |
| 302 | |
| 303 | int FI = MF.getInfo<MipsFunctionInfo>()->getBuildPairF64_FI(RC2); |
| 304 | TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI, |
| 305 | 0); |
| 306 | TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI, |
| 307 | 4); |
| 308 | TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, 0); |
| 309 | return true; |
| 310 | } |
| 311 | |
| 312 | return false; |
| 313 | } |
| 314 | |
Eric Christopher | 4cdb3f9 | 2014-07-02 23:29:55 +0000 | [diff] [blame] | 315 | MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) |
| 316 | : MipsFrameLowering(STI, STI.stackAlignment()) {} |
| 317 | |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 318 | unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const { |
| 319 | static const unsigned EhDataReg[] = { |
| 320 | Mips::A0, Mips::A1, Mips::A2, Mips::A3 |
| 321 | }; |
| 322 | static const unsigned EhDataReg64[] = { |
| 323 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64 |
| 324 | }; |
| 325 | |
| 326 | return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I]; |
| 327 | } |
| 328 | |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 329 | void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { |
| 330 | MachineBasicBlock &MBB = MF.front(); |
| 331 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 332 | MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 333 | |
Akira Hatanaka | 88d76cf | 2012-07-31 23:52:55 +0000 | [diff] [blame] | 334 | const MipsSEInstrInfo &TII = |
| 335 | *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 336 | const MipsRegisterInfo &RegInfo = |
| 337 | *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); |
| 338 | |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 339 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 340 | DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); |
| 341 | unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; |
| 342 | unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; |
| 343 | unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; |
| 344 | unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 345 | |
| 346 | // First, compute final stack size. |
| 347 | uint64_t StackSize = MFI->getStackSize(); |
| 348 | |
| 349 | // No need to allocate space on the stack. |
| 350 | if (StackSize == 0 && !MFI->adjustsStack()) return; |
| 351 | |
| 352 | MachineModuleInfo &MMI = MF.getMMI(); |
Bill Wendling | bc07a89 | 2013-06-18 07:20:20 +0000 | [diff] [blame] | 353 | const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 354 | MachineLocation DstML, SrcML; |
| 355 | |
| 356 | // Adjust stack. |
Akira Hatanaka | 88d76cf | 2012-07-31 23:52:55 +0000 | [diff] [blame] | 357 | TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 358 | |
| 359 | // emit ".cfi_def_cfa_offset StackSize" |
Rafael Espindola | b1f25f1 | 2014-03-07 06:08:31 +0000 | [diff] [blame] | 360 | unsigned CFIIndex = MMI.addFrameInst( |
| 361 | MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize)); |
| 362 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
| 363 | .addCFIIndex(CFIIndex); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 364 | |
| 365 | const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); |
| 366 | |
| 367 | if (CSI.size()) { |
| 368 | // Find the instruction past the last instruction that saves a callee-saved |
| 369 | // register to the stack. |
| 370 | for (unsigned i = 0; i < CSI.size(); ++i) |
| 371 | ++MBBI; |
| 372 | |
| 373 | // Iterate over list of callee-saved registers and emit .cfi_offset |
| 374 | // directives. |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 375 | for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), |
| 376 | E = CSI.end(); I != E; ++I) { |
| 377 | int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); |
| 378 | unsigned Reg = I->getReg(); |
| 379 | |
| 380 | // If Reg is a double precision register, emit two cfa_offsets, |
| 381 | // one for each of the paired single precision registers. |
| 382 | if (Mips::AFGR64RegClass.contains(Reg)) { |
Rafael Espindola | b08d2c2 | 2013-05-16 21:02:15 +0000 | [diff] [blame] | 383 | unsigned Reg0 = |
Akira Hatanaka | 14e31a2 | 2013-08-20 22:58:56 +0000 | [diff] [blame] | 384 | MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); |
Rafael Espindola | b08d2c2 | 2013-05-16 21:02:15 +0000 | [diff] [blame] | 385 | unsigned Reg1 = |
Akira Hatanaka | 14e31a2 | 2013-08-20 22:58:56 +0000 | [diff] [blame] | 386 | MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 387 | |
| 388 | if (!STI.isLittle()) |
Rafael Espindola | b08d2c2 | 2013-05-16 21:02:15 +0000 | [diff] [blame] | 389 | std::swap(Reg0, Reg1); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 390 | |
Rafael Espindola | b1f25f1 | 2014-03-07 06:08:31 +0000 | [diff] [blame] | 391 | unsigned CFIIndex = MMI.addFrameInst( |
| 392 | MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); |
| 393 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
| 394 | .addCFIIndex(CFIIndex); |
| 395 | |
| 396 | CFIIndex = MMI.addFrameInst( |
| 397 | MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); |
| 398 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
| 399 | .addCFIIndex(CFIIndex); |
Zoran Jovanovic | f34b454 | 2014-07-10 22:23:30 +0000 | [diff] [blame] | 400 | } else if (Mips::FGR64RegClass.contains(Reg)) { |
| 401 | unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); |
| 402 | unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; |
| 403 | |
| 404 | if (!STI.isLittle()) |
| 405 | std::swap(Reg0, Reg1); |
| 406 | |
| 407 | unsigned CFIIndex = MMI.addFrameInst( |
| 408 | MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); |
| 409 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
| 410 | .addCFIIndex(CFIIndex); |
| 411 | |
| 412 | CFIIndex = MMI.addFrameInst( |
| 413 | MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); |
| 414 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
| 415 | .addCFIIndex(CFIIndex); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 416 | } else { |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 417 | // Reg is either in GPR32 or FGR32. |
Rafael Espindola | b1f25f1 | 2014-03-07 06:08:31 +0000 | [diff] [blame] | 418 | unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( |
| 419 | nullptr, MRI->getDwarfRegNum(Reg, 1), Offset)); |
| 420 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
| 421 | .addCFIIndex(CFIIndex); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 422 | } |
| 423 | } |
| 424 | } |
| 425 | |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 426 | if (MipsFI->callsEhReturn()) { |
| 427 | const TargetRegisterClass *RC = STI.isABI_N64() ? |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 428 | &Mips::GPR64RegClass : &Mips::GPR32RegClass; |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 429 | |
| 430 | // Insert instructions that spill eh data registers. |
| 431 | for (int I = 0; I < 4; ++I) { |
| 432 | if (!MBB.isLiveIn(ehDataReg(I))) |
| 433 | MBB.addLiveIn(ehDataReg(I)); |
| 434 | TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false, |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 435 | MipsFI->getEhDataRegFI(I), RC, &RegInfo); |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 436 | } |
| 437 | |
| 438 | // Emit .cfi_offset directives for eh data registers. |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 439 | for (int I = 0; I < 4; ++I) { |
| 440 | int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I)); |
Bill Wendling | bc07a89 | 2013-06-18 07:20:20 +0000 | [diff] [blame] | 441 | unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true); |
Rafael Espindola | b1f25f1 | 2014-03-07 06:08:31 +0000 | [diff] [blame] | 442 | unsigned CFIIndex = MMI.addFrameInst( |
| 443 | MCCFIInstruction::createOffset(nullptr, Reg, Offset)); |
| 444 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
| 445 | .addCFIIndex(CFIIndex); |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 446 | } |
| 447 | } |
| 448 | |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 449 | // if framepointer enabled, set it to point to the stack pointer. |
| 450 | if (hasFP(MF)) { |
| 451 | // Insert instruction "move $fp, $sp" at this location. |
Eric Christopher | b45b481 | 2014-04-14 22:21:22 +0000 | [diff] [blame] | 452 | BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO) |
| 453 | .setMIFlag(MachineInstr::FrameSetup); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 454 | |
| 455 | // emit ".cfi_def_cfa_register $fp" |
Rafael Espindola | b1f25f1 | 2014-03-07 06:08:31 +0000 | [diff] [blame] | 456 | unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister( |
| 457 | nullptr, MRI->getDwarfRegNum(FP, true))); |
| 458 | BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) |
| 459 | .addCFIIndex(CFIIndex); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 460 | } |
| 461 | } |
| 462 | |
| 463 | void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, |
| 464 | MachineBasicBlock &MBB) const { |
| 465 | MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); |
| 466 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 467 | MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 468 | |
Akira Hatanaka | 88d76cf | 2012-07-31 23:52:55 +0000 | [diff] [blame] | 469 | const MipsSEInstrInfo &TII = |
| 470 | *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 471 | const MipsRegisterInfo &RegInfo = |
| 472 | *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); |
| 473 | |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 474 | DebugLoc dl = MBBI->getDebugLoc(); |
| 475 | unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; |
| 476 | unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; |
| 477 | unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; |
| 478 | unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 479 | |
| 480 | // if framepointer enabled, restore the stack pointer. |
| 481 | if (hasFP(MF)) { |
| 482 | // Find the first instruction that restores a callee-saved register. |
| 483 | MachineBasicBlock::iterator I = MBBI; |
| 484 | |
| 485 | for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) |
| 486 | --I; |
| 487 | |
| 488 | // Insert instruction "move $sp, $fp" at this location. |
| 489 | BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO); |
| 490 | } |
| 491 | |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 492 | if (MipsFI->callsEhReturn()) { |
| 493 | const TargetRegisterClass *RC = STI.isABI_N64() ? |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 494 | &Mips::GPR64RegClass : &Mips::GPR32RegClass; |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 495 | |
| 496 | // Find first instruction that restores a callee-saved register. |
| 497 | MachineBasicBlock::iterator I = MBBI; |
| 498 | for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) |
| 499 | --I; |
| 500 | |
| 501 | // Insert instructions that restore eh data registers. |
| 502 | for (int J = 0; J < 4; ++J) { |
| 503 | TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J), |
Bill Wendling | ead89ef | 2013-06-07 07:04:14 +0000 | [diff] [blame] | 504 | RC, &RegInfo); |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 505 | } |
| 506 | } |
| 507 | |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 508 | // Get the number of bytes from FrameInfo |
| 509 | uint64_t StackSize = MFI->getStackSize(); |
| 510 | |
| 511 | if (!StackSize) |
| 512 | return; |
| 513 | |
| 514 | // Adjust stack. |
Akira Hatanaka | 88d76cf | 2012-07-31 23:52:55 +0000 | [diff] [blame] | 515 | TII.adjustStackPtr(SP, StackSize, MBB, MBBI); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | bool MipsSEFrameLowering:: |
| 519 | spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 520 | MachineBasicBlock::iterator MI, |
| 521 | const std::vector<CalleeSavedInfo> &CSI, |
| 522 | const TargetRegisterInfo *TRI) const { |
| 523 | MachineFunction *MF = MBB.getParent(); |
| 524 | MachineBasicBlock *EntryBlock = MF->begin(); |
| 525 | const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); |
| 526 | |
| 527 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 528 | // Add the callee-saved register as live-in. Do not add if the register is |
| 529 | // RA and return address is taken, because it has already been added in |
| 530 | // method MipsTargetLowering::LowerRETURNADDR. |
| 531 | // It's killed at the spill, unless the register is RA and return address |
| 532 | // is taken. |
| 533 | unsigned Reg = CSI[i].getReg(); |
| 534 | bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) |
| 535 | && MF->getFrameInfo()->isReturnAddressTaken(); |
| 536 | if (!IsRAAndRetAddrIsTaken) |
| 537 | EntryBlock->addLiveIn(Reg); |
| 538 | |
| 539 | // Insert the spill to the stack frame. |
| 540 | bool IsKill = !IsRAAndRetAddrIsTaken; |
| 541 | const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); |
| 542 | TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill, |
| 543 | CSI[i].getFrameIdx(), RC, TRI); |
| 544 | } |
| 545 | |
| 546 | return true; |
| 547 | } |
| 548 | |
| 549 | bool |
| 550 | MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { |
| 551 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 552 | |
| 553 | // Reserve call frame if the size of the maximum call frame fits into 16-bit |
| 554 | // immediate field and there are no variable sized objects on the stack. |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 555 | // Make sure the second register scavenger spill slot can be accessed with one |
| 556 | // instruction. |
| 557 | return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) && |
| 558 | !MFI->hasVarSizedObjects(); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 559 | } |
| 560 | |
Eli Bendersky | 8da8716 | 2013-02-21 20:05:00 +0000 | [diff] [blame] | 561 | // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions |
| 562 | void MipsSEFrameLowering:: |
| 563 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 564 | MachineBasicBlock::iterator I) const { |
| 565 | const MipsSEInstrInfo &TII = |
| 566 | *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); |
| 567 | |
| 568 | if (!hasReservedCallFrame(MF)) { |
| 569 | int64_t Amount = I->getOperand(0).getImm(); |
| 570 | |
| 571 | if (I->getOpcode() == Mips::ADJCALLSTACKDOWN) |
| 572 | Amount = -Amount; |
| 573 | |
| 574 | unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; |
| 575 | TII.adjustStackPtr(SP, Amount, MBB, I); |
| 576 | } |
| 577 | |
| 578 | MBB.erase(I); |
| 579 | } |
| 580 | |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 581 | void MipsSEFrameLowering:: |
| 582 | processFunctionBeforeCalleeSavedScan(MachineFunction &MF, |
| 583 | RegScavenger *RS) const { |
| 584 | MachineRegisterInfo &MRI = MF.getRegInfo(); |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 585 | MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 586 | unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; |
| 587 | |
| 588 | // Mark $fp as used if function has dedicated frame pointer. |
| 589 | if (hasFP(MF)) |
| 590 | MRI.setPhysRegUsed(FP); |
Akira Hatanaka | 5852e3b | 2012-11-03 00:05:43 +0000 | [diff] [blame] | 591 | |
Akira Hatanaka | c0b0206 | 2013-01-30 00:26:49 +0000 | [diff] [blame] | 592 | // Create spill slots for eh data registers if function calls eh_return. |
| 593 | if (MipsFI->callsEhReturn()) |
| 594 | MipsFI->createEhDataRegsFI(); |
| 595 | |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 596 | // Expand pseudo instructions which load, store or copy accumulators. |
| 597 | // Add an emergency spill slot if a pseudo was expanded. |
Akira Hatanaka | ae4a556 | 2013-05-01 23:41:31 +0000 | [diff] [blame] | 598 | if (ExpandPseudo(MF).expand()) { |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 599 | // The spill slot should be half the size of the accumulator. If target is |
| 600 | // mips64, it should be 64-bit, otherwise it should be 32-bt. |
| 601 | const TargetRegisterClass *RC = STI.hasMips64() ? |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 602 | &Mips::GPR64RegClass : &Mips::GPR32RegClass; |
Akira Hatanaka | 3b70145 | 2013-03-30 01:04:11 +0000 | [diff] [blame] | 603 | int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), |
| 604 | RC->getAlignment(), false); |
| 605 | RS->addScavengingFrameIndex(FI); |
| 606 | } |
| 607 | |
Akira Hatanaka | 5852e3b | 2012-11-03 00:05:43 +0000 | [diff] [blame] | 608 | // Set scavenging frame index if necessary. |
| 609 | uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() + |
| 610 | estimateStackSize(MF); |
| 611 | |
| 612 | if (isInt<16>(MaxSPOffset)) |
| 613 | return; |
| 614 | |
| 615 | const TargetRegisterClass *RC = STI.isABI_N64() ? |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 616 | &Mips::GPR64RegClass : &Mips::GPR32RegClass; |
Akira Hatanaka | 5852e3b | 2012-11-03 00:05:43 +0000 | [diff] [blame] | 617 | int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), |
| 618 | RC->getAlignment(), false); |
Hal Finkel | 9e331c2 | 2013-03-22 23:32:27 +0000 | [diff] [blame] | 619 | RS->addScavengingFrameIndex(FI); |
Akira Hatanaka | d1c43ce | 2012-07-31 22:50:19 +0000 | [diff] [blame] | 620 | } |
Akira Hatanaka | fab8929 | 2012-08-02 18:21:47 +0000 | [diff] [blame] | 621 | |
| 622 | const MipsFrameLowering * |
| 623 | llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) { |
| 624 | return new MipsSEFrameLowering(ST); |
| 625 | } |