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gerrit-public.fairphone.software / toolchain / llvm-project / bc041b82d44b51a3b7da79c38e4052e28ff8011c / . / llvm / test / CodeGen / AMDGPU / reorder-stores.ll
blob: d5e10d0be883dc8742cb6aca78f4f6ef93c771fd [file] [log] [blame]
Tom Stellard49f8bfd2015-01-06 18:00:21 +0000[diff] [blame]1; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
Marek Olsak75170772015-01-27 17:27:15 +0000[diff] [blame]2; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]3
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]4; SI-LABEL: {{^}}no_reorder_v2f64_global_load_store:
Matt Arsenault61001bb2015-11-25 19:58:34 +0000[diff] [blame]5; SI: buffer_load_dwordx4
6; SI: buffer_load_dwordx4
7; SI: buffer_store_dwordx4
8; SI: buffer_store_dwordx4
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]9; SI: s_endpgm
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]10define void @no_reorder_v2f64_global_load_store(<2 x double> addrspace(1)* nocapture %x, <2 x double> addrspace(1)* nocapture %y) nounwind {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]11 %tmp1 = load <2 x double>, <2 x double> addrspace(1)* %x, align 16
12 %tmp4 = load <2 x double>, <2 x double> addrspace(1)* %y, align 16
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]13 store <2 x double> %tmp4, <2 x double> addrspace(1)* %x, align 16
14 store <2 x double> %tmp1, <2 x double> addrspace(1)* %y, align 16
15 ret void
16}
17
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]18; SI-LABEL: {{^}}no_reorder_scalarized_v2f64_local_load_store:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]19; SI: ds_read_b64
20; SI: ds_read_b64
21; SI: ds_write_b64
22; SI: ds_write_b64
23; SI: s_endpgm
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]24define void @no_reorder_scalarized_v2f64_local_load_store(<2 x double> addrspace(3)* nocapture %x, <2 x double> addrspace(3)* nocapture %y) nounwind {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]25 %tmp1 = load <2 x double>, <2 x double> addrspace(3)* %x, align 16
26 %tmp4 = load <2 x double>, <2 x double> addrspace(3)* %y, align 16
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]27 store <2 x double> %tmp4, <2 x double> addrspace(3)* %x, align 16
28 store <2 x double> %tmp1, <2 x double> addrspace(3)* %y, align 16
29 ret void
30}
31
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]32; SI-LABEL: {{^}}no_reorder_split_v8i32_global_load_store:
Matt Arsenault4d801cd2015-11-24 12:05:03 +0000[diff] [blame]33; SI: buffer_load_dwordx4
34; SI: buffer_load_dwordx4
35; SI: buffer_load_dwordx4
36; SI: buffer_load_dwordx4
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]37
38
Matt Arsenault4d801cd2015-11-24 12:05:03 +0000[diff] [blame]39; SI: buffer_store_dwordx4
40; SI: buffer_store_dwordx4
41; SI: buffer_store_dwordx4
42; SI: buffer_store_dwordx4
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]43; SI: s_endpgm
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]44define void @no_reorder_split_v8i32_global_load_store(<8 x i32> addrspace(1)* nocapture %x, <8 x i32> addrspace(1)* nocapture %y) nounwind {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]45 %tmp1 = load <8 x i32>, <8 x i32> addrspace(1)* %x, align 32
46 %tmp4 = load <8 x i32>, <8 x i32> addrspace(1)* %y, align 32
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]47 store <8 x i32> %tmp4, <8 x i32> addrspace(1)* %x, align 32
48 store <8 x i32> %tmp1, <8 x i32> addrspace(1)* %y, align 32
49 ret void
50}
51
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]52; SI-LABEL: {{^}}no_reorder_extload_64:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]53; SI: ds_read_b64
54; SI: ds_read_b64
55; SI: ds_write_b64
56; SI-NOT: ds_read
57; SI: ds_write_b64
58; SI: s_endpgm
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]59define void @no_reorder_extload_64(<2 x i32> addrspace(3)* nocapture %x, <2 x i32> addrspace(3)* nocapture %y) nounwind {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]60 %tmp1 = load <2 x i32>, <2 x i32> addrspace(3)* %x, align 8
61 %tmp4 = load <2 x i32>, <2 x i32> addrspace(3)* %y, align 8
Matt Arsenaultd2c9e082014-07-07 18:34:45 +0000[diff] [blame]62 %tmp1ext = zext <2 x i32> %tmp1 to <2 x i64>
63 %tmp4ext = zext <2 x i32> %tmp4 to <2 x i64>
64 %tmp7 = add <2 x i64> %tmp1ext, <i64 1, i64 1>
65 %tmp9 = add <2 x i64> %tmp4ext, <i64 1, i64 1>
66 %trunctmp9 = trunc <2 x i64> %tmp9 to <2 x i32>
67 %trunctmp7 = trunc <2 x i64> %tmp7 to <2 x i32>
68 store <2 x i32> %trunctmp9, <2 x i32> addrspace(3)* %x, align 8
69 store <2 x i32> %trunctmp7, <2 x i32> addrspace(3)* %y, align 8
70 ret void
71}