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gerrit-public.fairphone.software / toolchain / llvm-project / be8c453d58a77909b1e35410a8ea6e78f5d0e50c / . / llvm / lib / Target / Hexagon / Disassembler / HexagonDisassembler.cpp
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NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]1//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]10#include "Hexagon.h"
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]11#include "MCTargetDesc/HexagonBaseInfo.h"
Colin LeMahieu1174fea2015-02-19 21:10:50 +0000[diff] [blame]12#include "MCTargetDesc/HexagonMCInstrInfo.h"
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]13#include "MCTargetDesc/HexagonMCTargetDesc.h"
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]14
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDisassembler.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCFixedLenDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrDesc.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/Support/Debug.h"
Chandler Carruthd9903882015-01-14 11:23:27 +0000[diff] [blame]23#include "llvm/Support/Endian.h"
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/LEB128.h"
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Chandler Carruthd9903882015-01-14 11:23:27 +0000[diff] [blame]27#include "llvm/Support/raw_ostream.h"
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]28#include <array>
Chandler Carruthd9903882015-01-14 11:23:27 +0000[diff] [blame]29#include <vector>
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]30
31using namespace llvm;
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]32using namespace Hexagon;
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]33
34#define DEBUG_TYPE "hexagon-disassembler"
35
36// Pull DecodeStatus and its enum values into the global namespace.
37typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
38
39namespace {
40/// \brief Hexagon disassembler for all Hexagon platforms.
41class HexagonDisassembler : public MCDisassembler {
42public:
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]43 std::unique_ptr<MCInst *> CurrentBundle;
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]44 HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]45 : MCDisassembler(STI, Ctx), CurrentBundle(new MCInst *) {}
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]46
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]47 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
48 ArrayRef<uint8_t> Bytes, uint64_t Address,
49 raw_ostream &VStream, raw_ostream &CStream,
50 bool &Complete) const;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]51 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]52 ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]53 raw_ostream &VStream,
54 raw_ostream &CStream) const override;
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]55};
56}
57
Colin LeMahieuff370ed2014-12-26 20:30:58 +0000[diff] [blame]58static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]59 uint64_t Address,
60 const void *Decoder);
Colin LeMahieuf3db8842014-12-19 19:06:32 +0000[diff] [blame]61static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]62 uint64_t Address,
63 const void *Decoder);
Colin LeMahieu404d5b22015-02-10 16:59:36 +0000[diff] [blame]64static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]65 uint64_t Address,
66 void const *Decoder);
67
68static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
69 raw_ostream &os);
70static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst);
Colin LeMahieuf3db8842014-12-19 19:06:32 +0000[diff] [blame]71
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]72static const uint16_t IntRegDecoderTable[] = {
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]73 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
74 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
75 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
76 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
77 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
78 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
79 Hexagon::R30, Hexagon::R31};
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]80
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]81static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
82 Hexagon::P2, Hexagon::P3};
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]83
Colin LeMahieu383c36e2014-12-05 18:24:06 +0000[diff] [blame]84static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]85 const uint16_t Table[], size_t Size) {
Colin LeMahieu383c36e2014-12-05 18:24:06 +0000[diff] [blame]86 if (RegNo < Size) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]87 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
Colin LeMahieu383c36e2014-12-05 18:24:06 +0000[diff] [blame]88 return MCDisassembler::Success;
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]89 } else
Colin LeMahieu383c36e2014-12-05 18:24:06 +0000[diff] [blame]90 return MCDisassembler::Fail;
91}
92
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]93static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]94 uint64_t /*Address*/,
95 void const *Decoder) {
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]96 if (RegNo > 31)
97 return MCDisassembler::Fail;
98
99 unsigned Register = IntRegDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]100 Inst.addOperand(MCOperand::createReg(Register));
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]101 return MCDisassembler::Success;
102}
103
Colin LeMahieuf3db8842014-12-19 19:06:32 +0000[diff] [blame]104static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]105 uint64_t /*Address*/,
106 const void *Decoder) {
Colin LeMahieuf3db8842014-12-19 19:06:32 +0000[diff] [blame]107 static const uint16_t CtrlRegDecoderTable[] = {
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]108 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
109 Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,
110 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
111 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH};
Colin LeMahieuf3db8842014-12-19 19:06:32 +0000[diff] [blame]112
113 if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))
114 return MCDisassembler::Fail;
115
116 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
117 return MCDisassembler::Fail;
118
119 unsigned Register = CtrlRegDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]120 Inst.addOperand(MCOperand::createReg(Register));
Colin LeMahieuf3db8842014-12-19 19:06:32 +0000[diff] [blame]121 return MCDisassembler::Success;
122}
123
Colin LeMahieu404d5b22015-02-10 16:59:36 +0000[diff] [blame]124static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]125 uint64_t /*Address*/,
126 void const *Decoder) {
Colin LeMahieu404d5b22015-02-10 16:59:36 +0000[diff] [blame]127 static const uint16_t CtrlReg64DecoderTable[] = {
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]128 Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2,
129 Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister,
130 Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8,
131 Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister,
132 Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC,
133 Hexagon::NoRegister};
Colin LeMahieu404d5b22015-02-10 16:59:36 +0000[diff] [blame]134
135 if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))
136 return MCDisassembler::Fail;
137
138 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
139 return MCDisassembler::Fail;
140
141 unsigned Register = CtrlReg64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]142 Inst.addOperand(MCOperand::createReg(Register));
Colin LeMahieu404d5b22015-02-10 16:59:36 +0000[diff] [blame]143 return MCDisassembler::Success;
144}
145
Colin LeMahieuff370ed2014-12-26 20:30:58 +0000[diff] [blame]146static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]147 uint64_t /*Address*/,
148 const void *Decoder) {
Colin LeMahieuff370ed2014-12-26 20:30:58 +0000[diff] [blame]149 unsigned Register = 0;
150 switch (RegNo) {
151 case 0:
152 Register = Hexagon::M0;
153 break;
154 case 1:
155 Register = Hexagon::M1;
156 break;
157 default:
158 return MCDisassembler::Fail;
159 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]160 Inst.addOperand(MCOperand::createReg(Register));
Colin LeMahieuff370ed2014-12-26 20:30:58 +0000[diff] [blame]161 return MCDisassembler::Success;
162}
163
Colin LeMahieu383c36e2014-12-05 18:24:06 +0000[diff] [blame]164static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]165 uint64_t /*Address*/,
166 const void *Decoder) {
Colin LeMahieu383c36e2014-12-05 18:24:06 +0000[diff] [blame]167 static const uint16_t DoubleRegDecoderTable[] = {
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]168 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
169 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
170 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
171 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
Colin LeMahieu383c36e2014-12-05 18:24:06 +0000[diff] [blame]172
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]173 return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable,
174 sizeof(DoubleRegDecoderTable)));
Colin LeMahieu383c36e2014-12-05 18:24:06 +0000[diff] [blame]175}
176
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]177static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]178 uint64_t /*Address*/,
179 void const *Decoder) {
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]180 if (RegNo > 3)
181 return MCDisassembler::Fail;
182
183 unsigned Register = PredRegDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]184 Inst.addOperand(MCOperand::createReg(Register));
Colin LeMahieuefa74e02014-11-18 20:28:11 +0000[diff] [blame]185 return MCDisassembler::Success;
186}
187
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]188#include "HexagonGenDisassemblerTables.inc"
189
190static MCDisassembler *createHexagonDisassembler(Target const &T,
191 MCSubtargetInfo const &STI,
192 MCContext &Ctx) {
193 return new HexagonDisassembler(STI, Ctx);
194}
195
196extern "C" void LLVMInitializeHexagonDisassembler() {
197 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
198 createHexagonDisassembler);
199}
200
201DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]202 ArrayRef<uint8_t> Bytes,
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]203 uint64_t Address,
204 raw_ostream &os,
205 raw_ostream &cs) const {
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]206 DecodeStatus Result = DecodeStatus::Success;
207 bool Complete = false;
208 Size = 0;
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]209
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]210 *CurrentBundle = &MI;
211 MI.setOpcode(Hexagon::BUNDLE);
212 MI.addOperand(MCOperand::createImm(0));
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]213 while (Result == Success && Complete == false) {
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]214 if (Bytes.size() < HEXAGON_INSTR_SIZE)
215 return MCDisassembler::Fail;
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]216 MCInst *Inst = new (getContext()) MCInst;
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]217 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
218 MI.addOperand(MCOperand::createInst(Inst));
219 Size += HEXAGON_INSTR_SIZE;
220 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
221 }
222 return Result;
223}
224
225DecodeStatus HexagonDisassembler::getSingleInstruction(
226 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
227 raw_ostream &os, raw_ostream &cs, bool &Complete) const {
228 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
229
230 uint32_t Instruction =
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]231 llvm::support::endian::read<uint32_t, llvm::support::little,
232 llvm::support::unaligned>(Bytes.data());
233
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]234 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
235 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
236 HexagonII::INST_PARSE_LOOP_END) {
237 if (BundleSize == 0)
238 HexagonMCInstrInfo::setInnerLoop(MCB);
239 else if (BundleSize == 1)
240 HexagonMCInstrInfo::setOuterLoop(MCB);
241 else
242 return DecodeStatus::Fail;
243 }
244
245 DecodeStatus Result = DecodeStatus::Success;
246 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]247 HexagonII::INST_PARSE_DUPLEX) {
248 // Determine the instruction class of each instruction in the duplex.
249 unsigned duplexIClass, IClassLow, IClassHigh;
250
251 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
252 switch (duplexIClass) {
253 default:
254 return MCDisassembler::Fail;
255 case 0:
256 IClassLow = HexagonII::HSIG_L1;
257 IClassHigh = HexagonII::HSIG_L1;
258 break;
259 case 1:
260 IClassLow = HexagonII::HSIG_L2;
261 IClassHigh = HexagonII::HSIG_L1;
262 break;
263 case 2:
264 IClassLow = HexagonII::HSIG_L2;
265 IClassHigh = HexagonII::HSIG_L2;
266 break;
267 case 3:
268 IClassLow = HexagonII::HSIG_A;
269 IClassHigh = HexagonII::HSIG_A;
270 break;
271 case 4:
272 IClassLow = HexagonII::HSIG_L1;
273 IClassHigh = HexagonII::HSIG_A;
274 break;
275 case 5:
276 IClassLow = HexagonII::HSIG_L2;
277 IClassHigh = HexagonII::HSIG_A;
278 break;
279 case 6:
280 IClassLow = HexagonII::HSIG_S1;
281 IClassHigh = HexagonII::HSIG_A;
282 break;
283 case 7:
284 IClassLow = HexagonII::HSIG_S2;
285 IClassHigh = HexagonII::HSIG_A;
286 break;
287 case 8:
288 IClassLow = HexagonII::HSIG_S1;
289 IClassHigh = HexagonII::HSIG_L1;
290 break;
291 case 9:
292 IClassLow = HexagonII::HSIG_S1;
293 IClassHigh = HexagonII::HSIG_L2;
294 break;
295 case 10:
296 IClassLow = HexagonII::HSIG_S1;
297 IClassHigh = HexagonII::HSIG_S1;
298 break;
299 case 11:
300 IClassLow = HexagonII::HSIG_S2;
301 IClassHigh = HexagonII::HSIG_S1;
302 break;
303 case 12:
304 IClassLow = HexagonII::HSIG_S2;
305 IClassHigh = HexagonII::HSIG_L1;
306 break;
307 case 13:
308 IClassLow = HexagonII::HSIG_S2;
309 IClassHigh = HexagonII::HSIG_L2;
310 break;
311 case 14:
312 IClassLow = HexagonII::HSIG_S2;
313 IClassHigh = HexagonII::HSIG_S2;
314 break;
315 }
316
317 // Set the MCInst to be a duplex instruction. Which one doesn't matter.
318 MI.setOpcode(Hexagon::DuplexIClass0);
319
320 // Decode each instruction in the duplex.
321 // Create an MCInst for each instruction.
322 unsigned instLow = Instruction & 0x1fff;
323 unsigned instHigh = (Instruction >> 16) & 0x1fff;
324 unsigned opLow;
325 if (GetSubinstOpcode(IClassLow, instLow, opLow, os) !=
326 MCDisassembler::Success)
327 return MCDisassembler::Fail;
328 unsigned opHigh;
329 if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) !=
330 MCDisassembler::Success)
331 return MCDisassembler::Fail;
332 MCInst *MILow = new (getContext()) MCInst;
333 MILow->setOpcode(opLow);
334 MCInst *MIHigh = new (getContext()) MCInst;
335 MIHigh->setOpcode(opHigh);
336 AddSubinstOperands(MILow, opLow, instLow);
337 AddSubinstOperands(MIHigh, opHigh, instHigh);
338 // see ConvertToSubInst() in
339 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
340
341 // Add the duplex instruction MCInsts as operands to the passed in MCInst.
342 MCOperand OPLow = MCOperand::createInst(MILow);
343 MCOperand OPHigh = MCOperand::createInst(MIHigh);
344 MI.addOperand(OPLow);
345 MI.addOperand(OPHigh);
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]346 Complete = true;
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]347 } else {
348 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
349 HexagonII::INST_PARSE_PACKET_END)
350 Complete = true;
351 // Calling the auto-generated decoder function.
352 Result =
353 decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);
354 }
Colin LeMahieu68d967d2015-05-29 14:44:13 +0000[diff] [blame]355
Colin LeMahieu5d6f03b2014-12-04 03:41:21 +0000[diff] [blame]356 return Result;
NAKAMURA Takumi729be142014-10-27 12:37:26 +0000[diff] [blame]357}
Colin LeMahieube8c4532015-06-05 16:00:11 +0000[diff] [blame^]358
359// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
360enum subInstBinaryValues {
361 V4_SA1_addi_BITS = 0x0000,
362 V4_SA1_addi_MASK = 0x1800,
363 V4_SA1_addrx_BITS = 0x1800,
364 V4_SA1_addrx_MASK = 0x1f00,
365 V4_SA1_addsp_BITS = 0x0c00,
366 V4_SA1_addsp_MASK = 0x1c00,
367 V4_SA1_and1_BITS = 0x1200,
368 V4_SA1_and1_MASK = 0x1f00,
369 V4_SA1_clrf_BITS = 0x1a70,
370 V4_SA1_clrf_MASK = 0x1e70,
371 V4_SA1_clrfnew_BITS = 0x1a50,
372 V4_SA1_clrfnew_MASK = 0x1e70,
373 V4_SA1_clrt_BITS = 0x1a60,
374 V4_SA1_clrt_MASK = 0x1e70,
375 V4_SA1_clrtnew_BITS = 0x1a40,
376 V4_SA1_clrtnew_MASK = 0x1e70,
377 V4_SA1_cmpeqi_BITS = 0x1900,
378 V4_SA1_cmpeqi_MASK = 0x1f00,
379 V4_SA1_combine0i_BITS = 0x1c00,
380 V4_SA1_combine0i_MASK = 0x1d18,
381 V4_SA1_combine1i_BITS = 0x1c08,
382 V4_SA1_combine1i_MASK = 0x1d18,
383 V4_SA1_combine2i_BITS = 0x1c10,
384 V4_SA1_combine2i_MASK = 0x1d18,
385 V4_SA1_combine3i_BITS = 0x1c18,
386 V4_SA1_combine3i_MASK = 0x1d18,
387 V4_SA1_combinerz_BITS = 0x1d08,
388 V4_SA1_combinerz_MASK = 0x1d08,
389 V4_SA1_combinezr_BITS = 0x1d00,
390 V4_SA1_combinezr_MASK = 0x1d08,
391 V4_SA1_dec_BITS = 0x1300,
392 V4_SA1_dec_MASK = 0x1f00,
393 V4_SA1_inc_BITS = 0x1100,
394 V4_SA1_inc_MASK = 0x1f00,
395 V4_SA1_seti_BITS = 0x0800,
396 V4_SA1_seti_MASK = 0x1c00,
397 V4_SA1_setin1_BITS = 0x1a00,
398 V4_SA1_setin1_MASK = 0x1e40,
399 V4_SA1_sxtb_BITS = 0x1500,
400 V4_SA1_sxtb_MASK = 0x1f00,
401 V4_SA1_sxth_BITS = 0x1400,
402 V4_SA1_sxth_MASK = 0x1f00,
403 V4_SA1_tfr_BITS = 0x1000,
404 V4_SA1_tfr_MASK = 0x1f00,
405 V4_SA1_zxtb_BITS = 0x1700,
406 V4_SA1_zxtb_MASK = 0x1f00,
407 V4_SA1_zxth_BITS = 0x1600,
408 V4_SA1_zxth_MASK = 0x1f00,
409 V4_SL1_loadri_io_BITS = 0x0000,
410 V4_SL1_loadri_io_MASK = 0x1000,
411 V4_SL1_loadrub_io_BITS = 0x1000,
412 V4_SL1_loadrub_io_MASK = 0x1000,
413 V4_SL2_deallocframe_BITS = 0x1f00,
414 V4_SL2_deallocframe_MASK = 0x1fc0,
415 V4_SL2_jumpr31_BITS = 0x1fc0,
416 V4_SL2_jumpr31_MASK = 0x1fc4,
417 V4_SL2_jumpr31_f_BITS = 0x1fc5,
418 V4_SL2_jumpr31_f_MASK = 0x1fc7,
419 V4_SL2_jumpr31_fnew_BITS = 0x1fc7,
420 V4_SL2_jumpr31_fnew_MASK = 0x1fc7,
421 V4_SL2_jumpr31_t_BITS = 0x1fc4,
422 V4_SL2_jumpr31_t_MASK = 0x1fc7,
423 V4_SL2_jumpr31_tnew_BITS = 0x1fc6,
424 V4_SL2_jumpr31_tnew_MASK = 0x1fc7,
425 V4_SL2_loadrb_io_BITS = 0x1000,
426 V4_SL2_loadrb_io_MASK = 0x1800,
427 V4_SL2_loadrd_sp_BITS = 0x1e00,
428 V4_SL2_loadrd_sp_MASK = 0x1f00,
429 V4_SL2_loadrh_io_BITS = 0x0000,
430 V4_SL2_loadrh_io_MASK = 0x1800,
431 V4_SL2_loadri_sp_BITS = 0x1c00,
432 V4_SL2_loadri_sp_MASK = 0x1e00,
433 V4_SL2_loadruh_io_BITS = 0x0800,
434 V4_SL2_loadruh_io_MASK = 0x1800,
435 V4_SL2_return_BITS = 0x1f40,
436 V4_SL2_return_MASK = 0x1fc4,
437 V4_SL2_return_f_BITS = 0x1f45,
438 V4_SL2_return_f_MASK = 0x1fc7,
439 V4_SL2_return_fnew_BITS = 0x1f47,
440 V4_SL2_return_fnew_MASK = 0x1fc7,
441 V4_SL2_return_t_BITS = 0x1f44,
442 V4_SL2_return_t_MASK = 0x1fc7,
443 V4_SL2_return_tnew_BITS = 0x1f46,
444 V4_SL2_return_tnew_MASK = 0x1fc7,
445 V4_SS1_storeb_io_BITS = 0x1000,
446 V4_SS1_storeb_io_MASK = 0x1000,
447 V4_SS1_storew_io_BITS = 0x0000,
448 V4_SS1_storew_io_MASK = 0x1000,
449 V4_SS2_allocframe_BITS = 0x1c00,
450 V4_SS2_allocframe_MASK = 0x1e00,
451 V4_SS2_storebi0_BITS = 0x1200,
452 V4_SS2_storebi0_MASK = 0x1f00,
453 V4_SS2_storebi1_BITS = 0x1300,
454 V4_SS2_storebi1_MASK = 0x1f00,
455 V4_SS2_stored_sp_BITS = 0x0a00,
456 V4_SS2_stored_sp_MASK = 0x1e00,
457 V4_SS2_storeh_io_BITS = 0x0000,
458 V4_SS2_storeh_io_MASK = 0x1800,
459 V4_SS2_storew_sp_BITS = 0x0800,
460 V4_SS2_storew_sp_MASK = 0x1e00,
461 V4_SS2_storewi0_BITS = 0x1000,
462 V4_SS2_storewi0_MASK = 0x1f00,
463 V4_SS2_storewi1_BITS = 0x1100,
464 V4_SS2_storewi1_MASK = 0x1f00
465};
466
467static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
468 raw_ostream &os) {
469 switch (IClass) {
470 case HexagonII::HSIG_L1:
471 if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS)
472 op = Hexagon::V4_SL1_loadri_io;
473 else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS)
474 op = Hexagon::V4_SL1_loadrub_io;
475 else {
476 os << "<unknown subinstruction>";
477 return MCDisassembler::Fail;
478 }
479 break;
480 case HexagonII::HSIG_L2:
481 if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS)
482 op = Hexagon::V4_SL2_deallocframe;
483 else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS)
484 op = Hexagon::V4_SL2_jumpr31;
485 else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS)
486 op = Hexagon::V4_SL2_jumpr31_f;
487 else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS)
488 op = Hexagon::V4_SL2_jumpr31_fnew;
489 else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS)
490 op = Hexagon::V4_SL2_jumpr31_t;
491 else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS)
492 op = Hexagon::V4_SL2_jumpr31_tnew;
493 else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS)
494 op = Hexagon::V4_SL2_loadrb_io;
495 else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS)
496 op = Hexagon::V4_SL2_loadrd_sp;
497 else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS)
498 op = Hexagon::V4_SL2_loadrh_io;
499 else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS)
500 op = Hexagon::V4_SL2_loadri_sp;
501 else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS)
502 op = Hexagon::V4_SL2_loadruh_io;
503 else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS)
504 op = Hexagon::V4_SL2_return;
505 else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS)
506 op = Hexagon::V4_SL2_return_f;
507 else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS)
508 op = Hexagon::V4_SL2_return_fnew;
509 else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS)
510 op = Hexagon::V4_SL2_return_t;
511 else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS)
512 op = Hexagon::V4_SL2_return_tnew;
513 else {
514 os << "<unknown subinstruction>";
515 return MCDisassembler::Fail;
516 }
517 break;
518 case HexagonII::HSIG_A:
519 if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS)
520 op = Hexagon::V4_SA1_addi;
521 else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS)
522 op = Hexagon::V4_SA1_addrx;
523 else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS)
524 op = Hexagon::V4_SA1_addsp;
525 else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS)
526 op = Hexagon::V4_SA1_and1;
527 else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS)
528 op = Hexagon::V4_SA1_clrf;
529 else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS)
530 op = Hexagon::V4_SA1_clrfnew;
531 else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS)
532 op = Hexagon::V4_SA1_clrt;
533 else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS)
534 op = Hexagon::V4_SA1_clrtnew;
535 else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS)
536 op = Hexagon::V4_SA1_cmpeqi;
537 else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS)
538 op = Hexagon::V4_SA1_combine0i;
539 else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS)
540 op = Hexagon::V4_SA1_combine1i;
541 else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS)
542 op = Hexagon::V4_SA1_combine2i;
543 else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS)
544 op = Hexagon::V4_SA1_combine3i;
545 else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS)
546 op = Hexagon::V4_SA1_combinerz;
547 else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS)
548 op = Hexagon::V4_SA1_combinezr;
549 else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS)
550 op = Hexagon::V4_SA1_dec;
551 else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS)
552 op = Hexagon::V4_SA1_inc;
553 else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS)
554 op = Hexagon::V4_SA1_seti;
555 else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS)
556 op = Hexagon::V4_SA1_setin1;
557 else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS)
558 op = Hexagon::V4_SA1_sxtb;
559 else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS)
560 op = Hexagon::V4_SA1_sxth;
561 else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS)
562 op = Hexagon::V4_SA1_tfr;
563 else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS)
564 op = Hexagon::V4_SA1_zxtb;
565 else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS)
566 op = Hexagon::V4_SA1_zxth;
567 else {
568 os << "<unknown subinstruction>";
569 return MCDisassembler::Fail;
570 }
571 break;
572 case HexagonII::HSIG_S1:
573 if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS)
574 op = Hexagon::V4_SS1_storeb_io;
575 else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS)
576 op = Hexagon::V4_SS1_storew_io;
577 else {
578 os << "<unknown subinstruction>";
579 return MCDisassembler::Fail;
580 }
581 break;
582 case HexagonII::HSIG_S2:
583 if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS)
584 op = Hexagon::V4_SS2_allocframe;
585 else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS)
586 op = Hexagon::V4_SS2_storebi0;
587 else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS)
588 op = Hexagon::V4_SS2_storebi1;
589 else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS)
590 op = Hexagon::V4_SS2_stored_sp;
591 else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS)
592 op = Hexagon::V4_SS2_storeh_io;
593 else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS)
594 op = Hexagon::V4_SS2_storew_sp;
595 else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS)
596 op = Hexagon::V4_SS2_storewi0;
597 else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS)
598 op = Hexagon::V4_SS2_storewi1;
599 else {
600 os << "<unknown subinstruction>";
601 return MCDisassembler::Fail;
602 }
603 break;
604 default:
605 os << "<unknown>";
606 return MCDisassembler::Fail;
607 }
608 return MCDisassembler::Success;
609}
610
611static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) {
612 if (encoded_reg < 8)
613 return Hexagon::R0 + encoded_reg;
614 else if (encoded_reg < 16)
615 return Hexagon::R0 + encoded_reg + 8;
616 return Hexagon::NoRegister;
617}
618
619static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) {
620 if (encoded_dreg < 4)
621 return Hexagon::D0 + encoded_dreg;
622 else if (encoded_dreg < 8)
623 return Hexagon::D0 + encoded_dreg + 4;
624 return Hexagon::NoRegister;
625}
626
627static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) {
628 int64_t operand;
629 MCOperand Op;
630 switch (opcode) {
631 case Hexagon::V4_SL2_deallocframe:
632 case Hexagon::V4_SL2_jumpr31:
633 case Hexagon::V4_SL2_jumpr31_f:
634 case Hexagon::V4_SL2_jumpr31_fnew:
635 case Hexagon::V4_SL2_jumpr31_t:
636 case Hexagon::V4_SL2_jumpr31_tnew:
637 case Hexagon::V4_SL2_return:
638 case Hexagon::V4_SL2_return_f:
639 case Hexagon::V4_SL2_return_fnew:
640 case Hexagon::V4_SL2_return_t:
641 case Hexagon::V4_SL2_return_tnew:
642 // no operands for these instructions
643 break;
644 case Hexagon::V4_SS2_allocframe:
645 // u 8-4{5_3}
646 operand = ((inst & 0x1f0) >> 4) << 3;
647 Op = MCOperand::createImm(operand);
648 MI->addOperand(Op);
649 break;
650 case Hexagon::V4_SL1_loadri_io:
651 // Rd 3-0, Rs 7-4, u 11-8{4_2}
652 operand = getRegFromSubinstEncoding(inst & 0xf);
653 Op = MCOperand::createReg(operand);
654 MI->addOperand(Op);
655 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
656 Op = MCOperand::createReg(operand);
657 MI->addOperand(Op);
658 operand = (inst & 0xf00) >> 6;
659 Op = MCOperand::createImm(operand);
660 MI->addOperand(Op);
661 break;
662 case Hexagon::V4_SL1_loadrub_io:
663 // Rd 3-0, Rs 7-4, u 11-8
664 operand = getRegFromSubinstEncoding(inst & 0xf);
665 Op = MCOperand::createReg(operand);
666 MI->addOperand(Op);
667 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
668 Op = MCOperand::createReg(operand);
669 MI->addOperand(Op);
670 operand = (inst & 0xf00) >> 8;
671 Op = MCOperand::createImm(operand);
672 MI->addOperand(Op);
673 break;
674 case Hexagon::V4_SL2_loadrb_io:
675 // Rd 3-0, Rs 7-4, u 10-8
676 operand = getRegFromSubinstEncoding(inst & 0xf);
677 Op = MCOperand::createReg(operand);
678 MI->addOperand(Op);
679 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
680 Op = MCOperand::createReg(operand);
681 MI->addOperand(Op);
682 operand = (inst & 0x700) >> 8;
683 Op = MCOperand::createImm(operand);
684 MI->addOperand(Op);
685 break;
686 case Hexagon::V4_SL2_loadrh_io:
687 case Hexagon::V4_SL2_loadruh_io:
688 // Rd 3-0, Rs 7-4, u 10-8{3_1}
689 operand = getRegFromSubinstEncoding(inst & 0xf);
690 Op = MCOperand::createReg(operand);
691 MI->addOperand(Op);
692 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
693 Op = MCOperand::createReg(operand);
694 MI->addOperand(Op);
695 operand = ((inst & 0x700) >> 8) << 1;
696 Op = MCOperand::createImm(operand);
697 MI->addOperand(Op);
698 break;
699 case Hexagon::V4_SL2_loadrd_sp:
700 // Rdd 2-0, u 7-3{5_3}
701 operand = getDRegFromSubinstEncoding(inst & 0x7);
702 Op = MCOperand::createReg(operand);
703 MI->addOperand(Op);
704 operand = ((inst & 0x0f8) >> 3) << 3;
705 Op = MCOperand::createImm(operand);
706 MI->addOperand(Op);
707 break;
708 case Hexagon::V4_SL2_loadri_sp:
709 // Rd 3-0, u 8-4{5_2}
710 operand = getRegFromSubinstEncoding(inst & 0xf);
711 Op = MCOperand::createReg(operand);
712 MI->addOperand(Op);
713 operand = ((inst & 0x1f0) >> 4) << 2;
714 Op = MCOperand::createImm(operand);
715 MI->addOperand(Op);
716 break;
717 case Hexagon::V4_SA1_addi:
718 // Rx 3-0 (x2), s7 10-4
719 operand = getRegFromSubinstEncoding(inst & 0xf);
720 Op = MCOperand::createReg(operand);
721 MI->addOperand(Op);
722 MI->addOperand(Op);
723 operand = SignExtend64<7>((inst & 0x7f0) >> 4);
724 Op = MCOperand::createImm(operand);
725 MI->addOperand(Op);
726 break;
727 case Hexagon::V4_SA1_addrx:
728 // Rx 3-0 (x2), Rs 7-4
729 operand = getRegFromSubinstEncoding(inst & 0xf);
730 Op = MCOperand::createReg(operand);
731 MI->addOperand(Op);
732 MI->addOperand(Op);
733 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
734 Op = MCOperand::createReg(operand);
735 MI->addOperand(Op);
736 case Hexagon::V4_SA1_and1:
737 case Hexagon::V4_SA1_dec:
738 case Hexagon::V4_SA1_inc:
739 case Hexagon::V4_SA1_sxtb:
740 case Hexagon::V4_SA1_sxth:
741 case Hexagon::V4_SA1_tfr:
742 case Hexagon::V4_SA1_zxtb:
743 case Hexagon::V4_SA1_zxth:
744 // Rd 3-0, Rs 7-4
745 operand = getRegFromSubinstEncoding(inst & 0xf);
746 Op = MCOperand::createReg(operand);
747 MI->addOperand(Op);
748 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
749 Op = MCOperand::createReg(operand);
750 MI->addOperand(Op);
751 break;
752 case Hexagon::V4_SA1_addsp:
753 // Rd 3-0, u 9-4{6_2}
754 operand = getRegFromSubinstEncoding(inst & 0xf);
755 Op = MCOperand::createReg(operand);
756 MI->addOperand(Op);
757 operand = ((inst & 0x3f0) >> 4) << 2;
758 Op = MCOperand::createImm(operand);
759 MI->addOperand(Op);
760 break;
761 case Hexagon::V4_SA1_seti:
762 // Rd 3-0, u 9-4
763 operand = getRegFromSubinstEncoding(inst & 0xf);
764 Op = MCOperand::createReg(operand);
765 MI->addOperand(Op);
766 operand = (inst & 0x3f0) >> 4;
767 Op = MCOperand::createImm(operand);
768 MI->addOperand(Op);
769 break;
770 case Hexagon::V4_SA1_clrf:
771 case Hexagon::V4_SA1_clrfnew:
772 case Hexagon::V4_SA1_clrt:
773 case Hexagon::V4_SA1_clrtnew:
774 case Hexagon::V4_SA1_setin1:
775 // Rd 3-0
776 operand = getRegFromSubinstEncoding(inst & 0xf);
777 Op = MCOperand::createReg(operand);
778 MI->addOperand(Op);
779 break;
780 case Hexagon::V4_SA1_cmpeqi:
781 // Rs 7-4, u 1-0
782 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
783 Op = MCOperand::createReg(operand);
784 MI->addOperand(Op);
785 operand = inst & 0x3;
786 Op = MCOperand::createImm(operand);
787 MI->addOperand(Op);
788 break;
789 case Hexagon::V4_SA1_combine0i:
790 case Hexagon::V4_SA1_combine1i:
791 case Hexagon::V4_SA1_combine2i:
792 case Hexagon::V4_SA1_combine3i:
793 // Rdd 2-0, u 6-5
794 operand = getDRegFromSubinstEncoding(inst & 0x7);
795 Op = MCOperand::createReg(operand);
796 MI->addOperand(Op);
797 operand = (inst & 0x060) >> 5;
798 Op = MCOperand::createImm(operand);
799 MI->addOperand(Op);
800 break;
801 case Hexagon::V4_SA1_combinerz:
802 case Hexagon::V4_SA1_combinezr:
803 // Rdd 2-0, Rs 7-4
804 operand = getDRegFromSubinstEncoding(inst & 0x7);
805 Op = MCOperand::createReg(operand);
806 MI->addOperand(Op);
807 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
808 Op = MCOperand::createReg(operand);
809 MI->addOperand(Op);
810 break;
811 case Hexagon::V4_SS1_storeb_io:
812 // Rs 7-4, u 11-8, Rt 3-0
813 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
814 Op = MCOperand::createReg(operand);
815 MI->addOperand(Op);
816 operand = (inst & 0xf00) >> 8;
817 Op = MCOperand::createImm(operand);
818 MI->addOperand(Op);
819 operand = getRegFromSubinstEncoding(inst & 0xf);
820 Op = MCOperand::createReg(operand);
821 MI->addOperand(Op);
822 break;
823 case Hexagon::V4_SS1_storew_io:
824 // Rs 7-4, u 11-8{4_2}, Rt 3-0
825 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
826 Op = MCOperand::createReg(operand);
827 MI->addOperand(Op);
828 operand = ((inst & 0xf00) >> 8) << 2;
829 Op = MCOperand::createImm(operand);
830 MI->addOperand(Op);
831 operand = getRegFromSubinstEncoding(inst & 0xf);
832 Op = MCOperand::createReg(operand);
833 MI->addOperand(Op);
834 break;
835 case Hexagon::V4_SS2_storebi0:
836 case Hexagon::V4_SS2_storebi1:
837 // Rs 7-4, u 3-0
838 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
839 Op = MCOperand::createReg(operand);
840 MI->addOperand(Op);
841 operand = inst & 0xf;
842 Op = MCOperand::createImm(operand);
843 MI->addOperand(Op);
844 break;
845 case Hexagon::V4_SS2_storewi0:
846 case Hexagon::V4_SS2_storewi1:
847 // Rs 7-4, u 3-0{4_2}
848 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
849 Op = MCOperand::createReg(operand);
850 MI->addOperand(Op);
851 operand = (inst & 0xf) << 2;
852 Op = MCOperand::createImm(operand);
853 MI->addOperand(Op);
854 break;
855 case Hexagon::V4_SS2_stored_sp:
856 // s 8-3{6_3}, Rtt 2-0
857 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
858 Op = MCOperand::createImm(operand);
859 MI->addOperand(Op);
860 operand = getDRegFromSubinstEncoding(inst & 0x7);
861 Op = MCOperand::createReg(operand);
862 MI->addOperand(Op);
863 case Hexagon::V4_SS2_storeh_io:
864 // Rs 7-4, u 10-8{3_1}, Rt 3-0
865 operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
866 Op = MCOperand::createReg(operand);
867 MI->addOperand(Op);
868 operand = ((inst & 0x700) >> 8) << 1;
869 Op = MCOperand::createImm(operand);
870 MI->addOperand(Op);
871 operand = getRegFromSubinstEncoding(inst & 0xf);
872 Op = MCOperand::createReg(operand);
873 MI->addOperand(Op);
874 break;
875 case Hexagon::V4_SS2_storew_sp:
876 // u 8-4{5_2}, Rd 3-0
877 operand = ((inst & 0x1f0) >> 4) << 2;
878 Op = MCOperand::createImm(operand);
879 MI->addOperand(Op);
880 operand = getRegFromSubinstEncoding(inst & 0xf);
881 Op = MCOperand::createReg(operand);
882 MI->addOperand(Op);
883 break;
884 default:
885 // don't crash with an invalid subinstruction
886 // llvm_unreachable("Invalid subinstruction in duplex instruction");
887 break;
888 }
889}