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gerrit-public.fairphone.software / toolchain / llvm-project / bea19a9493b7286a0c79a8be2b788bed8cb4cfa9 / . / llvm / test / CodeGen / PowerPC / atomics-regression.ll
blob: daf55fc426d04c76a0c836075dbf40fcda653424 [file] [log] [blame]
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE
3
4define i8 @test0(i8* %ptr) {
5; PPC64LE-LABEL: test0:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7; PPC64LE-NEXT: lbz 3, 0(3)
8; PPC64LE-NEXT: blr
9 %val = load atomic i8, i8* %ptr unordered, align 1
10 ret i8 %val
11}
12
13define i8 @test1(i8* %ptr) {
14; PPC64LE-LABEL: test1:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]15; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]16; PPC64LE-NEXT: lbz 3, 0(3)
17; PPC64LE-NEXT: blr
18 %val = load atomic i8, i8* %ptr monotonic, align 1
19 ret i8 %val
20}
21
22define i8 @test2(i8* %ptr) {
23; PPC64LE-LABEL: test2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]24; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]25; PPC64LE-NEXT: lbz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]26; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]27; PPC64LE-NEXT: bne- 7, .+4
28; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]29; PPC64LE-NEXT: blr
30 %val = load atomic i8, i8* %ptr acquire, align 1
31 ret i8 %val
32}
33
34define i8 @test3(i8* %ptr) {
35; PPC64LE-LABEL: test3:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]36; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]37; PPC64LE-NEXT: sync
38; PPC64LE-NEXT: ori 2, 2, 0
39; PPC64LE-NEXT: lbz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]40; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]41; PPC64LE-NEXT: bne- 7, .+4
42; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]43; PPC64LE-NEXT: blr
44 %val = load atomic i8, i8* %ptr seq_cst, align 1
45 ret i8 %val
46}
47
48define i16 @test4(i16* %ptr) {
49; PPC64LE-LABEL: test4:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]50; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]51; PPC64LE-NEXT: lhz 3, 0(3)
52; PPC64LE-NEXT: blr
53 %val = load atomic i16, i16* %ptr unordered, align 2
54 ret i16 %val
55}
56
57define i16 @test5(i16* %ptr) {
58; PPC64LE-LABEL: test5:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]59; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]60; PPC64LE-NEXT: lhz 3, 0(3)
61; PPC64LE-NEXT: blr
62 %val = load atomic i16, i16* %ptr monotonic, align 2
63 ret i16 %val
64}
65
66define i16 @test6(i16* %ptr) {
67; PPC64LE-LABEL: test6:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]68; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]69; PPC64LE-NEXT: lhz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]70; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]71; PPC64LE-NEXT: bne- 7, .+4
72; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]73; PPC64LE-NEXT: blr
74 %val = load atomic i16, i16* %ptr acquire, align 2
75 ret i16 %val
76}
77
78define i16 @test7(i16* %ptr) {
79; PPC64LE-LABEL: test7:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]80; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]81; PPC64LE-NEXT: sync
82; PPC64LE-NEXT: ori 2, 2, 0
83; PPC64LE-NEXT: lhz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]84; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]85; PPC64LE-NEXT: bne- 7, .+4
86; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]87; PPC64LE-NEXT: blr
88 %val = load atomic i16, i16* %ptr seq_cst, align 2
89 ret i16 %val
90}
91
92define i32 @test8(i32* %ptr) {
93; PPC64LE-LABEL: test8:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]94; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]95; PPC64LE-NEXT: lwz 3, 0(3)
96; PPC64LE-NEXT: blr
97 %val = load atomic i32, i32* %ptr unordered, align 4
98 ret i32 %val
99}
100
101define i32 @test9(i32* %ptr) {
102; PPC64LE-LABEL: test9:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]103; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]104; PPC64LE-NEXT: lwz 3, 0(3)
105; PPC64LE-NEXT: blr
106 %val = load atomic i32, i32* %ptr monotonic, align 4
107 ret i32 %val
108}
109
110define i32 @test10(i32* %ptr) {
111; PPC64LE-LABEL: test10:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]112; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]113; PPC64LE-NEXT: lwz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]114; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]115; PPC64LE-NEXT: bne- 7, .+4
116; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]117; PPC64LE-NEXT: blr
118 %val = load atomic i32, i32* %ptr acquire, align 4
119 ret i32 %val
120}
121
122define i32 @test11(i32* %ptr) {
123; PPC64LE-LABEL: test11:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]124; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]125; PPC64LE-NEXT: sync
126; PPC64LE-NEXT: ori 2, 2, 0
127; PPC64LE-NEXT: lwz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]128; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]129; PPC64LE-NEXT: bne- 7, .+4
130; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]131; PPC64LE-NEXT: blr
132 %val = load atomic i32, i32* %ptr seq_cst, align 4
133 ret i32 %val
134}
135
136define i64 @test12(i64* %ptr) {
137; PPC64LE-LABEL: test12:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]138; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]139; PPC64LE-NEXT: ld 3, 0(3)
140; PPC64LE-NEXT: blr
141 %val = load atomic i64, i64* %ptr unordered, align 8
142 ret i64 %val
143}
144
145define i64 @test13(i64* %ptr) {
146; PPC64LE-LABEL: test13:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]147; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]148; PPC64LE-NEXT: ld 3, 0(3)
149; PPC64LE-NEXT: blr
150 %val = load atomic i64, i64* %ptr monotonic, align 8
151 ret i64 %val
152}
153
154define i64 @test14(i64* %ptr) {
155; PPC64LE-LABEL: test14:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]156; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]157; PPC64LE-NEXT: ld 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]158; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]159; PPC64LE-NEXT: bne- 7, .+4
160; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]161; PPC64LE-NEXT: blr
162 %val = load atomic i64, i64* %ptr acquire, align 8
163 ret i64 %val
164}
165
166define i64 @test15(i64* %ptr) {
167; PPC64LE-LABEL: test15:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]168; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]169; PPC64LE-NEXT: sync
170; PPC64LE-NEXT: ori 2, 2, 0
171; PPC64LE-NEXT: ld 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]172; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]173; PPC64LE-NEXT: bne- 7, .+4
174; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]175; PPC64LE-NEXT: blr
176 %val = load atomic i64, i64* %ptr seq_cst, align 8
177 ret i64 %val
178}
179
180define void @test16(i8* %ptr, i8 %val) {
181; PPC64LE-LABEL: test16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]182; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]183; PPC64LE-NEXT: stb 4, 0(3)
184; PPC64LE-NEXT: blr
185 store atomic i8 %val, i8* %ptr unordered, align 1
186 ret void
187}
188
189define void @test17(i8* %ptr, i8 %val) {
190; PPC64LE-LABEL: test17:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]191; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]192; PPC64LE-NEXT: stb 4, 0(3)
193; PPC64LE-NEXT: blr
194 store atomic i8 %val, i8* %ptr monotonic, align 1
195 ret void
196}
197
198define void @test18(i8* %ptr, i8 %val) {
199; PPC64LE-LABEL: test18:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]200; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]201; PPC64LE-NEXT: lwsync
202; PPC64LE-NEXT: stb 4, 0(3)
203; PPC64LE-NEXT: blr
204 store atomic i8 %val, i8* %ptr release, align 1
205 ret void
206}
207
208define void @test19(i8* %ptr, i8 %val) {
209; PPC64LE-LABEL: test19:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]210; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]211; PPC64LE-NEXT: sync
212; PPC64LE-NEXT: stb 4, 0(3)
213; PPC64LE-NEXT: blr
214 store atomic i8 %val, i8* %ptr seq_cst, align 1
215 ret void
216}
217
218define void @test20(i16* %ptr, i16 %val) {
219; PPC64LE-LABEL: test20:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]220; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]221; PPC64LE-NEXT: sth 4, 0(3)
222; PPC64LE-NEXT: blr
223 store atomic i16 %val, i16* %ptr unordered, align 2
224 ret void
225}
226
227define void @test21(i16* %ptr, i16 %val) {
228; PPC64LE-LABEL: test21:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]229; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]230; PPC64LE-NEXT: sth 4, 0(3)
231; PPC64LE-NEXT: blr
232 store atomic i16 %val, i16* %ptr monotonic, align 2
233 ret void
234}
235
236define void @test22(i16* %ptr, i16 %val) {
237; PPC64LE-LABEL: test22:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]238; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]239; PPC64LE-NEXT: lwsync
240; PPC64LE-NEXT: sth 4, 0(3)
241; PPC64LE-NEXT: blr
242 store atomic i16 %val, i16* %ptr release, align 2
243 ret void
244}
245
246define void @test23(i16* %ptr, i16 %val) {
247; PPC64LE-LABEL: test23:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]248; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]249; PPC64LE-NEXT: sync
250; PPC64LE-NEXT: sth 4, 0(3)
251; PPC64LE-NEXT: blr
252 store atomic i16 %val, i16* %ptr seq_cst, align 2
253 ret void
254}
255
256define void @test24(i32* %ptr, i32 %val) {
257; PPC64LE-LABEL: test24:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]258; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]259; PPC64LE-NEXT: stw 4, 0(3)
260; PPC64LE-NEXT: blr
261 store atomic i32 %val, i32* %ptr unordered, align 4
262 ret void
263}
264
265define void @test25(i32* %ptr, i32 %val) {
266; PPC64LE-LABEL: test25:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]267; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]268; PPC64LE-NEXT: stw 4, 0(3)
269; PPC64LE-NEXT: blr
270 store atomic i32 %val, i32* %ptr monotonic, align 4
271 ret void
272}
273
274define void @test26(i32* %ptr, i32 %val) {
275; PPC64LE-LABEL: test26:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]276; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]277; PPC64LE-NEXT: lwsync
278; PPC64LE-NEXT: stw 4, 0(3)
279; PPC64LE-NEXT: blr
280 store atomic i32 %val, i32* %ptr release, align 4
281 ret void
282}
283
284define void @test27(i32* %ptr, i32 %val) {
285; PPC64LE-LABEL: test27:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]286; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]287; PPC64LE-NEXT: sync
288; PPC64LE-NEXT: stw 4, 0(3)
289; PPC64LE-NEXT: blr
290 store atomic i32 %val, i32* %ptr seq_cst, align 4
291 ret void
292}
293
294define void @test28(i64* %ptr, i64 %val) {
295; PPC64LE-LABEL: test28:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]296; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]297; PPC64LE-NEXT: std 4, 0(3)
298; PPC64LE-NEXT: blr
299 store atomic i64 %val, i64* %ptr unordered, align 8
300 ret void
301}
302
303define void @test29(i64* %ptr, i64 %val) {
304; PPC64LE-LABEL: test29:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]305; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]306; PPC64LE-NEXT: std 4, 0(3)
307; PPC64LE-NEXT: blr
308 store atomic i64 %val, i64* %ptr monotonic, align 8
309 ret void
310}
311
312define void @test30(i64* %ptr, i64 %val) {
313; PPC64LE-LABEL: test30:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]314; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]315; PPC64LE-NEXT: lwsync
316; PPC64LE-NEXT: std 4, 0(3)
317; PPC64LE-NEXT: blr
318 store atomic i64 %val, i64* %ptr release, align 8
319 ret void
320}
321
322define void @test31(i64* %ptr, i64 %val) {
323; PPC64LE-LABEL: test31:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]324; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]325; PPC64LE-NEXT: sync
326; PPC64LE-NEXT: std 4, 0(3)
327; PPC64LE-NEXT: blr
328 store atomic i64 %val, i64* %ptr seq_cst, align 8
329 ret void
330}
331
332define void @test32() {
333; PPC64LE-LABEL: test32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]334; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]335; PPC64LE-NEXT: lwsync
336; PPC64LE-NEXT: blr
337 fence acquire
338 ret void
339}
340
341define void @test33() {
342; PPC64LE-LABEL: test33:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]343; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]344; PPC64LE-NEXT: lwsync
345; PPC64LE-NEXT: blr
346 fence release
347 ret void
348}
349
350define void @test34() {
351; PPC64LE-LABEL: test34:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]352; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]353; PPC64LE-NEXT: lwsync
354; PPC64LE-NEXT: blr
355 fence acq_rel
356 ret void
357}
358
359define void @test35() {
360; PPC64LE-LABEL: test35:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]361; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]362; PPC64LE-NEXT: sync
363; PPC64LE-NEXT: blr
364 fence seq_cst
365 ret void
366}
367
368define void @test36() {
369; PPC64LE-LABEL: test36:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]370; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]371; PPC64LE-NEXT: lwsync
372; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]373 fence syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]374 ret void
375}
376
377define void @test37() {
378; PPC64LE-LABEL: test37:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]379; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]380; PPC64LE-NEXT: lwsync
381; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]382 fence syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]383 ret void
384}
385
386define void @test38() {
387; PPC64LE-LABEL: test38:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]388; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]389; PPC64LE-NEXT: lwsync
390; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]391 fence syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]392 ret void
393}
394
395define void @test39() {
396; PPC64LE-LABEL: test39:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]397; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]398; PPC64LE-NEXT: sync
399; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]400 fence syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]401 ret void
402}
403
404define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
405; PPC64LE-LABEL: test40:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]406; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]407; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]408; PPC64LE-NEXT: b .LBB40_2
409; PPC64LE-NEXT: .p2align 5
410; PPC64LE-NEXT: .LBB40_1:
411; PPC64LE-NEXT: stbcx. 5, 0, 3
412; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]413; PPC64LE-NEXT: .LBB40_2:
414; PPC64LE-NEXT: lbarx 6, 0, 3
415; PPC64LE-NEXT: cmpw 4, 6
416; PPC64LE-NEXT: beq 0, .LBB40_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]417; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]418; PPC64LE-NEXT: stbcx. 6, 0, 3
419; PPC64LE-NEXT: blr
420 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
421 ret void
422}
423
424define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
425; PPC64LE-LABEL: test41:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]426; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]427; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]428; PPC64LE-NEXT: .LBB41_1:
429; PPC64LE-NEXT: lbarx 6, 0, 3
430; PPC64LE-NEXT: cmpw 4, 6
431; PPC64LE-NEXT: bne 0, .LBB41_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]432; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]433; PPC64LE-NEXT: stbcx. 5, 0, 3
434; PPC64LE-NEXT: bne 0, .LBB41_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]435; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]436; PPC64LE-NEXT: lwsync
437; PPC64LE-NEXT: blr
438; PPC64LE-NEXT: .LBB41_4:
439; PPC64LE-NEXT: stbcx. 6, 0, 3
440; PPC64LE-NEXT: lwsync
441; PPC64LE-NEXT: blr
442 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
443 ret void
444}
445
446define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
447; PPC64LE-LABEL: test42:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]448; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]449; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]450; PPC64LE-NEXT: .LBB42_1:
451; PPC64LE-NEXT: lbarx 6, 0, 3
452; PPC64LE-NEXT: cmpw 4, 6
453; PPC64LE-NEXT: bne 0, .LBB42_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]454; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]455; PPC64LE-NEXT: stbcx. 5, 0, 3
456; PPC64LE-NEXT: bne 0, .LBB42_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]457; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]458; PPC64LE-NEXT: lwsync
459; PPC64LE-NEXT: blr
460; PPC64LE-NEXT: .LBB42_4:
461; PPC64LE-NEXT: stbcx. 6, 0, 3
462; PPC64LE-NEXT: lwsync
463; PPC64LE-NEXT: blr
464 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
465 ret void
466}
467
468define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
469; PPC64LE-LABEL: test43:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]470; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]471; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]472; PPC64LE-NEXT: lwsync
473; PPC64LE-NEXT: b .LBB43_2
474; PPC64LE-NEXT: .p2align 5
475; PPC64LE-NEXT: .LBB43_1:
476; PPC64LE-NEXT: stbcx. 5, 0, 3
477; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]478; PPC64LE-NEXT: .LBB43_2:
479; PPC64LE-NEXT: lbarx 6, 0, 3
480; PPC64LE-NEXT: cmpw 4, 6
481; PPC64LE-NEXT: beq 0, .LBB43_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]482; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]483; PPC64LE-NEXT: stbcx. 6, 0, 3
484; PPC64LE-NEXT: blr
485 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
486 ret void
487}
488
489define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
490; PPC64LE-LABEL: test44:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]491; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]492; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]493; PPC64LE-NEXT: lwsync
494; PPC64LE-NEXT: b .LBB44_2
495; PPC64LE-NEXT: .p2align 5
496; PPC64LE-NEXT: .LBB44_1:
497; PPC64LE-NEXT: stbcx. 5, 0, 3
498; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]499; PPC64LE-NEXT: .LBB44_2:
500; PPC64LE-NEXT: lbarx 6, 0, 3
501; PPC64LE-NEXT: cmpw 4, 6
502; PPC64LE-NEXT: beq 0, .LBB44_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]503; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]504; PPC64LE-NEXT: stbcx. 6, 0, 3
505; PPC64LE-NEXT: blr
506 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
507 ret void
508}
509
510define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
511; PPC64LE-LABEL: test45:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]512; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]513; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]514; PPC64LE-NEXT: lwsync
515; PPC64LE-NEXT: .LBB45_1:
516; PPC64LE-NEXT: lbarx 6, 0, 3
517; PPC64LE-NEXT: cmpw 4, 6
518; PPC64LE-NEXT: bne 0, .LBB45_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]519; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]520; PPC64LE-NEXT: stbcx. 5, 0, 3
521; PPC64LE-NEXT: bne 0, .LBB45_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]522; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]523; PPC64LE-NEXT: lwsync
524; PPC64LE-NEXT: blr
525; PPC64LE-NEXT: .LBB45_4:
526; PPC64LE-NEXT: stbcx. 6, 0, 3
527; PPC64LE-NEXT: lwsync
528; PPC64LE-NEXT: blr
529 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
530 ret void
531}
532
533define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
534; PPC64LE-LABEL: test46:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]535; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]536; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]537; PPC64LE-NEXT: lwsync
538; PPC64LE-NEXT: .LBB46_1:
539; PPC64LE-NEXT: lbarx 6, 0, 3
540; PPC64LE-NEXT: cmpw 4, 6
541; PPC64LE-NEXT: bne 0, .LBB46_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]542; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]543; PPC64LE-NEXT: stbcx. 5, 0, 3
544; PPC64LE-NEXT: bne 0, .LBB46_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]545; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]546; PPC64LE-NEXT: lwsync
547; PPC64LE-NEXT: blr
548; PPC64LE-NEXT: .LBB46_4:
549; PPC64LE-NEXT: stbcx. 6, 0, 3
550; PPC64LE-NEXT: lwsync
551; PPC64LE-NEXT: blr
552 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
553 ret void
554}
555
556define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
557; PPC64LE-LABEL: test47:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]558; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]559; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]560; PPC64LE-NEXT: sync
561; PPC64LE-NEXT: .LBB47_1:
562; PPC64LE-NEXT: lbarx 6, 0, 3
563; PPC64LE-NEXT: cmpw 4, 6
564; PPC64LE-NEXT: bne 0, .LBB47_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]565; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]566; PPC64LE-NEXT: stbcx. 5, 0, 3
567; PPC64LE-NEXT: bne 0, .LBB47_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]568; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]569; PPC64LE-NEXT: lwsync
570; PPC64LE-NEXT: blr
571; PPC64LE-NEXT: .LBB47_4:
572; PPC64LE-NEXT: stbcx. 6, 0, 3
573; PPC64LE-NEXT: lwsync
574; PPC64LE-NEXT: blr
575 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
576 ret void
577}
578
579define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
580; PPC64LE-LABEL: test48:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]581; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]582; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]583; PPC64LE-NEXT: sync
584; PPC64LE-NEXT: .LBB48_1:
585; PPC64LE-NEXT: lbarx 6, 0, 3
586; PPC64LE-NEXT: cmpw 4, 6
587; PPC64LE-NEXT: bne 0, .LBB48_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]588; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]589; PPC64LE-NEXT: stbcx. 5, 0, 3
590; PPC64LE-NEXT: bne 0, .LBB48_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]591; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]592; PPC64LE-NEXT: lwsync
593; PPC64LE-NEXT: blr
594; PPC64LE-NEXT: .LBB48_4:
595; PPC64LE-NEXT: stbcx. 6, 0, 3
596; PPC64LE-NEXT: lwsync
597; PPC64LE-NEXT: blr
598 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
599 ret void
600}
601
602define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
603; PPC64LE-LABEL: test49:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]604; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]605; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]606; PPC64LE-NEXT: sync
607; PPC64LE-NEXT: .LBB49_1:
608; PPC64LE-NEXT: lbarx 6, 0, 3
609; PPC64LE-NEXT: cmpw 4, 6
610; PPC64LE-NEXT: bne 0, .LBB49_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]611; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]612; PPC64LE-NEXT: stbcx. 5, 0, 3
613; PPC64LE-NEXT: bne 0, .LBB49_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]614; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]615; PPC64LE-NEXT: lwsync
616; PPC64LE-NEXT: blr
617; PPC64LE-NEXT: .LBB49_4:
618; PPC64LE-NEXT: stbcx. 6, 0, 3
619; PPC64LE-NEXT: lwsync
620; PPC64LE-NEXT: blr
621 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
622 ret void
623}
624
625define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
626; PPC64LE-LABEL: test50:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]627; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]628; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]629; PPC64LE-NEXT: b .LBB50_2
630; PPC64LE-NEXT: .p2align 5
631; PPC64LE-NEXT: .LBB50_1:
632; PPC64LE-NEXT: sthcx. 5, 0, 3
633; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]634; PPC64LE-NEXT: .LBB50_2:
635; PPC64LE-NEXT: lharx 6, 0, 3
636; PPC64LE-NEXT: cmpw 4, 6
637; PPC64LE-NEXT: beq 0, .LBB50_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]638; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]639; PPC64LE-NEXT: sthcx. 6, 0, 3
640; PPC64LE-NEXT: blr
641 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
642 ret void
643}
644
645define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
646; PPC64LE-LABEL: test51:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]647; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]648; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]649; PPC64LE-NEXT: .LBB51_1:
650; PPC64LE-NEXT: lharx 6, 0, 3
651; PPC64LE-NEXT: cmpw 4, 6
652; PPC64LE-NEXT: bne 0, .LBB51_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]653; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]654; PPC64LE-NEXT: sthcx. 5, 0, 3
655; PPC64LE-NEXT: bne 0, .LBB51_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]656; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]657; PPC64LE-NEXT: lwsync
658; PPC64LE-NEXT: blr
659; PPC64LE-NEXT: .LBB51_4:
660; PPC64LE-NEXT: sthcx. 6, 0, 3
661; PPC64LE-NEXT: lwsync
662; PPC64LE-NEXT: blr
663 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
664 ret void
665}
666
667define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
668; PPC64LE-LABEL: test52:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]669; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]670; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]671; PPC64LE-NEXT: .LBB52_1:
672; PPC64LE-NEXT: lharx 6, 0, 3
673; PPC64LE-NEXT: cmpw 4, 6
674; PPC64LE-NEXT: bne 0, .LBB52_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]675; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]676; PPC64LE-NEXT: sthcx. 5, 0, 3
677; PPC64LE-NEXT: bne 0, .LBB52_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]678; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]679; PPC64LE-NEXT: lwsync
680; PPC64LE-NEXT: blr
681; PPC64LE-NEXT: .LBB52_4:
682; PPC64LE-NEXT: sthcx. 6, 0, 3
683; PPC64LE-NEXT: lwsync
684; PPC64LE-NEXT: blr
685 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
686 ret void
687}
688
689define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
690; PPC64LE-LABEL: test53:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]691; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]692; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]693; PPC64LE-NEXT: lwsync
694; PPC64LE-NEXT: b .LBB53_2
695; PPC64LE-NEXT: .p2align 5
696; PPC64LE-NEXT: .LBB53_1:
697; PPC64LE-NEXT: sthcx. 5, 0, 3
698; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]699; PPC64LE-NEXT: .LBB53_2:
700; PPC64LE-NEXT: lharx 6, 0, 3
701; PPC64LE-NEXT: cmpw 4, 6
702; PPC64LE-NEXT: beq 0, .LBB53_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]703; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]704; PPC64LE-NEXT: sthcx. 6, 0, 3
705; PPC64LE-NEXT: blr
706 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
707 ret void
708}
709
710define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
711; PPC64LE-LABEL: test54:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]712; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]713; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]714; PPC64LE-NEXT: lwsync
715; PPC64LE-NEXT: b .LBB54_2
716; PPC64LE-NEXT: .p2align 5
717; PPC64LE-NEXT: .LBB54_1:
718; PPC64LE-NEXT: sthcx. 5, 0, 3
719; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]720; PPC64LE-NEXT: .LBB54_2:
721; PPC64LE-NEXT: lharx 6, 0, 3
722; PPC64LE-NEXT: cmpw 4, 6
723; PPC64LE-NEXT: beq 0, .LBB54_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]724; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]725; PPC64LE-NEXT: sthcx. 6, 0, 3
726; PPC64LE-NEXT: blr
727 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
728 ret void
729}
730
731define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
732; PPC64LE-LABEL: test55:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]733; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]734; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]735; PPC64LE-NEXT: lwsync
736; PPC64LE-NEXT: .LBB55_1:
737; PPC64LE-NEXT: lharx 6, 0, 3
738; PPC64LE-NEXT: cmpw 4, 6
739; PPC64LE-NEXT: bne 0, .LBB55_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]740; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]741; PPC64LE-NEXT: sthcx. 5, 0, 3
742; PPC64LE-NEXT: bne 0, .LBB55_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]743; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]744; PPC64LE-NEXT: lwsync
745; PPC64LE-NEXT: blr
746; PPC64LE-NEXT: .LBB55_4:
747; PPC64LE-NEXT: sthcx. 6, 0, 3
748; PPC64LE-NEXT: lwsync
749; PPC64LE-NEXT: blr
750 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
751 ret void
752}
753
754define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
755; PPC64LE-LABEL: test56:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]756; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]757; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]758; PPC64LE-NEXT: lwsync
759; PPC64LE-NEXT: .LBB56_1:
760; PPC64LE-NEXT: lharx 6, 0, 3
761; PPC64LE-NEXT: cmpw 4, 6
762; PPC64LE-NEXT: bne 0, .LBB56_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]763; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]764; PPC64LE-NEXT: sthcx. 5, 0, 3
765; PPC64LE-NEXT: bne 0, .LBB56_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]766; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]767; PPC64LE-NEXT: lwsync
768; PPC64LE-NEXT: blr
769; PPC64LE-NEXT: .LBB56_4:
770; PPC64LE-NEXT: sthcx. 6, 0, 3
771; PPC64LE-NEXT: lwsync
772; PPC64LE-NEXT: blr
773 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
774 ret void
775}
776
777define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
778; PPC64LE-LABEL: test57:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]779; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]780; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]781; PPC64LE-NEXT: sync
782; PPC64LE-NEXT: .LBB57_1:
783; PPC64LE-NEXT: lharx 6, 0, 3
784; PPC64LE-NEXT: cmpw 4, 6
785; PPC64LE-NEXT: bne 0, .LBB57_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]786; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]787; PPC64LE-NEXT: sthcx. 5, 0, 3
788; PPC64LE-NEXT: bne 0, .LBB57_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]789; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]790; PPC64LE-NEXT: lwsync
791; PPC64LE-NEXT: blr
792; PPC64LE-NEXT: .LBB57_4:
793; PPC64LE-NEXT: sthcx. 6, 0, 3
794; PPC64LE-NEXT: lwsync
795; PPC64LE-NEXT: blr
796 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
797 ret void
798}
799
800define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
801; PPC64LE-LABEL: test58:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]802; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]803; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]804; PPC64LE-NEXT: sync
805; PPC64LE-NEXT: .LBB58_1:
806; PPC64LE-NEXT: lharx 6, 0, 3
807; PPC64LE-NEXT: cmpw 4, 6
808; PPC64LE-NEXT: bne 0, .LBB58_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]809; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]810; PPC64LE-NEXT: sthcx. 5, 0, 3
811; PPC64LE-NEXT: bne 0, .LBB58_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]812; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]813; PPC64LE-NEXT: lwsync
814; PPC64LE-NEXT: blr
815; PPC64LE-NEXT: .LBB58_4:
816; PPC64LE-NEXT: sthcx. 6, 0, 3
817; PPC64LE-NEXT: lwsync
818; PPC64LE-NEXT: blr
819 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
820 ret void
821}
822
823define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
824; PPC64LE-LABEL: test59:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]825; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]826; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]827; PPC64LE-NEXT: sync
828; PPC64LE-NEXT: .LBB59_1:
829; PPC64LE-NEXT: lharx 6, 0, 3
830; PPC64LE-NEXT: cmpw 4, 6
831; PPC64LE-NEXT: bne 0, .LBB59_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]832; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]833; PPC64LE-NEXT: sthcx. 5, 0, 3
834; PPC64LE-NEXT: bne 0, .LBB59_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]835; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]836; PPC64LE-NEXT: lwsync
837; PPC64LE-NEXT: blr
838; PPC64LE-NEXT: .LBB59_4:
839; PPC64LE-NEXT: sthcx. 6, 0, 3
840; PPC64LE-NEXT: lwsync
841; PPC64LE-NEXT: blr
842 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
843 ret void
844}
845
846define void @test60(i32* %ptr, i32 %cmp, i32 %val) {
847; PPC64LE-LABEL: test60:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]848; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]849; PPC64LE-NEXT: b .LBB60_2
850; PPC64LE-NEXT: .p2align 5
851; PPC64LE-NEXT: .LBB60_1:
852; PPC64LE-NEXT: stwcx. 5, 0, 3
853; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]854; PPC64LE-NEXT: .LBB60_2:
855; PPC64LE-NEXT: lwarx 6, 0, 3
856; PPC64LE-NEXT: cmpw 4, 6
857; PPC64LE-NEXT: beq 0, .LBB60_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]858; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]859; PPC64LE-NEXT: stwcx. 6, 0, 3
860; PPC64LE-NEXT: blr
861 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
862 ret void
863}
864
865define void @test61(i32* %ptr, i32 %cmp, i32 %val) {
866; PPC64LE-LABEL: test61:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]867; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]868; PPC64LE-NEXT: .LBB61_1:
869; PPC64LE-NEXT: lwarx 6, 0, 3
870; PPC64LE-NEXT: cmpw 4, 6
871; PPC64LE-NEXT: bne 0, .LBB61_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]872; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]873; PPC64LE-NEXT: stwcx. 5, 0, 3
874; PPC64LE-NEXT: bne 0, .LBB61_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]875; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]876; PPC64LE-NEXT: lwsync
877; PPC64LE-NEXT: blr
878; PPC64LE-NEXT: .LBB61_4:
879; PPC64LE-NEXT: stwcx. 6, 0, 3
880; PPC64LE-NEXT: lwsync
881; PPC64LE-NEXT: blr
882 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
883 ret void
884}
885
886define void @test62(i32* %ptr, i32 %cmp, i32 %val) {
887; PPC64LE-LABEL: test62:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]888; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]889; PPC64LE-NEXT: .LBB62_1:
890; PPC64LE-NEXT: lwarx 6, 0, 3
891; PPC64LE-NEXT: cmpw 4, 6
892; PPC64LE-NEXT: bne 0, .LBB62_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]893; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]894; PPC64LE-NEXT: stwcx. 5, 0, 3
895; PPC64LE-NEXT: bne 0, .LBB62_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]896; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]897; PPC64LE-NEXT: lwsync
898; PPC64LE-NEXT: blr
899; PPC64LE-NEXT: .LBB62_4:
900; PPC64LE-NEXT: stwcx. 6, 0, 3
901; PPC64LE-NEXT: lwsync
902; PPC64LE-NEXT: blr
903 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
904 ret void
905}
906
907define void @test63(i32* %ptr, i32 %cmp, i32 %val) {
908; PPC64LE-LABEL: test63:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]909; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]910; PPC64LE-NEXT: lwsync
911; PPC64LE-NEXT: b .LBB63_2
912; PPC64LE-NEXT: .p2align 5
913; PPC64LE-NEXT: .LBB63_1:
914; PPC64LE-NEXT: stwcx. 5, 0, 3
915; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]916; PPC64LE-NEXT: .LBB63_2:
917; PPC64LE-NEXT: lwarx 6, 0, 3
918; PPC64LE-NEXT: cmpw 4, 6
919; PPC64LE-NEXT: beq 0, .LBB63_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]920; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]921; PPC64LE-NEXT: stwcx. 6, 0, 3
922; PPC64LE-NEXT: blr
923 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
924 ret void
925}
926
927define void @test64(i32* %ptr, i32 %cmp, i32 %val) {
928; PPC64LE-LABEL: test64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]929; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]930; PPC64LE-NEXT: lwsync
931; PPC64LE-NEXT: b .LBB64_2
932; PPC64LE-NEXT: .p2align 5
933; PPC64LE-NEXT: .LBB64_1:
934; PPC64LE-NEXT: stwcx. 5, 0, 3
935; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]936; PPC64LE-NEXT: .LBB64_2:
937; PPC64LE-NEXT: lwarx 6, 0, 3
938; PPC64LE-NEXT: cmpw 4, 6
939; PPC64LE-NEXT: beq 0, .LBB64_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]940; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]941; PPC64LE-NEXT: stwcx. 6, 0, 3
942; PPC64LE-NEXT: blr
943 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
944 ret void
945}
946
947define void @test65(i32* %ptr, i32 %cmp, i32 %val) {
948; PPC64LE-LABEL: test65:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]949; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]950; PPC64LE-NEXT: lwsync
951; PPC64LE-NEXT: .LBB65_1:
952; PPC64LE-NEXT: lwarx 6, 0, 3
953; PPC64LE-NEXT: cmpw 4, 6
954; PPC64LE-NEXT: bne 0, .LBB65_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]955; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]956; PPC64LE-NEXT: stwcx. 5, 0, 3
957; PPC64LE-NEXT: bne 0, .LBB65_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]958; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]959; PPC64LE-NEXT: lwsync
960; PPC64LE-NEXT: blr
961; PPC64LE-NEXT: .LBB65_4:
962; PPC64LE-NEXT: stwcx. 6, 0, 3
963; PPC64LE-NEXT: lwsync
964; PPC64LE-NEXT: blr
965 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
966 ret void
967}
968
969define void @test66(i32* %ptr, i32 %cmp, i32 %val) {
970; PPC64LE-LABEL: test66:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]971; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]972; PPC64LE-NEXT: lwsync
973; PPC64LE-NEXT: .LBB66_1:
974; PPC64LE-NEXT: lwarx 6, 0, 3
975; PPC64LE-NEXT: cmpw 4, 6
976; PPC64LE-NEXT: bne 0, .LBB66_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]977; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]978; PPC64LE-NEXT: stwcx. 5, 0, 3
979; PPC64LE-NEXT: bne 0, .LBB66_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]980; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]981; PPC64LE-NEXT: lwsync
982; PPC64LE-NEXT: blr
983; PPC64LE-NEXT: .LBB66_4:
984; PPC64LE-NEXT: stwcx. 6, 0, 3
985; PPC64LE-NEXT: lwsync
986; PPC64LE-NEXT: blr
987 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
988 ret void
989}
990
991define void @test67(i32* %ptr, i32 %cmp, i32 %val) {
992; PPC64LE-LABEL: test67:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]993; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]994; PPC64LE-NEXT: sync
995; PPC64LE-NEXT: .LBB67_1:
996; PPC64LE-NEXT: lwarx 6, 0, 3
997; PPC64LE-NEXT: cmpw 4, 6
998; PPC64LE-NEXT: bne 0, .LBB67_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]999; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1000; PPC64LE-NEXT: stwcx. 5, 0, 3
1001; PPC64LE-NEXT: bne 0, .LBB67_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1002; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1003; PPC64LE-NEXT: lwsync
1004; PPC64LE-NEXT: blr
1005; PPC64LE-NEXT: .LBB67_4:
1006; PPC64LE-NEXT: stwcx. 6, 0, 3
1007; PPC64LE-NEXT: lwsync
1008; PPC64LE-NEXT: blr
1009 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
1010 ret void
1011}
1012
1013define void @test68(i32* %ptr, i32 %cmp, i32 %val) {
1014; PPC64LE-LABEL: test68:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1015; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1016; PPC64LE-NEXT: sync
1017; PPC64LE-NEXT: .LBB68_1:
1018; PPC64LE-NEXT: lwarx 6, 0, 3
1019; PPC64LE-NEXT: cmpw 4, 6
1020; PPC64LE-NEXT: bne 0, .LBB68_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1021; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1022; PPC64LE-NEXT: stwcx. 5, 0, 3
1023; PPC64LE-NEXT: bne 0, .LBB68_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1024; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1025; PPC64LE-NEXT: lwsync
1026; PPC64LE-NEXT: blr
1027; PPC64LE-NEXT: .LBB68_4:
1028; PPC64LE-NEXT: stwcx. 6, 0, 3
1029; PPC64LE-NEXT: lwsync
1030; PPC64LE-NEXT: blr
1031 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
1032 ret void
1033}
1034
1035define void @test69(i32* %ptr, i32 %cmp, i32 %val) {
1036; PPC64LE-LABEL: test69:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1037; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1038; PPC64LE-NEXT: sync
1039; PPC64LE-NEXT: .LBB69_1:
1040; PPC64LE-NEXT: lwarx 6, 0, 3
1041; PPC64LE-NEXT: cmpw 4, 6
1042; PPC64LE-NEXT: bne 0, .LBB69_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1043; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1044; PPC64LE-NEXT: stwcx. 5, 0, 3
1045; PPC64LE-NEXT: bne 0, .LBB69_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1046; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1047; PPC64LE-NEXT: lwsync
1048; PPC64LE-NEXT: blr
1049; PPC64LE-NEXT: .LBB69_4:
1050; PPC64LE-NEXT: stwcx. 6, 0, 3
1051; PPC64LE-NEXT: lwsync
1052; PPC64LE-NEXT: blr
1053 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
1054 ret void
1055}
1056
1057define void @test70(i64* %ptr, i64 %cmp, i64 %val) {
1058; PPC64LE-LABEL: test70:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1059; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1060; PPC64LE-NEXT: b .LBB70_2
1061; PPC64LE-NEXT: .p2align 5
1062; PPC64LE-NEXT: .LBB70_1:
1063; PPC64LE-NEXT: stdcx. 5, 0, 3
1064; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1065; PPC64LE-NEXT: .LBB70_2:
1066; PPC64LE-NEXT: ldarx 6, 0, 3
1067; PPC64LE-NEXT: cmpd 4, 6
1068; PPC64LE-NEXT: beq 0, .LBB70_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1069; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1070; PPC64LE-NEXT: stdcx. 6, 0, 3
1071; PPC64LE-NEXT: blr
1072 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
1073 ret void
1074}
1075
1076define void @test71(i64* %ptr, i64 %cmp, i64 %val) {
1077; PPC64LE-LABEL: test71:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1078; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1079; PPC64LE-NEXT: .LBB71_1:
1080; PPC64LE-NEXT: ldarx 6, 0, 3
1081; PPC64LE-NEXT: cmpd 4, 6
1082; PPC64LE-NEXT: bne 0, .LBB71_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1083; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1084; PPC64LE-NEXT: stdcx. 5, 0, 3
1085; PPC64LE-NEXT: bne 0, .LBB71_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1086; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1087; PPC64LE-NEXT: lwsync
1088; PPC64LE-NEXT: blr
1089; PPC64LE-NEXT: .LBB71_4:
1090; PPC64LE-NEXT: stdcx. 6, 0, 3
1091; PPC64LE-NEXT: lwsync
1092; PPC64LE-NEXT: blr
1093 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
1094 ret void
1095}
1096
1097define void @test72(i64* %ptr, i64 %cmp, i64 %val) {
1098; PPC64LE-LABEL: test72:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1099; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1100; PPC64LE-NEXT: .LBB72_1:
1101; PPC64LE-NEXT: ldarx 6, 0, 3
1102; PPC64LE-NEXT: cmpd 4, 6
1103; PPC64LE-NEXT: bne 0, .LBB72_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1104; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1105; PPC64LE-NEXT: stdcx. 5, 0, 3
1106; PPC64LE-NEXT: bne 0, .LBB72_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1107; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1108; PPC64LE-NEXT: lwsync
1109; PPC64LE-NEXT: blr
1110; PPC64LE-NEXT: .LBB72_4:
1111; PPC64LE-NEXT: stdcx. 6, 0, 3
1112; PPC64LE-NEXT: lwsync
1113; PPC64LE-NEXT: blr
1114 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
1115 ret void
1116}
1117
1118define void @test73(i64* %ptr, i64 %cmp, i64 %val) {
1119; PPC64LE-LABEL: test73:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1120; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1121; PPC64LE-NEXT: lwsync
1122; PPC64LE-NEXT: b .LBB73_2
1123; PPC64LE-NEXT: .p2align 5
1124; PPC64LE-NEXT: .LBB73_1:
1125; PPC64LE-NEXT: stdcx. 5, 0, 3
1126; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1127; PPC64LE-NEXT: .LBB73_2:
1128; PPC64LE-NEXT: ldarx 6, 0, 3
1129; PPC64LE-NEXT: cmpd 4, 6
1130; PPC64LE-NEXT: beq 0, .LBB73_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1131; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1132; PPC64LE-NEXT: stdcx. 6, 0, 3
1133; PPC64LE-NEXT: blr
1134 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
1135 ret void
1136}
1137
1138define void @test74(i64* %ptr, i64 %cmp, i64 %val) {
1139; PPC64LE-LABEL: test74:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1140; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1141; PPC64LE-NEXT: lwsync
1142; PPC64LE-NEXT: b .LBB74_2
1143; PPC64LE-NEXT: .p2align 5
1144; PPC64LE-NEXT: .LBB74_1:
1145; PPC64LE-NEXT: stdcx. 5, 0, 3
1146; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1147; PPC64LE-NEXT: .LBB74_2:
1148; PPC64LE-NEXT: ldarx 6, 0, 3
1149; PPC64LE-NEXT: cmpd 4, 6
1150; PPC64LE-NEXT: beq 0, .LBB74_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1151; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1152; PPC64LE-NEXT: stdcx. 6, 0, 3
1153; PPC64LE-NEXT: blr
1154 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
1155 ret void
1156}
1157
1158define void @test75(i64* %ptr, i64 %cmp, i64 %val) {
1159; PPC64LE-LABEL: test75:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1160; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1161; PPC64LE-NEXT: lwsync
1162; PPC64LE-NEXT: .LBB75_1:
1163; PPC64LE-NEXT: ldarx 6, 0, 3
1164; PPC64LE-NEXT: cmpd 4, 6
1165; PPC64LE-NEXT: bne 0, .LBB75_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1166; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1167; PPC64LE-NEXT: stdcx. 5, 0, 3
1168; PPC64LE-NEXT: bne 0, .LBB75_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1169; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1170; PPC64LE-NEXT: lwsync
1171; PPC64LE-NEXT: blr
1172; PPC64LE-NEXT: .LBB75_4:
1173; PPC64LE-NEXT: stdcx. 6, 0, 3
1174; PPC64LE-NEXT: lwsync
1175; PPC64LE-NEXT: blr
1176 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
1177 ret void
1178}
1179
1180define void @test76(i64* %ptr, i64 %cmp, i64 %val) {
1181; PPC64LE-LABEL: test76:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1182; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1183; PPC64LE-NEXT: lwsync
1184; PPC64LE-NEXT: .LBB76_1:
1185; PPC64LE-NEXT: ldarx 6, 0, 3
1186; PPC64LE-NEXT: cmpd 4, 6
1187; PPC64LE-NEXT: bne 0, .LBB76_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1188; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1189; PPC64LE-NEXT: stdcx. 5, 0, 3
1190; PPC64LE-NEXT: bne 0, .LBB76_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1191; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1192; PPC64LE-NEXT: lwsync
1193; PPC64LE-NEXT: blr
1194; PPC64LE-NEXT: .LBB76_4:
1195; PPC64LE-NEXT: stdcx. 6, 0, 3
1196; PPC64LE-NEXT: lwsync
1197; PPC64LE-NEXT: blr
1198 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
1199 ret void
1200}
1201
1202define void @test77(i64* %ptr, i64 %cmp, i64 %val) {
1203; PPC64LE-LABEL: test77:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1204; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1205; PPC64LE-NEXT: sync
1206; PPC64LE-NEXT: .LBB77_1:
1207; PPC64LE-NEXT: ldarx 6, 0, 3
1208; PPC64LE-NEXT: cmpd 4, 6
1209; PPC64LE-NEXT: bne 0, .LBB77_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1210; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1211; PPC64LE-NEXT: stdcx. 5, 0, 3
1212; PPC64LE-NEXT: bne 0, .LBB77_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1213; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1214; PPC64LE-NEXT: lwsync
1215; PPC64LE-NEXT: blr
1216; PPC64LE-NEXT: .LBB77_4:
1217; PPC64LE-NEXT: stdcx. 6, 0, 3
1218; PPC64LE-NEXT: lwsync
1219; PPC64LE-NEXT: blr
1220 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
1221 ret void
1222}
1223
1224define void @test78(i64* %ptr, i64 %cmp, i64 %val) {
1225; PPC64LE-LABEL: test78:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1226; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1227; PPC64LE-NEXT: sync
1228; PPC64LE-NEXT: .LBB78_1:
1229; PPC64LE-NEXT: ldarx 6, 0, 3
1230; PPC64LE-NEXT: cmpd 4, 6
1231; PPC64LE-NEXT: bne 0, .LBB78_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1232; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1233; PPC64LE-NEXT: stdcx. 5, 0, 3
1234; PPC64LE-NEXT: bne 0, .LBB78_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1235; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1236; PPC64LE-NEXT: lwsync
1237; PPC64LE-NEXT: blr
1238; PPC64LE-NEXT: .LBB78_4:
1239; PPC64LE-NEXT: stdcx. 6, 0, 3
1240; PPC64LE-NEXT: lwsync
1241; PPC64LE-NEXT: blr
1242 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
1243 ret void
1244}
1245
1246define void @test79(i64* %ptr, i64 %cmp, i64 %val) {
1247; PPC64LE-LABEL: test79:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1248; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1249; PPC64LE-NEXT: sync
1250; PPC64LE-NEXT: .LBB79_1:
1251; PPC64LE-NEXT: ldarx 6, 0, 3
1252; PPC64LE-NEXT: cmpd 4, 6
1253; PPC64LE-NEXT: bne 0, .LBB79_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1254; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1255; PPC64LE-NEXT: stdcx. 5, 0, 3
1256; PPC64LE-NEXT: bne 0, .LBB79_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1257; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1258; PPC64LE-NEXT: lwsync
1259; PPC64LE-NEXT: blr
1260; PPC64LE-NEXT: .LBB79_4:
1261; PPC64LE-NEXT: stdcx. 6, 0, 3
1262; PPC64LE-NEXT: lwsync
1263; PPC64LE-NEXT: blr
1264 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
1265 ret void
1266}
1267
1268define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
1269; PPC64LE-LABEL: test80:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1270; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1271; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1272; PPC64LE-NEXT: b .LBB80_2
1273; PPC64LE-NEXT: .p2align 5
1274; PPC64LE-NEXT: .LBB80_1:
1275; PPC64LE-NEXT: stbcx. 5, 0, 3
1276; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1277; PPC64LE-NEXT: .LBB80_2:
1278; PPC64LE-NEXT: lbarx 6, 0, 3
1279; PPC64LE-NEXT: cmpw 4, 6
1280; PPC64LE-NEXT: beq 0, .LBB80_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1281; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1282; PPC64LE-NEXT: stbcx. 6, 0, 3
1283; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1284 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1285 ret void
1286}
1287
1288define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
1289; PPC64LE-LABEL: test81:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1290; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1291; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1292; PPC64LE-NEXT: .LBB81_1:
1293; PPC64LE-NEXT: lbarx 6, 0, 3
1294; PPC64LE-NEXT: cmpw 4, 6
1295; PPC64LE-NEXT: bne 0, .LBB81_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1296; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1297; PPC64LE-NEXT: stbcx. 5, 0, 3
1298; PPC64LE-NEXT: bne 0, .LBB81_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1299; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1300; PPC64LE-NEXT: lwsync
1301; PPC64LE-NEXT: blr
1302; PPC64LE-NEXT: .LBB81_4:
1303; PPC64LE-NEXT: stbcx. 6, 0, 3
1304; PPC64LE-NEXT: lwsync
1305; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1306 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1307 ret void
1308}
1309
1310define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
1311; PPC64LE-LABEL: test82:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1312; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1313; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1314; PPC64LE-NEXT: .LBB82_1:
1315; PPC64LE-NEXT: lbarx 6, 0, 3
1316; PPC64LE-NEXT: cmpw 4, 6
1317; PPC64LE-NEXT: bne 0, .LBB82_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1318; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1319; PPC64LE-NEXT: stbcx. 5, 0, 3
1320; PPC64LE-NEXT: bne 0, .LBB82_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1321; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1322; PPC64LE-NEXT: lwsync
1323; PPC64LE-NEXT: blr
1324; PPC64LE-NEXT: .LBB82_4:
1325; PPC64LE-NEXT: stbcx. 6, 0, 3
1326; PPC64LE-NEXT: lwsync
1327; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1328 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1329 ret void
1330}
1331
1332define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
1333; PPC64LE-LABEL: test83:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1334; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1335; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1336; PPC64LE-NEXT: lwsync
1337; PPC64LE-NEXT: b .LBB83_2
1338; PPC64LE-NEXT: .p2align 5
1339; PPC64LE-NEXT: .LBB83_1:
1340; PPC64LE-NEXT: stbcx. 5, 0, 3
1341; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1342; PPC64LE-NEXT: .LBB83_2:
1343; PPC64LE-NEXT: lbarx 6, 0, 3
1344; PPC64LE-NEXT: cmpw 4, 6
1345; PPC64LE-NEXT: beq 0, .LBB83_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1346; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1347; PPC64LE-NEXT: stbcx. 6, 0, 3
1348; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1349 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1350 ret void
1351}
1352
1353define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
1354; PPC64LE-LABEL: test84:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1355; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1356; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1357; PPC64LE-NEXT: lwsync
1358; PPC64LE-NEXT: b .LBB84_2
1359; PPC64LE-NEXT: .p2align 5
1360; PPC64LE-NEXT: .LBB84_1:
1361; PPC64LE-NEXT: stbcx. 5, 0, 3
1362; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1363; PPC64LE-NEXT: .LBB84_2:
1364; PPC64LE-NEXT: lbarx 6, 0, 3
1365; PPC64LE-NEXT: cmpw 4, 6
1366; PPC64LE-NEXT: beq 0, .LBB84_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1367; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1368; PPC64LE-NEXT: stbcx. 6, 0, 3
1369; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1370 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1371 ret void
1372}
1373
1374define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
1375; PPC64LE-LABEL: test85:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1376; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1377; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1378; PPC64LE-NEXT: lwsync
1379; PPC64LE-NEXT: .LBB85_1:
1380; PPC64LE-NEXT: lbarx 6, 0, 3
1381; PPC64LE-NEXT: cmpw 4, 6
1382; PPC64LE-NEXT: bne 0, .LBB85_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1383; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1384; PPC64LE-NEXT: stbcx. 5, 0, 3
1385; PPC64LE-NEXT: bne 0, .LBB85_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1386; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1387; PPC64LE-NEXT: lwsync
1388; PPC64LE-NEXT: blr
1389; PPC64LE-NEXT: .LBB85_4:
1390; PPC64LE-NEXT: stbcx. 6, 0, 3
1391; PPC64LE-NEXT: lwsync
1392; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1393 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1394 ret void
1395}
1396
1397define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
1398; PPC64LE-LABEL: test86:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1399; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1400; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1401; PPC64LE-NEXT: lwsync
1402; PPC64LE-NEXT: .LBB86_1:
1403; PPC64LE-NEXT: lbarx 6, 0, 3
1404; PPC64LE-NEXT: cmpw 4, 6
1405; PPC64LE-NEXT: bne 0, .LBB86_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1406; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1407; PPC64LE-NEXT: stbcx. 5, 0, 3
1408; PPC64LE-NEXT: bne 0, .LBB86_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1409; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1410; PPC64LE-NEXT: lwsync
1411; PPC64LE-NEXT: blr
1412; PPC64LE-NEXT: .LBB86_4:
1413; PPC64LE-NEXT: stbcx. 6, 0, 3
1414; PPC64LE-NEXT: lwsync
1415; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1416 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1417 ret void
1418}
1419
1420define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
1421; PPC64LE-LABEL: test87:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1422; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1423; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1424; PPC64LE-NEXT: sync
1425; PPC64LE-NEXT: .LBB87_1:
1426; PPC64LE-NEXT: lbarx 6, 0, 3
1427; PPC64LE-NEXT: cmpw 4, 6
1428; PPC64LE-NEXT: bne 0, .LBB87_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1429; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1430; PPC64LE-NEXT: stbcx. 5, 0, 3
1431; PPC64LE-NEXT: bne 0, .LBB87_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1432; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1433; PPC64LE-NEXT: lwsync
1434; PPC64LE-NEXT: blr
1435; PPC64LE-NEXT: .LBB87_4:
1436; PPC64LE-NEXT: stbcx. 6, 0, 3
1437; PPC64LE-NEXT: lwsync
1438; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1439 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1440 ret void
1441}
1442
1443define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
1444; PPC64LE-LABEL: test88:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1445; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1446; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1447; PPC64LE-NEXT: sync
1448; PPC64LE-NEXT: .LBB88_1:
1449; PPC64LE-NEXT: lbarx 6, 0, 3
1450; PPC64LE-NEXT: cmpw 4, 6
1451; PPC64LE-NEXT: bne 0, .LBB88_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1452; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1453; PPC64LE-NEXT: stbcx. 5, 0, 3
1454; PPC64LE-NEXT: bne 0, .LBB88_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1455; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1456; PPC64LE-NEXT: lwsync
1457; PPC64LE-NEXT: blr
1458; PPC64LE-NEXT: .LBB88_4:
1459; PPC64LE-NEXT: stbcx. 6, 0, 3
1460; PPC64LE-NEXT: lwsync
1461; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1462 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1463 ret void
1464}
1465
1466define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
1467; PPC64LE-LABEL: test89:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1468; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1469; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1470; PPC64LE-NEXT: sync
1471; PPC64LE-NEXT: .LBB89_1:
1472; PPC64LE-NEXT: lbarx 6, 0, 3
1473; PPC64LE-NEXT: cmpw 4, 6
1474; PPC64LE-NEXT: bne 0, .LBB89_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1475; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1476; PPC64LE-NEXT: stbcx. 5, 0, 3
1477; PPC64LE-NEXT: bne 0, .LBB89_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1478; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1479; PPC64LE-NEXT: lwsync
1480; PPC64LE-NEXT: blr
1481; PPC64LE-NEXT: .LBB89_4:
1482; PPC64LE-NEXT: stbcx. 6, 0, 3
1483; PPC64LE-NEXT: lwsync
1484; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1485 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1486 ret void
1487}
1488
1489define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
1490; PPC64LE-LABEL: test90:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1491; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1492; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1493; PPC64LE-NEXT: b .LBB90_2
1494; PPC64LE-NEXT: .p2align 5
1495; PPC64LE-NEXT: .LBB90_1:
1496; PPC64LE-NEXT: sthcx. 5, 0, 3
1497; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1498; PPC64LE-NEXT: .LBB90_2:
1499; PPC64LE-NEXT: lharx 6, 0, 3
1500; PPC64LE-NEXT: cmpw 4, 6
1501; PPC64LE-NEXT: beq 0, .LBB90_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1502; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1503; PPC64LE-NEXT: sthcx. 6, 0, 3
1504; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1505 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1506 ret void
1507}
1508
1509define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
1510; PPC64LE-LABEL: test91:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1511; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1512; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1513; PPC64LE-NEXT: .LBB91_1:
1514; PPC64LE-NEXT: lharx 6, 0, 3
1515; PPC64LE-NEXT: cmpw 4, 6
1516; PPC64LE-NEXT: bne 0, .LBB91_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1517; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1518; PPC64LE-NEXT: sthcx. 5, 0, 3
1519; PPC64LE-NEXT: bne 0, .LBB91_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1520; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1521; PPC64LE-NEXT: lwsync
1522; PPC64LE-NEXT: blr
1523; PPC64LE-NEXT: .LBB91_4:
1524; PPC64LE-NEXT: sthcx. 6, 0, 3
1525; PPC64LE-NEXT: lwsync
1526; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1527 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1528 ret void
1529}
1530
1531define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
1532; PPC64LE-LABEL: test92:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1533; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1534; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1535; PPC64LE-NEXT: .LBB92_1:
1536; PPC64LE-NEXT: lharx 6, 0, 3
1537; PPC64LE-NEXT: cmpw 4, 6
1538; PPC64LE-NEXT: bne 0, .LBB92_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1539; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1540; PPC64LE-NEXT: sthcx. 5, 0, 3
1541; PPC64LE-NEXT: bne 0, .LBB92_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1542; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1543; PPC64LE-NEXT: lwsync
1544; PPC64LE-NEXT: blr
1545; PPC64LE-NEXT: .LBB92_4:
1546; PPC64LE-NEXT: sthcx. 6, 0, 3
1547; PPC64LE-NEXT: lwsync
1548; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1549 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1550 ret void
1551}
1552
1553define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
1554; PPC64LE-LABEL: test93:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1555; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1556; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1557; PPC64LE-NEXT: lwsync
1558; PPC64LE-NEXT: b .LBB93_2
1559; PPC64LE-NEXT: .p2align 5
1560; PPC64LE-NEXT: .LBB93_1:
1561; PPC64LE-NEXT: sthcx. 5, 0, 3
1562; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1563; PPC64LE-NEXT: .LBB93_2:
1564; PPC64LE-NEXT: lharx 6, 0, 3
1565; PPC64LE-NEXT: cmpw 4, 6
1566; PPC64LE-NEXT: beq 0, .LBB93_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1567; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1568; PPC64LE-NEXT: sthcx. 6, 0, 3
1569; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1570 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1571 ret void
1572}
1573
1574define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
1575; PPC64LE-LABEL: test94:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1576; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1577; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1578; PPC64LE-NEXT: lwsync
1579; PPC64LE-NEXT: b .LBB94_2
1580; PPC64LE-NEXT: .p2align 5
1581; PPC64LE-NEXT: .LBB94_1:
1582; PPC64LE-NEXT: sthcx. 5, 0, 3
1583; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1584; PPC64LE-NEXT: .LBB94_2:
1585; PPC64LE-NEXT: lharx 6, 0, 3
1586; PPC64LE-NEXT: cmpw 4, 6
1587; PPC64LE-NEXT: beq 0, .LBB94_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1588; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1589; PPC64LE-NEXT: sthcx. 6, 0, 3
1590; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1591 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1592 ret void
1593}
1594
1595define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
1596; PPC64LE-LABEL: test95:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1597; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1598; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1599; PPC64LE-NEXT: lwsync
1600; PPC64LE-NEXT: .LBB95_1:
1601; PPC64LE-NEXT: lharx 6, 0, 3
1602; PPC64LE-NEXT: cmpw 4, 6
1603; PPC64LE-NEXT: bne 0, .LBB95_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1604; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1605; PPC64LE-NEXT: sthcx. 5, 0, 3
1606; PPC64LE-NEXT: bne 0, .LBB95_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1607; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1608; PPC64LE-NEXT: lwsync
1609; PPC64LE-NEXT: blr
1610; PPC64LE-NEXT: .LBB95_4:
1611; PPC64LE-NEXT: sthcx. 6, 0, 3
1612; PPC64LE-NEXT: lwsync
1613; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1614 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1615 ret void
1616}
1617
1618define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
1619; PPC64LE-LABEL: test96:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1620; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1621; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1622; PPC64LE-NEXT: lwsync
1623; PPC64LE-NEXT: .LBB96_1:
1624; PPC64LE-NEXT: lharx 6, 0, 3
1625; PPC64LE-NEXT: cmpw 4, 6
1626; PPC64LE-NEXT: bne 0, .LBB96_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1627; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1628; PPC64LE-NEXT: sthcx. 5, 0, 3
1629; PPC64LE-NEXT: bne 0, .LBB96_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1630; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1631; PPC64LE-NEXT: lwsync
1632; PPC64LE-NEXT: blr
1633; PPC64LE-NEXT: .LBB96_4:
1634; PPC64LE-NEXT: sthcx. 6, 0, 3
1635; PPC64LE-NEXT: lwsync
1636; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1637 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1638 ret void
1639}
1640
1641define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
1642; PPC64LE-LABEL: test97:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1643; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1644; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1645; PPC64LE-NEXT: sync
1646; PPC64LE-NEXT: .LBB97_1:
1647; PPC64LE-NEXT: lharx 6, 0, 3
1648; PPC64LE-NEXT: cmpw 4, 6
1649; PPC64LE-NEXT: bne 0, .LBB97_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1650; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1651; PPC64LE-NEXT: sthcx. 5, 0, 3
1652; PPC64LE-NEXT: bne 0, .LBB97_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1653; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1654; PPC64LE-NEXT: lwsync
1655; PPC64LE-NEXT: blr
1656; PPC64LE-NEXT: .LBB97_4:
1657; PPC64LE-NEXT: sthcx. 6, 0, 3
1658; PPC64LE-NEXT: lwsync
1659; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1660 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1661 ret void
1662}
1663
1664define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
1665; PPC64LE-LABEL: test98:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1666; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1667; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1668; PPC64LE-NEXT: sync
1669; PPC64LE-NEXT: .LBB98_1:
1670; PPC64LE-NEXT: lharx 6, 0, 3
1671; PPC64LE-NEXT: cmpw 4, 6
1672; PPC64LE-NEXT: bne 0, .LBB98_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1673; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1674; PPC64LE-NEXT: sthcx. 5, 0, 3
1675; PPC64LE-NEXT: bne 0, .LBB98_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1676; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1677; PPC64LE-NEXT: lwsync
1678; PPC64LE-NEXT: blr
1679; PPC64LE-NEXT: .LBB98_4:
1680; PPC64LE-NEXT: sthcx. 6, 0, 3
1681; PPC64LE-NEXT: lwsync
1682; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1683 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1684 ret void
1685}
1686
1687define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
1688; PPC64LE-LABEL: test99:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1689; PPC64LE: # %bb.0:
Nemanja Ivanovicebb23072018-01-12 14:58:41 +0000[diff] [blame]1690; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1691; PPC64LE-NEXT: sync
1692; PPC64LE-NEXT: .LBB99_1:
1693; PPC64LE-NEXT: lharx 6, 0, 3
1694; PPC64LE-NEXT: cmpw 4, 6
1695; PPC64LE-NEXT: bne 0, .LBB99_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1696; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1697; PPC64LE-NEXT: sthcx. 5, 0, 3
1698; PPC64LE-NEXT: bne 0, .LBB99_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1699; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1700; PPC64LE-NEXT: lwsync
1701; PPC64LE-NEXT: blr
1702; PPC64LE-NEXT: .LBB99_4:
1703; PPC64LE-NEXT: sthcx. 6, 0, 3
1704; PPC64LE-NEXT: lwsync
1705; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1706 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1707 ret void
1708}
1709
1710define void @test100(i32* %ptr, i32 %cmp, i32 %val) {
1711; PPC64LE-LABEL: test100:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1712; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1713; PPC64LE-NEXT: b .LBB100_2
1714; PPC64LE-NEXT: .p2align 5
1715; PPC64LE-NEXT: .LBB100_1:
1716; PPC64LE-NEXT: stwcx. 5, 0, 3
1717; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1718; PPC64LE-NEXT: .LBB100_2:
1719; PPC64LE-NEXT: lwarx 6, 0, 3
1720; PPC64LE-NEXT: cmpw 4, 6
1721; PPC64LE-NEXT: beq 0, .LBB100_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1722; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1723; PPC64LE-NEXT: stwcx. 6, 0, 3
1724; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1725 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1726 ret void
1727}
1728
1729define void @test101(i32* %ptr, i32 %cmp, i32 %val) {
1730; PPC64LE-LABEL: test101:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1731; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1732; PPC64LE-NEXT: .LBB101_1:
1733; PPC64LE-NEXT: lwarx 6, 0, 3
1734; PPC64LE-NEXT: cmpw 4, 6
1735; PPC64LE-NEXT: bne 0, .LBB101_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1736; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1737; PPC64LE-NEXT: stwcx. 5, 0, 3
1738; PPC64LE-NEXT: bne 0, .LBB101_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1739; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1740; PPC64LE-NEXT: lwsync
1741; PPC64LE-NEXT: blr
1742; PPC64LE-NEXT: .LBB101_4:
1743; PPC64LE-NEXT: stwcx. 6, 0, 3
1744; PPC64LE-NEXT: lwsync
1745; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1746 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1747 ret void
1748}
1749
1750define void @test102(i32* %ptr, i32 %cmp, i32 %val) {
1751; PPC64LE-LABEL: test102:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1752; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1753; PPC64LE-NEXT: .LBB102_1:
1754; PPC64LE-NEXT: lwarx 6, 0, 3
1755; PPC64LE-NEXT: cmpw 4, 6
1756; PPC64LE-NEXT: bne 0, .LBB102_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1757; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1758; PPC64LE-NEXT: stwcx. 5, 0, 3
1759; PPC64LE-NEXT: bne 0, .LBB102_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1760; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1761; PPC64LE-NEXT: lwsync
1762; PPC64LE-NEXT: blr
1763; PPC64LE-NEXT: .LBB102_4:
1764; PPC64LE-NEXT: stwcx. 6, 0, 3
1765; PPC64LE-NEXT: lwsync
1766; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1767 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1768 ret void
1769}
1770
1771define void @test103(i32* %ptr, i32 %cmp, i32 %val) {
1772; PPC64LE-LABEL: test103:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1773; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1774; PPC64LE-NEXT: lwsync
1775; PPC64LE-NEXT: b .LBB103_2
1776; PPC64LE-NEXT: .p2align 5
1777; PPC64LE-NEXT: .LBB103_1:
1778; PPC64LE-NEXT: stwcx. 5, 0, 3
1779; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1780; PPC64LE-NEXT: .LBB103_2:
1781; PPC64LE-NEXT: lwarx 6, 0, 3
1782; PPC64LE-NEXT: cmpw 4, 6
1783; PPC64LE-NEXT: beq 0, .LBB103_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1784; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1785; PPC64LE-NEXT: stwcx. 6, 0, 3
1786; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1787 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1788 ret void
1789}
1790
1791define void @test104(i32* %ptr, i32 %cmp, i32 %val) {
1792; PPC64LE-LABEL: test104:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1793; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1794; PPC64LE-NEXT: lwsync
1795; PPC64LE-NEXT: b .LBB104_2
1796; PPC64LE-NEXT: .p2align 5
1797; PPC64LE-NEXT: .LBB104_1:
1798; PPC64LE-NEXT: stwcx. 5, 0, 3
1799; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1800; PPC64LE-NEXT: .LBB104_2:
1801; PPC64LE-NEXT: lwarx 6, 0, 3
1802; PPC64LE-NEXT: cmpw 4, 6
1803; PPC64LE-NEXT: beq 0, .LBB104_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1804; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1805; PPC64LE-NEXT: stwcx. 6, 0, 3
1806; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1807 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1808 ret void
1809}
1810
1811define void @test105(i32* %ptr, i32 %cmp, i32 %val) {
1812; PPC64LE-LABEL: test105:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1813; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1814; PPC64LE-NEXT: lwsync
1815; PPC64LE-NEXT: .LBB105_1:
1816; PPC64LE-NEXT: lwarx 6, 0, 3
1817; PPC64LE-NEXT: cmpw 4, 6
1818; PPC64LE-NEXT: bne 0, .LBB105_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1819; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1820; PPC64LE-NEXT: stwcx. 5, 0, 3
1821; PPC64LE-NEXT: bne 0, .LBB105_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1822; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1823; PPC64LE-NEXT: lwsync
1824; PPC64LE-NEXT: blr
1825; PPC64LE-NEXT: .LBB105_4:
1826; PPC64LE-NEXT: stwcx. 6, 0, 3
1827; PPC64LE-NEXT: lwsync
1828; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1829 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1830 ret void
1831}
1832
1833define void @test106(i32* %ptr, i32 %cmp, i32 %val) {
1834; PPC64LE-LABEL: test106:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1835; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1836; PPC64LE-NEXT: lwsync
1837; PPC64LE-NEXT: .LBB106_1:
1838; PPC64LE-NEXT: lwarx 6, 0, 3
1839; PPC64LE-NEXT: cmpw 4, 6
1840; PPC64LE-NEXT: bne 0, .LBB106_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1841; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1842; PPC64LE-NEXT: stwcx. 5, 0, 3
1843; PPC64LE-NEXT: bne 0, .LBB106_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1844; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1845; PPC64LE-NEXT: lwsync
1846; PPC64LE-NEXT: blr
1847; PPC64LE-NEXT: .LBB106_4:
1848; PPC64LE-NEXT: stwcx. 6, 0, 3
1849; PPC64LE-NEXT: lwsync
1850; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1851 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1852 ret void
1853}
1854
1855define void @test107(i32* %ptr, i32 %cmp, i32 %val) {
1856; PPC64LE-LABEL: test107:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1857; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1858; PPC64LE-NEXT: sync
1859; PPC64LE-NEXT: .LBB107_1:
1860; PPC64LE-NEXT: lwarx 6, 0, 3
1861; PPC64LE-NEXT: cmpw 4, 6
1862; PPC64LE-NEXT: bne 0, .LBB107_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1863; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1864; PPC64LE-NEXT: stwcx. 5, 0, 3
1865; PPC64LE-NEXT: bne 0, .LBB107_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1866; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1867; PPC64LE-NEXT: lwsync
1868; PPC64LE-NEXT: blr
1869; PPC64LE-NEXT: .LBB107_4:
1870; PPC64LE-NEXT: stwcx. 6, 0, 3
1871; PPC64LE-NEXT: lwsync
1872; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1873 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1874 ret void
1875}
1876
1877define void @test108(i32* %ptr, i32 %cmp, i32 %val) {
1878; PPC64LE-LABEL: test108:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1879; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1880; PPC64LE-NEXT: sync
1881; PPC64LE-NEXT: .LBB108_1:
1882; PPC64LE-NEXT: lwarx 6, 0, 3
1883; PPC64LE-NEXT: cmpw 4, 6
1884; PPC64LE-NEXT: bne 0, .LBB108_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1885; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1886; PPC64LE-NEXT: stwcx. 5, 0, 3
1887; PPC64LE-NEXT: bne 0, .LBB108_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1888; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1889; PPC64LE-NEXT: lwsync
1890; PPC64LE-NEXT: blr
1891; PPC64LE-NEXT: .LBB108_4:
1892; PPC64LE-NEXT: stwcx. 6, 0, 3
1893; PPC64LE-NEXT: lwsync
1894; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1895 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1896 ret void
1897}
1898
1899define void @test109(i32* %ptr, i32 %cmp, i32 %val) {
1900; PPC64LE-LABEL: test109:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1901; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1902; PPC64LE-NEXT: sync
1903; PPC64LE-NEXT: .LBB109_1:
1904; PPC64LE-NEXT: lwarx 6, 0, 3
1905; PPC64LE-NEXT: cmpw 4, 6
1906; PPC64LE-NEXT: bne 0, .LBB109_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1907; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1908; PPC64LE-NEXT: stwcx. 5, 0, 3
1909; PPC64LE-NEXT: bne 0, .LBB109_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1910; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1911; PPC64LE-NEXT: lwsync
1912; PPC64LE-NEXT: blr
1913; PPC64LE-NEXT: .LBB109_4:
1914; PPC64LE-NEXT: stwcx. 6, 0, 3
1915; PPC64LE-NEXT: lwsync
1916; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1917 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1918 ret void
1919}
1920
1921define void @test110(i64* %ptr, i64 %cmp, i64 %val) {
1922; PPC64LE-LABEL: test110:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1923; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1924; PPC64LE-NEXT: b .LBB110_2
1925; PPC64LE-NEXT: .p2align 5
1926; PPC64LE-NEXT: .LBB110_1:
1927; PPC64LE-NEXT: stdcx. 5, 0, 3
1928; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1929; PPC64LE-NEXT: .LBB110_2:
1930; PPC64LE-NEXT: ldarx 6, 0, 3
1931; PPC64LE-NEXT: cmpd 4, 6
1932; PPC64LE-NEXT: beq 0, .LBB110_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1933; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1934; PPC64LE-NEXT: stdcx. 6, 0, 3
1935; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1936 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1937 ret void
1938}
1939
1940define void @test111(i64* %ptr, i64 %cmp, i64 %val) {
1941; PPC64LE-LABEL: test111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1942; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1943; PPC64LE-NEXT: .LBB111_1:
1944; PPC64LE-NEXT: ldarx 6, 0, 3
1945; PPC64LE-NEXT: cmpd 4, 6
1946; PPC64LE-NEXT: bne 0, .LBB111_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1947; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1948; PPC64LE-NEXT: stdcx. 5, 0, 3
1949; PPC64LE-NEXT: bne 0, .LBB111_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1950; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1951; PPC64LE-NEXT: lwsync
1952; PPC64LE-NEXT: blr
1953; PPC64LE-NEXT: .LBB111_4:
1954; PPC64LE-NEXT: stdcx. 6, 0, 3
1955; PPC64LE-NEXT: lwsync
1956; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1957 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1958 ret void
1959}
1960
1961define void @test112(i64* %ptr, i64 %cmp, i64 %val) {
1962; PPC64LE-LABEL: test112:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1963; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1964; PPC64LE-NEXT: .LBB112_1:
1965; PPC64LE-NEXT: ldarx 6, 0, 3
1966; PPC64LE-NEXT: cmpd 4, 6
1967; PPC64LE-NEXT: bne 0, .LBB112_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1968; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1969; PPC64LE-NEXT: stdcx. 5, 0, 3
1970; PPC64LE-NEXT: bne 0, .LBB112_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1971; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1972; PPC64LE-NEXT: lwsync
1973; PPC64LE-NEXT: blr
1974; PPC64LE-NEXT: .LBB112_4:
1975; PPC64LE-NEXT: stdcx. 6, 0, 3
1976; PPC64LE-NEXT: lwsync
1977; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1978 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1979 ret void
1980}
1981
1982define void @test113(i64* %ptr, i64 %cmp, i64 %val) {
1983; PPC64LE-LABEL: test113:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1984; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1985; PPC64LE-NEXT: lwsync
1986; PPC64LE-NEXT: b .LBB113_2
1987; PPC64LE-NEXT: .p2align 5
1988; PPC64LE-NEXT: .LBB113_1:
1989; PPC64LE-NEXT: stdcx. 5, 0, 3
1990; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1991; PPC64LE-NEXT: .LBB113_2:
1992; PPC64LE-NEXT: ldarx 6, 0, 3
1993; PPC64LE-NEXT: cmpd 4, 6
1994; PPC64LE-NEXT: beq 0, .LBB113_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]1995; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1996; PPC64LE-NEXT: stdcx. 6, 0, 3
1997; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1998 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1999 ret void
2000}
2001
2002define void @test114(i64* %ptr, i64 %cmp, i64 %val) {
2003; PPC64LE-LABEL: test114:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2004; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2005; PPC64LE-NEXT: lwsync
2006; PPC64LE-NEXT: b .LBB114_2
2007; PPC64LE-NEXT: .p2align 5
2008; PPC64LE-NEXT: .LBB114_1:
2009; PPC64LE-NEXT: stdcx. 5, 0, 3
2010; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2011; PPC64LE-NEXT: .LBB114_2:
2012; PPC64LE-NEXT: ldarx 6, 0, 3
2013; PPC64LE-NEXT: cmpd 4, 6
2014; PPC64LE-NEXT: beq 0, .LBB114_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2015; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2016; PPC64LE-NEXT: stdcx. 6, 0, 3
2017; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2018 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2019 ret void
2020}
2021
2022define void @test115(i64* %ptr, i64 %cmp, i64 %val) {
2023; PPC64LE-LABEL: test115:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2024; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2025; PPC64LE-NEXT: lwsync
2026; PPC64LE-NEXT: .LBB115_1:
2027; PPC64LE-NEXT: ldarx 6, 0, 3
2028; PPC64LE-NEXT: cmpd 4, 6
2029; PPC64LE-NEXT: bne 0, .LBB115_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2030; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2031; PPC64LE-NEXT: stdcx. 5, 0, 3
2032; PPC64LE-NEXT: bne 0, .LBB115_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2033; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2034; PPC64LE-NEXT: lwsync
2035; PPC64LE-NEXT: blr
2036; PPC64LE-NEXT: .LBB115_4:
2037; PPC64LE-NEXT: stdcx. 6, 0, 3
2038; PPC64LE-NEXT: lwsync
2039; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2040 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2041 ret void
2042}
2043
2044define void @test116(i64* %ptr, i64 %cmp, i64 %val) {
2045; PPC64LE-LABEL: test116:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2046; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2047; PPC64LE-NEXT: lwsync
2048; PPC64LE-NEXT: .LBB116_1:
2049; PPC64LE-NEXT: ldarx 6, 0, 3
2050; PPC64LE-NEXT: cmpd 4, 6
2051; PPC64LE-NEXT: bne 0, .LBB116_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2052; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2053; PPC64LE-NEXT: stdcx. 5, 0, 3
2054; PPC64LE-NEXT: bne 0, .LBB116_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2055; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2056; PPC64LE-NEXT: lwsync
2057; PPC64LE-NEXT: blr
2058; PPC64LE-NEXT: .LBB116_4:
2059; PPC64LE-NEXT: stdcx. 6, 0, 3
2060; PPC64LE-NEXT: lwsync
2061; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2062 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2063 ret void
2064}
2065
2066define void @test117(i64* %ptr, i64 %cmp, i64 %val) {
2067; PPC64LE-LABEL: test117:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2068; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2069; PPC64LE-NEXT: sync
2070; PPC64LE-NEXT: .LBB117_1:
2071; PPC64LE-NEXT: ldarx 6, 0, 3
2072; PPC64LE-NEXT: cmpd 4, 6
2073; PPC64LE-NEXT: bne 0, .LBB117_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2074; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2075; PPC64LE-NEXT: stdcx. 5, 0, 3
2076; PPC64LE-NEXT: bne 0, .LBB117_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2077; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2078; PPC64LE-NEXT: lwsync
2079; PPC64LE-NEXT: blr
2080; PPC64LE-NEXT: .LBB117_4:
2081; PPC64LE-NEXT: stdcx. 6, 0, 3
2082; PPC64LE-NEXT: lwsync
2083; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2084 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2085 ret void
2086}
2087
2088define void @test118(i64* %ptr, i64 %cmp, i64 %val) {
2089; PPC64LE-LABEL: test118:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2090; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2091; PPC64LE-NEXT: sync
2092; PPC64LE-NEXT: .LBB118_1:
2093; PPC64LE-NEXT: ldarx 6, 0, 3
2094; PPC64LE-NEXT: cmpd 4, 6
2095; PPC64LE-NEXT: bne 0, .LBB118_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2096; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2097; PPC64LE-NEXT: stdcx. 5, 0, 3
2098; PPC64LE-NEXT: bne 0, .LBB118_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2099; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2100; PPC64LE-NEXT: lwsync
2101; PPC64LE-NEXT: blr
2102; PPC64LE-NEXT: .LBB118_4:
2103; PPC64LE-NEXT: stdcx. 6, 0, 3
2104; PPC64LE-NEXT: lwsync
2105; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2106 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2107 ret void
2108}
2109
2110define void @test119(i64* %ptr, i64 %cmp, i64 %val) {
2111; PPC64LE-LABEL: test119:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2112; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2113; PPC64LE-NEXT: sync
2114; PPC64LE-NEXT: .LBB119_1:
2115; PPC64LE-NEXT: ldarx 6, 0, 3
2116; PPC64LE-NEXT: cmpd 4, 6
2117; PPC64LE-NEXT: bne 0, .LBB119_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2118; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2119; PPC64LE-NEXT: stdcx. 5, 0, 3
2120; PPC64LE-NEXT: bne 0, .LBB119_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2121; PPC64LE-NEXT: # %bb.3:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2122; PPC64LE-NEXT: lwsync
2123; PPC64LE-NEXT: blr
2124; PPC64LE-NEXT: .LBB119_4:
2125; PPC64LE-NEXT: stdcx. 6, 0, 3
2126; PPC64LE-NEXT: lwsync
2127; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2128 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2129 ret void
2130}
2131
2132define i8 @test120(i8* %ptr, i8 %val) {
2133; PPC64LE-LABEL: test120:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2134; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2135; PPC64LE-NEXT: .LBB120_1:
2136; PPC64LE-NEXT: lbarx 5, 0, 3
2137; PPC64LE-NEXT: stbcx. 4, 0, 3
2138; PPC64LE-NEXT: bne 0, .LBB120_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2139; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2140; PPC64LE-NEXT: mr 3, 5
2141; PPC64LE-NEXT: blr
2142 %ret = atomicrmw xchg i8* %ptr, i8 %val monotonic
2143 ret i8 %ret
2144}
2145
2146define i8 @test121(i8* %ptr, i8 %val) {
2147; PPC64LE-LABEL: test121:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2148; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2149; PPC64LE-NEXT: mr 5, 3
2150; PPC64LE-NEXT: .LBB121_1:
2151; PPC64LE-NEXT: lbarx 3, 0, 5
2152; PPC64LE-NEXT: stbcx. 4, 0, 5
2153; PPC64LE-NEXT: bne 0, .LBB121_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2154; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2155; PPC64LE-NEXT: lwsync
2156; PPC64LE-NEXT: blr
2157 %ret = atomicrmw xchg i8* %ptr, i8 %val acquire
2158 ret i8 %ret
2159}
2160
2161define i8 @test122(i8* %ptr, i8 %val) {
2162; PPC64LE-LABEL: test122:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2163; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2164; PPC64LE-NEXT: lwsync
2165; PPC64LE-NEXT: .LBB122_1:
2166; PPC64LE-NEXT: lbarx 5, 0, 3
2167; PPC64LE-NEXT: stbcx. 4, 0, 3
2168; PPC64LE-NEXT: bne 0, .LBB122_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2169; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2170; PPC64LE-NEXT: mr 3, 5
2171; PPC64LE-NEXT: blr
2172 %ret = atomicrmw xchg i8* %ptr, i8 %val release
2173 ret i8 %ret
2174}
2175
2176define i8 @test123(i8* %ptr, i8 %val) {
2177; PPC64LE-LABEL: test123:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2178; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2179; PPC64LE-NEXT: lwsync
2180; PPC64LE-NEXT: .LBB123_1:
2181; PPC64LE-NEXT: lbarx 5, 0, 3
2182; PPC64LE-NEXT: stbcx. 4, 0, 3
2183; PPC64LE-NEXT: bne 0, .LBB123_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2184; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2185; PPC64LE-NEXT: mr 3, 5
2186; PPC64LE-NEXT: lwsync
2187; PPC64LE-NEXT: blr
2188 %ret = atomicrmw xchg i8* %ptr, i8 %val acq_rel
2189 ret i8 %ret
2190}
2191
2192define i8 @test124(i8* %ptr, i8 %val) {
2193; PPC64LE-LABEL: test124:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2194; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2195; PPC64LE-NEXT: sync
2196; PPC64LE-NEXT: .LBB124_1:
2197; PPC64LE-NEXT: lbarx 5, 0, 3
2198; PPC64LE-NEXT: stbcx. 4, 0, 3
2199; PPC64LE-NEXT: bne 0, .LBB124_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2200; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2201; PPC64LE-NEXT: mr 3, 5
2202; PPC64LE-NEXT: lwsync
2203; PPC64LE-NEXT: blr
2204 %ret = atomicrmw xchg i8* %ptr, i8 %val seq_cst
2205 ret i8 %ret
2206}
2207
2208define i16 @test125(i16* %ptr, i16 %val) {
2209; PPC64LE-LABEL: test125:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2210; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2211; PPC64LE-NEXT: .LBB125_1:
2212; PPC64LE-NEXT: lharx 5, 0, 3
2213; PPC64LE-NEXT: sthcx. 4, 0, 3
2214; PPC64LE-NEXT: bne 0, .LBB125_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2215; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2216; PPC64LE-NEXT: mr 3, 5
2217; PPC64LE-NEXT: blr
2218 %ret = atomicrmw xchg i16* %ptr, i16 %val monotonic
2219 ret i16 %ret
2220}
2221
2222define i16 @test126(i16* %ptr, i16 %val) {
2223; PPC64LE-LABEL: test126:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2224; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2225; PPC64LE-NEXT: mr 5, 3
2226; PPC64LE-NEXT: .LBB126_1:
2227; PPC64LE-NEXT: lharx 3, 0, 5
2228; PPC64LE-NEXT: sthcx. 4, 0, 5
2229; PPC64LE-NEXT: bne 0, .LBB126_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2230; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2231; PPC64LE-NEXT: lwsync
2232; PPC64LE-NEXT: blr
2233 %ret = atomicrmw xchg i16* %ptr, i16 %val acquire
2234 ret i16 %ret
2235}
2236
2237define i16 @test127(i16* %ptr, i16 %val) {
2238; PPC64LE-LABEL: test127:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2239; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2240; PPC64LE-NEXT: lwsync
2241; PPC64LE-NEXT: .LBB127_1:
2242; PPC64LE-NEXT: lharx 5, 0, 3
2243; PPC64LE-NEXT: sthcx. 4, 0, 3
2244; PPC64LE-NEXT: bne 0, .LBB127_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2245; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2246; PPC64LE-NEXT: mr 3, 5
2247; PPC64LE-NEXT: blr
2248 %ret = atomicrmw xchg i16* %ptr, i16 %val release
2249 ret i16 %ret
2250}
2251
2252define i16 @test128(i16* %ptr, i16 %val) {
2253; PPC64LE-LABEL: test128:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2254; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2255; PPC64LE-NEXT: lwsync
2256; PPC64LE-NEXT: .LBB128_1:
2257; PPC64LE-NEXT: lharx 5, 0, 3
2258; PPC64LE-NEXT: sthcx. 4, 0, 3
2259; PPC64LE-NEXT: bne 0, .LBB128_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2260; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2261; PPC64LE-NEXT: mr 3, 5
2262; PPC64LE-NEXT: lwsync
2263; PPC64LE-NEXT: blr
2264 %ret = atomicrmw xchg i16* %ptr, i16 %val acq_rel
2265 ret i16 %ret
2266}
2267
2268define i16 @test129(i16* %ptr, i16 %val) {
2269; PPC64LE-LABEL: test129:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2270; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2271; PPC64LE-NEXT: sync
2272; PPC64LE-NEXT: .LBB129_1:
2273; PPC64LE-NEXT: lharx 5, 0, 3
2274; PPC64LE-NEXT: sthcx. 4, 0, 3
2275; PPC64LE-NEXT: bne 0, .LBB129_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2276; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2277; PPC64LE-NEXT: mr 3, 5
2278; PPC64LE-NEXT: lwsync
2279; PPC64LE-NEXT: blr
2280 %ret = atomicrmw xchg i16* %ptr, i16 %val seq_cst
2281 ret i16 %ret
2282}
2283
2284define i32 @test130(i32* %ptr, i32 %val) {
2285; PPC64LE-LABEL: test130:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2286; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2287; PPC64LE-NEXT: .LBB130_1:
2288; PPC64LE-NEXT: lwarx 5, 0, 3
2289; PPC64LE-NEXT: stwcx. 4, 0, 3
2290; PPC64LE-NEXT: bne 0, .LBB130_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2291; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2292; PPC64LE-NEXT: mr 3, 5
2293; PPC64LE-NEXT: blr
2294 %ret = atomicrmw xchg i32* %ptr, i32 %val monotonic
2295 ret i32 %ret
2296}
2297
2298define i32 @test131(i32* %ptr, i32 %val) {
2299; PPC64LE-LABEL: test131:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2300; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2301; PPC64LE-NEXT: mr 5, 3
2302; PPC64LE-NEXT: .LBB131_1:
2303; PPC64LE-NEXT: lwarx 3, 0, 5
2304; PPC64LE-NEXT: stwcx. 4, 0, 5
2305; PPC64LE-NEXT: bne 0, .LBB131_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2306; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2307; PPC64LE-NEXT: lwsync
2308; PPC64LE-NEXT: blr
2309 %ret = atomicrmw xchg i32* %ptr, i32 %val acquire
2310 ret i32 %ret
2311}
2312
2313define i32 @test132(i32* %ptr, i32 %val) {
2314; PPC64LE-LABEL: test132:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2315; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2316; PPC64LE-NEXT: lwsync
2317; PPC64LE-NEXT: .LBB132_1:
2318; PPC64LE-NEXT: lwarx 5, 0, 3
2319; PPC64LE-NEXT: stwcx. 4, 0, 3
2320; PPC64LE-NEXT: bne 0, .LBB132_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2321; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2322; PPC64LE-NEXT: mr 3, 5
2323; PPC64LE-NEXT: blr
2324 %ret = atomicrmw xchg i32* %ptr, i32 %val release
2325 ret i32 %ret
2326}
2327
2328define i32 @test133(i32* %ptr, i32 %val) {
2329; PPC64LE-LABEL: test133:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2330; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2331; PPC64LE-NEXT: lwsync
2332; PPC64LE-NEXT: .LBB133_1:
2333; PPC64LE-NEXT: lwarx 5, 0, 3
2334; PPC64LE-NEXT: stwcx. 4, 0, 3
2335; PPC64LE-NEXT: bne 0, .LBB133_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2336; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2337; PPC64LE-NEXT: mr 3, 5
2338; PPC64LE-NEXT: lwsync
2339; PPC64LE-NEXT: blr
2340 %ret = atomicrmw xchg i32* %ptr, i32 %val acq_rel
2341 ret i32 %ret
2342}
2343
2344define i32 @test134(i32* %ptr, i32 %val) {
2345; PPC64LE-LABEL: test134:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2346; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2347; PPC64LE-NEXT: sync
2348; PPC64LE-NEXT: .LBB134_1:
2349; PPC64LE-NEXT: lwarx 5, 0, 3
2350; PPC64LE-NEXT: stwcx. 4, 0, 3
2351; PPC64LE-NEXT: bne 0, .LBB134_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2352; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2353; PPC64LE-NEXT: mr 3, 5
2354; PPC64LE-NEXT: lwsync
2355; PPC64LE-NEXT: blr
2356 %ret = atomicrmw xchg i32* %ptr, i32 %val seq_cst
2357 ret i32 %ret
2358}
2359
2360define i64 @test135(i64* %ptr, i64 %val) {
2361; PPC64LE-LABEL: test135:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2362; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2363; PPC64LE-NEXT: .LBB135_1:
2364; PPC64LE-NEXT: ldarx 5, 0, 3
2365; PPC64LE-NEXT: stdcx. 4, 0, 3
2366; PPC64LE-NEXT: bne 0, .LBB135_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2367; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2368; PPC64LE-NEXT: mr 3, 5
2369; PPC64LE-NEXT: blr
2370 %ret = atomicrmw xchg i64* %ptr, i64 %val monotonic
2371 ret i64 %ret
2372}
2373
2374define i64 @test136(i64* %ptr, i64 %val) {
2375; PPC64LE-LABEL: test136:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2376; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2377; PPC64LE-NEXT: mr 5, 3
2378; PPC64LE-NEXT: .LBB136_1:
2379; PPC64LE-NEXT: ldarx 3, 0, 5
2380; PPC64LE-NEXT: stdcx. 4, 0, 5
2381; PPC64LE-NEXT: bne 0, .LBB136_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2382; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2383; PPC64LE-NEXT: lwsync
2384; PPC64LE-NEXT: blr
2385 %ret = atomicrmw xchg i64* %ptr, i64 %val acquire
2386 ret i64 %ret
2387}
2388
2389define i64 @test137(i64* %ptr, i64 %val) {
2390; PPC64LE-LABEL: test137:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2391; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2392; PPC64LE-NEXT: lwsync
2393; PPC64LE-NEXT: .LBB137_1:
2394; PPC64LE-NEXT: ldarx 5, 0, 3
2395; PPC64LE-NEXT: stdcx. 4, 0, 3
2396; PPC64LE-NEXT: bne 0, .LBB137_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2397; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2398; PPC64LE-NEXT: mr 3, 5
2399; PPC64LE-NEXT: blr
2400 %ret = atomicrmw xchg i64* %ptr, i64 %val release
2401 ret i64 %ret
2402}
2403
2404define i64 @test138(i64* %ptr, i64 %val) {
2405; PPC64LE-LABEL: test138:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2406; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2407; PPC64LE-NEXT: lwsync
2408; PPC64LE-NEXT: .LBB138_1:
2409; PPC64LE-NEXT: ldarx 5, 0, 3
2410; PPC64LE-NEXT: stdcx. 4, 0, 3
2411; PPC64LE-NEXT: bne 0, .LBB138_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2412; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2413; PPC64LE-NEXT: mr 3, 5
2414; PPC64LE-NEXT: lwsync
2415; PPC64LE-NEXT: blr
2416 %ret = atomicrmw xchg i64* %ptr, i64 %val acq_rel
2417 ret i64 %ret
2418}
2419
2420define i64 @test139(i64* %ptr, i64 %val) {
2421; PPC64LE-LABEL: test139:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2422; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2423; PPC64LE-NEXT: sync
2424; PPC64LE-NEXT: .LBB139_1:
2425; PPC64LE-NEXT: ldarx 5, 0, 3
2426; PPC64LE-NEXT: stdcx. 4, 0, 3
2427; PPC64LE-NEXT: bne 0, .LBB139_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2428; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2429; PPC64LE-NEXT: mr 3, 5
2430; PPC64LE-NEXT: lwsync
2431; PPC64LE-NEXT: blr
2432 %ret = atomicrmw xchg i64* %ptr, i64 %val seq_cst
2433 ret i64 %ret
2434}
2435
2436define i8 @test140(i8* %ptr, i8 %val) {
2437; PPC64LE-LABEL: test140:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2438; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2439; PPC64LE-NEXT: .LBB140_1:
2440; PPC64LE-NEXT: lbarx 5, 0, 3
2441; PPC64LE-NEXT: add 6, 4, 5
2442; PPC64LE-NEXT: stbcx. 6, 0, 3
2443; PPC64LE-NEXT: bne 0, .LBB140_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2444; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2445; PPC64LE-NEXT: mr 3, 5
2446; PPC64LE-NEXT: blr
2447 %ret = atomicrmw add i8* %ptr, i8 %val monotonic
2448 ret i8 %ret
2449}
2450
2451define i8 @test141(i8* %ptr, i8 %val) {
2452; PPC64LE-LABEL: test141:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2453; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2454; PPC64LE-NEXT: mr 5, 3
2455; PPC64LE-NEXT: .LBB141_1:
2456; PPC64LE-NEXT: lbarx 3, 0, 5
2457; PPC64LE-NEXT: add 6, 4, 3
2458; PPC64LE-NEXT: stbcx. 6, 0, 5
2459; PPC64LE-NEXT: bne 0, .LBB141_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2460; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2461; PPC64LE-NEXT: lwsync
2462; PPC64LE-NEXT: blr
2463 %ret = atomicrmw add i8* %ptr, i8 %val acquire
2464 ret i8 %ret
2465}
2466
2467define i8 @test142(i8* %ptr, i8 %val) {
2468; PPC64LE-LABEL: test142:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2469; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2470; PPC64LE-NEXT: lwsync
2471; PPC64LE-NEXT: .LBB142_1:
2472; PPC64LE-NEXT: lbarx 5, 0, 3
2473; PPC64LE-NEXT: add 6, 4, 5
2474; PPC64LE-NEXT: stbcx. 6, 0, 3
2475; PPC64LE-NEXT: bne 0, .LBB142_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2476; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2477; PPC64LE-NEXT: mr 3, 5
2478; PPC64LE-NEXT: blr
2479 %ret = atomicrmw add i8* %ptr, i8 %val release
2480 ret i8 %ret
2481}
2482
2483define i8 @test143(i8* %ptr, i8 %val) {
2484; PPC64LE-LABEL: test143:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2485; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2486; PPC64LE-NEXT: lwsync
2487; PPC64LE-NEXT: .LBB143_1:
2488; PPC64LE-NEXT: lbarx 5, 0, 3
2489; PPC64LE-NEXT: add 6, 4, 5
2490; PPC64LE-NEXT: stbcx. 6, 0, 3
2491; PPC64LE-NEXT: bne 0, .LBB143_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2492; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2493; PPC64LE-NEXT: mr 3, 5
2494; PPC64LE-NEXT: lwsync
2495; PPC64LE-NEXT: blr
2496 %ret = atomicrmw add i8* %ptr, i8 %val acq_rel
2497 ret i8 %ret
2498}
2499
2500define i8 @test144(i8* %ptr, i8 %val) {
2501; PPC64LE-LABEL: test144:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2502; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2503; PPC64LE-NEXT: sync
2504; PPC64LE-NEXT: .LBB144_1:
2505; PPC64LE-NEXT: lbarx 5, 0, 3
2506; PPC64LE-NEXT: add 6, 4, 5
2507; PPC64LE-NEXT: stbcx. 6, 0, 3
2508; PPC64LE-NEXT: bne 0, .LBB144_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2509; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2510; PPC64LE-NEXT: mr 3, 5
2511; PPC64LE-NEXT: lwsync
2512; PPC64LE-NEXT: blr
2513 %ret = atomicrmw add i8* %ptr, i8 %val seq_cst
2514 ret i8 %ret
2515}
2516
2517define i16 @test145(i16* %ptr, i16 %val) {
2518; PPC64LE-LABEL: test145:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2519; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2520; PPC64LE-NEXT: .LBB145_1:
2521; PPC64LE-NEXT: lharx 5, 0, 3
2522; PPC64LE-NEXT: add 6, 4, 5
2523; PPC64LE-NEXT: sthcx. 6, 0, 3
2524; PPC64LE-NEXT: bne 0, .LBB145_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2525; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2526; PPC64LE-NEXT: mr 3, 5
2527; PPC64LE-NEXT: blr
2528 %ret = atomicrmw add i16* %ptr, i16 %val monotonic
2529 ret i16 %ret
2530}
2531
2532define i16 @test146(i16* %ptr, i16 %val) {
2533; PPC64LE-LABEL: test146:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2534; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2535; PPC64LE-NEXT: mr 5, 3
2536; PPC64LE-NEXT: .LBB146_1:
2537; PPC64LE-NEXT: lharx 3, 0, 5
2538; PPC64LE-NEXT: add 6, 4, 3
2539; PPC64LE-NEXT: sthcx. 6, 0, 5
2540; PPC64LE-NEXT: bne 0, .LBB146_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2541; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2542; PPC64LE-NEXT: lwsync
2543; PPC64LE-NEXT: blr
2544 %ret = atomicrmw add i16* %ptr, i16 %val acquire
2545 ret i16 %ret
2546}
2547
2548define i16 @test147(i16* %ptr, i16 %val) {
2549; PPC64LE-LABEL: test147:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2550; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2551; PPC64LE-NEXT: lwsync
2552; PPC64LE-NEXT: .LBB147_1:
2553; PPC64LE-NEXT: lharx 5, 0, 3
2554; PPC64LE-NEXT: add 6, 4, 5
2555; PPC64LE-NEXT: sthcx. 6, 0, 3
2556; PPC64LE-NEXT: bne 0, .LBB147_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2557; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2558; PPC64LE-NEXT: mr 3, 5
2559; PPC64LE-NEXT: blr
2560 %ret = atomicrmw add i16* %ptr, i16 %val release
2561 ret i16 %ret
2562}
2563
2564define i16 @test148(i16* %ptr, i16 %val) {
2565; PPC64LE-LABEL: test148:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2566; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2567; PPC64LE-NEXT: lwsync
2568; PPC64LE-NEXT: .LBB148_1:
2569; PPC64LE-NEXT: lharx 5, 0, 3
2570; PPC64LE-NEXT: add 6, 4, 5
2571; PPC64LE-NEXT: sthcx. 6, 0, 3
2572; PPC64LE-NEXT: bne 0, .LBB148_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2573; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2574; PPC64LE-NEXT: mr 3, 5
2575; PPC64LE-NEXT: lwsync
2576; PPC64LE-NEXT: blr
2577 %ret = atomicrmw add i16* %ptr, i16 %val acq_rel
2578 ret i16 %ret
2579}
2580
2581define i16 @test149(i16* %ptr, i16 %val) {
2582; PPC64LE-LABEL: test149:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2583; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2584; PPC64LE-NEXT: sync
2585; PPC64LE-NEXT: .LBB149_1:
2586; PPC64LE-NEXT: lharx 5, 0, 3
2587; PPC64LE-NEXT: add 6, 4, 5
2588; PPC64LE-NEXT: sthcx. 6, 0, 3
2589; PPC64LE-NEXT: bne 0, .LBB149_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2590; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2591; PPC64LE-NEXT: mr 3, 5
2592; PPC64LE-NEXT: lwsync
2593; PPC64LE-NEXT: blr
2594 %ret = atomicrmw add i16* %ptr, i16 %val seq_cst
2595 ret i16 %ret
2596}
2597
2598define i32 @test150(i32* %ptr, i32 %val) {
2599; PPC64LE-LABEL: test150:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2600; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2601; PPC64LE-NEXT: .LBB150_1:
2602; PPC64LE-NEXT: lwarx 5, 0, 3
2603; PPC64LE-NEXT: add 6, 4, 5
2604; PPC64LE-NEXT: stwcx. 6, 0, 3
2605; PPC64LE-NEXT: bne 0, .LBB150_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2606; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2607; PPC64LE-NEXT: mr 3, 5
2608; PPC64LE-NEXT: blr
2609 %ret = atomicrmw add i32* %ptr, i32 %val monotonic
2610 ret i32 %ret
2611}
2612
2613define i32 @test151(i32* %ptr, i32 %val) {
2614; PPC64LE-LABEL: test151:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2615; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2616; PPC64LE-NEXT: mr 5, 3
2617; PPC64LE-NEXT: .LBB151_1:
2618; PPC64LE-NEXT: lwarx 3, 0, 5
2619; PPC64LE-NEXT: add 6, 4, 3
2620; PPC64LE-NEXT: stwcx. 6, 0, 5
2621; PPC64LE-NEXT: bne 0, .LBB151_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2622; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2623; PPC64LE-NEXT: lwsync
2624; PPC64LE-NEXT: blr
2625 %ret = atomicrmw add i32* %ptr, i32 %val acquire
2626 ret i32 %ret
2627}
2628
2629define i32 @test152(i32* %ptr, i32 %val) {
2630; PPC64LE-LABEL: test152:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2631; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2632; PPC64LE-NEXT: lwsync
2633; PPC64LE-NEXT: .LBB152_1:
2634; PPC64LE-NEXT: lwarx 5, 0, 3
2635; PPC64LE-NEXT: add 6, 4, 5
2636; PPC64LE-NEXT: stwcx. 6, 0, 3
2637; PPC64LE-NEXT: bne 0, .LBB152_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2638; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2639; PPC64LE-NEXT: mr 3, 5
2640; PPC64LE-NEXT: blr
2641 %ret = atomicrmw add i32* %ptr, i32 %val release
2642 ret i32 %ret
2643}
2644
2645define i32 @test153(i32* %ptr, i32 %val) {
2646; PPC64LE-LABEL: test153:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2647; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2648; PPC64LE-NEXT: lwsync
2649; PPC64LE-NEXT: .LBB153_1:
2650; PPC64LE-NEXT: lwarx 5, 0, 3
2651; PPC64LE-NEXT: add 6, 4, 5
2652; PPC64LE-NEXT: stwcx. 6, 0, 3
2653; PPC64LE-NEXT: bne 0, .LBB153_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2654; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2655; PPC64LE-NEXT: mr 3, 5
2656; PPC64LE-NEXT: lwsync
2657; PPC64LE-NEXT: blr
2658 %ret = atomicrmw add i32* %ptr, i32 %val acq_rel
2659 ret i32 %ret
2660}
2661
2662define i32 @test154(i32* %ptr, i32 %val) {
2663; PPC64LE-LABEL: test154:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2664; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2665; PPC64LE-NEXT: sync
2666; PPC64LE-NEXT: .LBB154_1:
2667; PPC64LE-NEXT: lwarx 5, 0, 3
2668; PPC64LE-NEXT: add 6, 4, 5
2669; PPC64LE-NEXT: stwcx. 6, 0, 3
2670; PPC64LE-NEXT: bne 0, .LBB154_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2671; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2672; PPC64LE-NEXT: mr 3, 5
2673; PPC64LE-NEXT: lwsync
2674; PPC64LE-NEXT: blr
2675 %ret = atomicrmw add i32* %ptr, i32 %val seq_cst
2676 ret i32 %ret
2677}
2678
2679define i64 @test155(i64* %ptr, i64 %val) {
2680; PPC64LE-LABEL: test155:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2681; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2682; PPC64LE-NEXT: .LBB155_1:
2683; PPC64LE-NEXT: ldarx 5, 0, 3
2684; PPC64LE-NEXT: add 6, 4, 5
2685; PPC64LE-NEXT: stdcx. 6, 0, 3
2686; PPC64LE-NEXT: bne 0, .LBB155_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2687; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2688; PPC64LE-NEXT: mr 3, 5
2689; PPC64LE-NEXT: blr
2690 %ret = atomicrmw add i64* %ptr, i64 %val monotonic
2691 ret i64 %ret
2692}
2693
2694define i64 @test156(i64* %ptr, i64 %val) {
2695; PPC64LE-LABEL: test156:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2696; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2697; PPC64LE-NEXT: mr 5, 3
2698; PPC64LE-NEXT: .LBB156_1:
2699; PPC64LE-NEXT: ldarx 3, 0, 5
2700; PPC64LE-NEXT: add 6, 4, 3
2701; PPC64LE-NEXT: stdcx. 6, 0, 5
2702; PPC64LE-NEXT: bne 0, .LBB156_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2703; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2704; PPC64LE-NEXT: lwsync
2705; PPC64LE-NEXT: blr
2706 %ret = atomicrmw add i64* %ptr, i64 %val acquire
2707 ret i64 %ret
2708}
2709
2710define i64 @test157(i64* %ptr, i64 %val) {
2711; PPC64LE-LABEL: test157:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2712; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2713; PPC64LE-NEXT: lwsync
2714; PPC64LE-NEXT: .LBB157_1:
2715; PPC64LE-NEXT: ldarx 5, 0, 3
2716; PPC64LE-NEXT: add 6, 4, 5
2717; PPC64LE-NEXT: stdcx. 6, 0, 3
2718; PPC64LE-NEXT: bne 0, .LBB157_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2719; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2720; PPC64LE-NEXT: mr 3, 5
2721; PPC64LE-NEXT: blr
2722 %ret = atomicrmw add i64* %ptr, i64 %val release
2723 ret i64 %ret
2724}
2725
2726define i64 @test158(i64* %ptr, i64 %val) {
2727; PPC64LE-LABEL: test158:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2728; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2729; PPC64LE-NEXT: lwsync
2730; PPC64LE-NEXT: .LBB158_1:
2731; PPC64LE-NEXT: ldarx 5, 0, 3
2732; PPC64LE-NEXT: add 6, 4, 5
2733; PPC64LE-NEXT: stdcx. 6, 0, 3
2734; PPC64LE-NEXT: bne 0, .LBB158_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2735; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2736; PPC64LE-NEXT: mr 3, 5
2737; PPC64LE-NEXT: lwsync
2738; PPC64LE-NEXT: blr
2739 %ret = atomicrmw add i64* %ptr, i64 %val acq_rel
2740 ret i64 %ret
2741}
2742
2743define i64 @test159(i64* %ptr, i64 %val) {
2744; PPC64LE-LABEL: test159:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2745; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2746; PPC64LE-NEXT: sync
2747; PPC64LE-NEXT: .LBB159_1:
2748; PPC64LE-NEXT: ldarx 5, 0, 3
2749; PPC64LE-NEXT: add 6, 4, 5
2750; PPC64LE-NEXT: stdcx. 6, 0, 3
2751; PPC64LE-NEXT: bne 0, .LBB159_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2752; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2753; PPC64LE-NEXT: mr 3, 5
2754; PPC64LE-NEXT: lwsync
2755; PPC64LE-NEXT: blr
2756 %ret = atomicrmw add i64* %ptr, i64 %val seq_cst
2757 ret i64 %ret
2758}
2759
2760define i8 @test160(i8* %ptr, i8 %val) {
2761; PPC64LE-LABEL: test160:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2762; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2763; PPC64LE-NEXT: .LBB160_1:
2764; PPC64LE-NEXT: lbarx 5, 0, 3
2765; PPC64LE-NEXT: subf 6, 4, 5
2766; PPC64LE-NEXT: stbcx. 6, 0, 3
2767; PPC64LE-NEXT: bne 0, .LBB160_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2768; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2769; PPC64LE-NEXT: mr 3, 5
2770; PPC64LE-NEXT: blr
2771 %ret = atomicrmw sub i8* %ptr, i8 %val monotonic
2772 ret i8 %ret
2773}
2774
2775define i8 @test161(i8* %ptr, i8 %val) {
2776; PPC64LE-LABEL: test161:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2777; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2778; PPC64LE-NEXT: mr 5, 3
2779; PPC64LE-NEXT: .LBB161_1:
2780; PPC64LE-NEXT: lbarx 3, 0, 5
2781; PPC64LE-NEXT: subf 6, 4, 3
2782; PPC64LE-NEXT: stbcx. 6, 0, 5
2783; PPC64LE-NEXT: bne 0, .LBB161_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2784; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2785; PPC64LE-NEXT: lwsync
2786; PPC64LE-NEXT: blr
2787 %ret = atomicrmw sub i8* %ptr, i8 %val acquire
2788 ret i8 %ret
2789}
2790
2791define i8 @test162(i8* %ptr, i8 %val) {
2792; PPC64LE-LABEL: test162:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2793; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2794; PPC64LE-NEXT: lwsync
2795; PPC64LE-NEXT: .LBB162_1:
2796; PPC64LE-NEXT: lbarx 5, 0, 3
2797; PPC64LE-NEXT: subf 6, 4, 5
2798; PPC64LE-NEXT: stbcx. 6, 0, 3
2799; PPC64LE-NEXT: bne 0, .LBB162_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2800; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2801; PPC64LE-NEXT: mr 3, 5
2802; PPC64LE-NEXT: blr
2803 %ret = atomicrmw sub i8* %ptr, i8 %val release
2804 ret i8 %ret
2805}
2806
2807define i8 @test163(i8* %ptr, i8 %val) {
2808; PPC64LE-LABEL: test163:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2809; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2810; PPC64LE-NEXT: lwsync
2811; PPC64LE-NEXT: .LBB163_1:
2812; PPC64LE-NEXT: lbarx 5, 0, 3
2813; PPC64LE-NEXT: subf 6, 4, 5
2814; PPC64LE-NEXT: stbcx. 6, 0, 3
2815; PPC64LE-NEXT: bne 0, .LBB163_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2816; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2817; PPC64LE-NEXT: mr 3, 5
2818; PPC64LE-NEXT: lwsync
2819; PPC64LE-NEXT: blr
2820 %ret = atomicrmw sub i8* %ptr, i8 %val acq_rel
2821 ret i8 %ret
2822}
2823
2824define i8 @test164(i8* %ptr, i8 %val) {
2825; PPC64LE-LABEL: test164:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2826; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2827; PPC64LE-NEXT: sync
2828; PPC64LE-NEXT: .LBB164_1:
2829; PPC64LE-NEXT: lbarx 5, 0, 3
2830; PPC64LE-NEXT: subf 6, 4, 5
2831; PPC64LE-NEXT: stbcx. 6, 0, 3
2832; PPC64LE-NEXT: bne 0, .LBB164_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2833; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2834; PPC64LE-NEXT: mr 3, 5
2835; PPC64LE-NEXT: lwsync
2836; PPC64LE-NEXT: blr
2837 %ret = atomicrmw sub i8* %ptr, i8 %val seq_cst
2838 ret i8 %ret
2839}
2840
2841define i16 @test165(i16* %ptr, i16 %val) {
2842; PPC64LE-LABEL: test165:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2843; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2844; PPC64LE-NEXT: .LBB165_1:
2845; PPC64LE-NEXT: lharx 5, 0, 3
2846; PPC64LE-NEXT: subf 6, 4, 5
2847; PPC64LE-NEXT: sthcx. 6, 0, 3
2848; PPC64LE-NEXT: bne 0, .LBB165_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2849; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2850; PPC64LE-NEXT: mr 3, 5
2851; PPC64LE-NEXT: blr
2852 %ret = atomicrmw sub i16* %ptr, i16 %val monotonic
2853 ret i16 %ret
2854}
2855
2856define i16 @test166(i16* %ptr, i16 %val) {
2857; PPC64LE-LABEL: test166:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2858; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2859; PPC64LE-NEXT: mr 5, 3
2860; PPC64LE-NEXT: .LBB166_1:
2861; PPC64LE-NEXT: lharx 3, 0, 5
2862; PPC64LE-NEXT: subf 6, 4, 3
2863; PPC64LE-NEXT: sthcx. 6, 0, 5
2864; PPC64LE-NEXT: bne 0, .LBB166_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2865; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2866; PPC64LE-NEXT: lwsync
2867; PPC64LE-NEXT: blr
2868 %ret = atomicrmw sub i16* %ptr, i16 %val acquire
2869 ret i16 %ret
2870}
2871
2872define i16 @test167(i16* %ptr, i16 %val) {
2873; PPC64LE-LABEL: test167:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2874; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2875; PPC64LE-NEXT: lwsync
2876; PPC64LE-NEXT: .LBB167_1:
2877; PPC64LE-NEXT: lharx 5, 0, 3
2878; PPC64LE-NEXT: subf 6, 4, 5
2879; PPC64LE-NEXT: sthcx. 6, 0, 3
2880; PPC64LE-NEXT: bne 0, .LBB167_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2881; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2882; PPC64LE-NEXT: mr 3, 5
2883; PPC64LE-NEXT: blr
2884 %ret = atomicrmw sub i16* %ptr, i16 %val release
2885 ret i16 %ret
2886}
2887
2888define i16 @test168(i16* %ptr, i16 %val) {
2889; PPC64LE-LABEL: test168:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2890; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2891; PPC64LE-NEXT: lwsync
2892; PPC64LE-NEXT: .LBB168_1:
2893; PPC64LE-NEXT: lharx 5, 0, 3
2894; PPC64LE-NEXT: subf 6, 4, 5
2895; PPC64LE-NEXT: sthcx. 6, 0, 3
2896; PPC64LE-NEXT: bne 0, .LBB168_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2897; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2898; PPC64LE-NEXT: mr 3, 5
2899; PPC64LE-NEXT: lwsync
2900; PPC64LE-NEXT: blr
2901 %ret = atomicrmw sub i16* %ptr, i16 %val acq_rel
2902 ret i16 %ret
2903}
2904
2905define i16 @test169(i16* %ptr, i16 %val) {
2906; PPC64LE-LABEL: test169:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2907; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2908; PPC64LE-NEXT: sync
2909; PPC64LE-NEXT: .LBB169_1:
2910; PPC64LE-NEXT: lharx 5, 0, 3
2911; PPC64LE-NEXT: subf 6, 4, 5
2912; PPC64LE-NEXT: sthcx. 6, 0, 3
2913; PPC64LE-NEXT: bne 0, .LBB169_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2914; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2915; PPC64LE-NEXT: mr 3, 5
2916; PPC64LE-NEXT: lwsync
2917; PPC64LE-NEXT: blr
2918 %ret = atomicrmw sub i16* %ptr, i16 %val seq_cst
2919 ret i16 %ret
2920}
2921
2922define i32 @test170(i32* %ptr, i32 %val) {
2923; PPC64LE-LABEL: test170:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2924; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2925; PPC64LE-NEXT: .LBB170_1:
2926; PPC64LE-NEXT: lwarx 5, 0, 3
2927; PPC64LE-NEXT: subf 6, 4, 5
2928; PPC64LE-NEXT: stwcx. 6, 0, 3
2929; PPC64LE-NEXT: bne 0, .LBB170_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2930; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2931; PPC64LE-NEXT: mr 3, 5
2932; PPC64LE-NEXT: blr
2933 %ret = atomicrmw sub i32* %ptr, i32 %val monotonic
2934 ret i32 %ret
2935}
2936
2937define i32 @test171(i32* %ptr, i32 %val) {
2938; PPC64LE-LABEL: test171:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2939; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2940; PPC64LE-NEXT: mr 5, 3
2941; PPC64LE-NEXT: .LBB171_1:
2942; PPC64LE-NEXT: lwarx 3, 0, 5
2943; PPC64LE-NEXT: subf 6, 4, 3
2944; PPC64LE-NEXT: stwcx. 6, 0, 5
2945; PPC64LE-NEXT: bne 0, .LBB171_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2946; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2947; PPC64LE-NEXT: lwsync
2948; PPC64LE-NEXT: blr
2949 %ret = atomicrmw sub i32* %ptr, i32 %val acquire
2950 ret i32 %ret
2951}
2952
2953define i32 @test172(i32* %ptr, i32 %val) {
2954; PPC64LE-LABEL: test172:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2955; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2956; PPC64LE-NEXT: lwsync
2957; PPC64LE-NEXT: .LBB172_1:
2958; PPC64LE-NEXT: lwarx 5, 0, 3
2959; PPC64LE-NEXT: subf 6, 4, 5
2960; PPC64LE-NEXT: stwcx. 6, 0, 3
2961; PPC64LE-NEXT: bne 0, .LBB172_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2962; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2963; PPC64LE-NEXT: mr 3, 5
2964; PPC64LE-NEXT: blr
2965 %ret = atomicrmw sub i32* %ptr, i32 %val release
2966 ret i32 %ret
2967}
2968
2969define i32 @test173(i32* %ptr, i32 %val) {
2970; PPC64LE-LABEL: test173:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2971; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2972; PPC64LE-NEXT: lwsync
2973; PPC64LE-NEXT: .LBB173_1:
2974; PPC64LE-NEXT: lwarx 5, 0, 3
2975; PPC64LE-NEXT: subf 6, 4, 5
2976; PPC64LE-NEXT: stwcx. 6, 0, 3
2977; PPC64LE-NEXT: bne 0, .LBB173_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2978; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2979; PPC64LE-NEXT: mr 3, 5
2980; PPC64LE-NEXT: lwsync
2981; PPC64LE-NEXT: blr
2982 %ret = atomicrmw sub i32* %ptr, i32 %val acq_rel
2983 ret i32 %ret
2984}
2985
2986define i32 @test174(i32* %ptr, i32 %val) {
2987; PPC64LE-LABEL: test174:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2988; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2989; PPC64LE-NEXT: sync
2990; PPC64LE-NEXT: .LBB174_1:
2991; PPC64LE-NEXT: lwarx 5, 0, 3
2992; PPC64LE-NEXT: subf 6, 4, 5
2993; PPC64LE-NEXT: stwcx. 6, 0, 3
2994; PPC64LE-NEXT: bne 0, .LBB174_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]2995; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2996; PPC64LE-NEXT: mr 3, 5
2997; PPC64LE-NEXT: lwsync
2998; PPC64LE-NEXT: blr
2999 %ret = atomicrmw sub i32* %ptr, i32 %val seq_cst
3000 ret i32 %ret
3001}
3002
3003define i64 @test175(i64* %ptr, i64 %val) {
3004; PPC64LE-LABEL: test175:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3005; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3006; PPC64LE-NEXT: .LBB175_1:
3007; PPC64LE-NEXT: ldarx 5, 0, 3
3008; PPC64LE-NEXT: sub 6, 5, 4
3009; PPC64LE-NEXT: stdcx. 6, 0, 3
3010; PPC64LE-NEXT: bne 0, .LBB175_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3011; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3012; PPC64LE-NEXT: mr 3, 5
3013; PPC64LE-NEXT: blr
3014 %ret = atomicrmw sub i64* %ptr, i64 %val monotonic
3015 ret i64 %ret
3016}
3017
3018define i64 @test176(i64* %ptr, i64 %val) {
3019; PPC64LE-LABEL: test176:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3020; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3021; PPC64LE-NEXT: mr 5, 3
3022; PPC64LE-NEXT: .LBB176_1:
3023; PPC64LE-NEXT: ldarx 3, 0, 5
3024; PPC64LE-NEXT: sub 6, 3, 4
3025; PPC64LE-NEXT: stdcx. 6, 0, 5
3026; PPC64LE-NEXT: bne 0, .LBB176_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3027; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3028; PPC64LE-NEXT: lwsync
3029; PPC64LE-NEXT: blr
3030 %ret = atomicrmw sub i64* %ptr, i64 %val acquire
3031 ret i64 %ret
3032}
3033
3034define i64 @test177(i64* %ptr, i64 %val) {
3035; PPC64LE-LABEL: test177:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3036; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3037; PPC64LE-NEXT: lwsync
3038; PPC64LE-NEXT: .LBB177_1:
3039; PPC64LE-NEXT: ldarx 5, 0, 3
3040; PPC64LE-NEXT: sub 6, 5, 4
3041; PPC64LE-NEXT: stdcx. 6, 0, 3
3042; PPC64LE-NEXT: bne 0, .LBB177_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3043; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3044; PPC64LE-NEXT: mr 3, 5
3045; PPC64LE-NEXT: blr
3046 %ret = atomicrmw sub i64* %ptr, i64 %val release
3047 ret i64 %ret
3048}
3049
3050define i64 @test178(i64* %ptr, i64 %val) {
3051; PPC64LE-LABEL: test178:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3052; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3053; PPC64LE-NEXT: lwsync
3054; PPC64LE-NEXT: .LBB178_1:
3055; PPC64LE-NEXT: ldarx 5, 0, 3
3056; PPC64LE-NEXT: sub 6, 5, 4
3057; PPC64LE-NEXT: stdcx. 6, 0, 3
3058; PPC64LE-NEXT: bne 0, .LBB178_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3059; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3060; PPC64LE-NEXT: mr 3, 5
3061; PPC64LE-NEXT: lwsync
3062; PPC64LE-NEXT: blr
3063 %ret = atomicrmw sub i64* %ptr, i64 %val acq_rel
3064 ret i64 %ret
3065}
3066
3067define i64 @test179(i64* %ptr, i64 %val) {
3068; PPC64LE-LABEL: test179:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3069; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3070; PPC64LE-NEXT: sync
3071; PPC64LE-NEXT: .LBB179_1:
3072; PPC64LE-NEXT: ldarx 5, 0, 3
3073; PPC64LE-NEXT: sub 6, 5, 4
3074; PPC64LE-NEXT: stdcx. 6, 0, 3
3075; PPC64LE-NEXT: bne 0, .LBB179_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3076; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3077; PPC64LE-NEXT: mr 3, 5
3078; PPC64LE-NEXT: lwsync
3079; PPC64LE-NEXT: blr
3080 %ret = atomicrmw sub i64* %ptr, i64 %val seq_cst
3081 ret i64 %ret
3082}
3083
3084define i8 @test180(i8* %ptr, i8 %val) {
3085; PPC64LE-LABEL: test180:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3086; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3087; PPC64LE-NEXT: .LBB180_1:
3088; PPC64LE-NEXT: lbarx 5, 0, 3
3089; PPC64LE-NEXT: and 6, 4, 5
3090; PPC64LE-NEXT: stbcx. 6, 0, 3
3091; PPC64LE-NEXT: bne 0, .LBB180_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3092; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3093; PPC64LE-NEXT: mr 3, 5
3094; PPC64LE-NEXT: blr
3095 %ret = atomicrmw and i8* %ptr, i8 %val monotonic
3096 ret i8 %ret
3097}
3098
3099define i8 @test181(i8* %ptr, i8 %val) {
3100; PPC64LE-LABEL: test181:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3101; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3102; PPC64LE-NEXT: mr 5, 3
3103; PPC64LE-NEXT: .LBB181_1:
3104; PPC64LE-NEXT: lbarx 3, 0, 5
3105; PPC64LE-NEXT: and 6, 4, 3
3106; PPC64LE-NEXT: stbcx. 6, 0, 5
3107; PPC64LE-NEXT: bne 0, .LBB181_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3108; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3109; PPC64LE-NEXT: lwsync
3110; PPC64LE-NEXT: blr
3111 %ret = atomicrmw and i8* %ptr, i8 %val acquire
3112 ret i8 %ret
3113}
3114
3115define i8 @test182(i8* %ptr, i8 %val) {
3116; PPC64LE-LABEL: test182:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3117; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3118; PPC64LE-NEXT: lwsync
3119; PPC64LE-NEXT: .LBB182_1:
3120; PPC64LE-NEXT: lbarx 5, 0, 3
3121; PPC64LE-NEXT: and 6, 4, 5
3122; PPC64LE-NEXT: stbcx. 6, 0, 3
3123; PPC64LE-NEXT: bne 0, .LBB182_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3124; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3125; PPC64LE-NEXT: mr 3, 5
3126; PPC64LE-NEXT: blr
3127 %ret = atomicrmw and i8* %ptr, i8 %val release
3128 ret i8 %ret
3129}
3130
3131define i8 @test183(i8* %ptr, i8 %val) {
3132; PPC64LE-LABEL: test183:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3133; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3134; PPC64LE-NEXT: lwsync
3135; PPC64LE-NEXT: .LBB183_1:
3136; PPC64LE-NEXT: lbarx 5, 0, 3
3137; PPC64LE-NEXT: and 6, 4, 5
3138; PPC64LE-NEXT: stbcx. 6, 0, 3
3139; PPC64LE-NEXT: bne 0, .LBB183_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3140; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3141; PPC64LE-NEXT: mr 3, 5
3142; PPC64LE-NEXT: lwsync
3143; PPC64LE-NEXT: blr
3144 %ret = atomicrmw and i8* %ptr, i8 %val acq_rel
3145 ret i8 %ret
3146}
3147
3148define i8 @test184(i8* %ptr, i8 %val) {
3149; PPC64LE-LABEL: test184:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3150; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3151; PPC64LE-NEXT: sync
3152; PPC64LE-NEXT: .LBB184_1:
3153; PPC64LE-NEXT: lbarx 5, 0, 3
3154; PPC64LE-NEXT: and 6, 4, 5
3155; PPC64LE-NEXT: stbcx. 6, 0, 3
3156; PPC64LE-NEXT: bne 0, .LBB184_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3157; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3158; PPC64LE-NEXT: mr 3, 5
3159; PPC64LE-NEXT: lwsync
3160; PPC64LE-NEXT: blr
3161 %ret = atomicrmw and i8* %ptr, i8 %val seq_cst
3162 ret i8 %ret
3163}
3164
3165define i16 @test185(i16* %ptr, i16 %val) {
3166; PPC64LE-LABEL: test185:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3167; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3168; PPC64LE-NEXT: .LBB185_1:
3169; PPC64LE-NEXT: lharx 5, 0, 3
3170; PPC64LE-NEXT: and 6, 4, 5
3171; PPC64LE-NEXT: sthcx. 6, 0, 3
3172; PPC64LE-NEXT: bne 0, .LBB185_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3173; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3174; PPC64LE-NEXT: mr 3, 5
3175; PPC64LE-NEXT: blr
3176 %ret = atomicrmw and i16* %ptr, i16 %val monotonic
3177 ret i16 %ret
3178}
3179
3180define i16 @test186(i16* %ptr, i16 %val) {
3181; PPC64LE-LABEL: test186:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3182; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3183; PPC64LE-NEXT: mr 5, 3
3184; PPC64LE-NEXT: .LBB186_1:
3185; PPC64LE-NEXT: lharx 3, 0, 5
3186; PPC64LE-NEXT: and 6, 4, 3
3187; PPC64LE-NEXT: sthcx. 6, 0, 5
3188; PPC64LE-NEXT: bne 0, .LBB186_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3189; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3190; PPC64LE-NEXT: lwsync
3191; PPC64LE-NEXT: blr
3192 %ret = atomicrmw and i16* %ptr, i16 %val acquire
3193 ret i16 %ret
3194}
3195
3196define i16 @test187(i16* %ptr, i16 %val) {
3197; PPC64LE-LABEL: test187:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3198; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3199; PPC64LE-NEXT: lwsync
3200; PPC64LE-NEXT: .LBB187_1:
3201; PPC64LE-NEXT: lharx 5, 0, 3
3202; PPC64LE-NEXT: and 6, 4, 5
3203; PPC64LE-NEXT: sthcx. 6, 0, 3
3204; PPC64LE-NEXT: bne 0, .LBB187_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3205; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3206; PPC64LE-NEXT: mr 3, 5
3207; PPC64LE-NEXT: blr
3208 %ret = atomicrmw and i16* %ptr, i16 %val release
3209 ret i16 %ret
3210}
3211
3212define i16 @test188(i16* %ptr, i16 %val) {
3213; PPC64LE-LABEL: test188:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3214; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3215; PPC64LE-NEXT: lwsync
3216; PPC64LE-NEXT: .LBB188_1:
3217; PPC64LE-NEXT: lharx 5, 0, 3
3218; PPC64LE-NEXT: and 6, 4, 5
3219; PPC64LE-NEXT: sthcx. 6, 0, 3
3220; PPC64LE-NEXT: bne 0, .LBB188_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3221; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3222; PPC64LE-NEXT: mr 3, 5
3223; PPC64LE-NEXT: lwsync
3224; PPC64LE-NEXT: blr
3225 %ret = atomicrmw and i16* %ptr, i16 %val acq_rel
3226 ret i16 %ret
3227}
3228
3229define i16 @test189(i16* %ptr, i16 %val) {
3230; PPC64LE-LABEL: test189:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3231; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3232; PPC64LE-NEXT: sync
3233; PPC64LE-NEXT: .LBB189_1:
3234; PPC64LE-NEXT: lharx 5, 0, 3
3235; PPC64LE-NEXT: and 6, 4, 5
3236; PPC64LE-NEXT: sthcx. 6, 0, 3
3237; PPC64LE-NEXT: bne 0, .LBB189_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3238; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3239; PPC64LE-NEXT: mr 3, 5
3240; PPC64LE-NEXT: lwsync
3241; PPC64LE-NEXT: blr
3242 %ret = atomicrmw and i16* %ptr, i16 %val seq_cst
3243 ret i16 %ret
3244}
3245
3246define i32 @test190(i32* %ptr, i32 %val) {
3247; PPC64LE-LABEL: test190:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3248; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3249; PPC64LE-NEXT: .LBB190_1:
3250; PPC64LE-NEXT: lwarx 5, 0, 3
3251; PPC64LE-NEXT: and 6, 4, 5
3252; PPC64LE-NEXT: stwcx. 6, 0, 3
3253; PPC64LE-NEXT: bne 0, .LBB190_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3254; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3255; PPC64LE-NEXT: mr 3, 5
3256; PPC64LE-NEXT: blr
3257 %ret = atomicrmw and i32* %ptr, i32 %val monotonic
3258 ret i32 %ret
3259}
3260
3261define i32 @test191(i32* %ptr, i32 %val) {
3262; PPC64LE-LABEL: test191:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3263; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3264; PPC64LE-NEXT: mr 5, 3
3265; PPC64LE-NEXT: .LBB191_1:
3266; PPC64LE-NEXT: lwarx 3, 0, 5
3267; PPC64LE-NEXT: and 6, 4, 3
3268; PPC64LE-NEXT: stwcx. 6, 0, 5
3269; PPC64LE-NEXT: bne 0, .LBB191_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3270; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3271; PPC64LE-NEXT: lwsync
3272; PPC64LE-NEXT: blr
3273 %ret = atomicrmw and i32* %ptr, i32 %val acquire
3274 ret i32 %ret
3275}
3276
3277define i32 @test192(i32* %ptr, i32 %val) {
3278; PPC64LE-LABEL: test192:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3279; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3280; PPC64LE-NEXT: lwsync
3281; PPC64LE-NEXT: .LBB192_1:
3282; PPC64LE-NEXT: lwarx 5, 0, 3
3283; PPC64LE-NEXT: and 6, 4, 5
3284; PPC64LE-NEXT: stwcx. 6, 0, 3
3285; PPC64LE-NEXT: bne 0, .LBB192_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3286; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3287; PPC64LE-NEXT: mr 3, 5
3288; PPC64LE-NEXT: blr
3289 %ret = atomicrmw and i32* %ptr, i32 %val release
3290 ret i32 %ret
3291}
3292
3293define i32 @test193(i32* %ptr, i32 %val) {
3294; PPC64LE-LABEL: test193:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3295; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3296; PPC64LE-NEXT: lwsync
3297; PPC64LE-NEXT: .LBB193_1:
3298; PPC64LE-NEXT: lwarx 5, 0, 3
3299; PPC64LE-NEXT: and 6, 4, 5
3300; PPC64LE-NEXT: stwcx. 6, 0, 3
3301; PPC64LE-NEXT: bne 0, .LBB193_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3302; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3303; PPC64LE-NEXT: mr 3, 5
3304; PPC64LE-NEXT: lwsync
3305; PPC64LE-NEXT: blr
3306 %ret = atomicrmw and i32* %ptr, i32 %val acq_rel
3307 ret i32 %ret
3308}
3309
3310define i32 @test194(i32* %ptr, i32 %val) {
3311; PPC64LE-LABEL: test194:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3312; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3313; PPC64LE-NEXT: sync
3314; PPC64LE-NEXT: .LBB194_1:
3315; PPC64LE-NEXT: lwarx 5, 0, 3
3316; PPC64LE-NEXT: and 6, 4, 5
3317; PPC64LE-NEXT: stwcx. 6, 0, 3
3318; PPC64LE-NEXT: bne 0, .LBB194_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3319; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3320; PPC64LE-NEXT: mr 3, 5
3321; PPC64LE-NEXT: lwsync
3322; PPC64LE-NEXT: blr
3323 %ret = atomicrmw and i32* %ptr, i32 %val seq_cst
3324 ret i32 %ret
3325}
3326
3327define i64 @test195(i64* %ptr, i64 %val) {
3328; PPC64LE-LABEL: test195:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3329; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3330; PPC64LE-NEXT: .LBB195_1:
3331; PPC64LE-NEXT: ldarx 5, 0, 3
3332; PPC64LE-NEXT: and 6, 4, 5
3333; PPC64LE-NEXT: stdcx. 6, 0, 3
3334; PPC64LE-NEXT: bne 0, .LBB195_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3335; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3336; PPC64LE-NEXT: mr 3, 5
3337; PPC64LE-NEXT: blr
3338 %ret = atomicrmw and i64* %ptr, i64 %val monotonic
3339 ret i64 %ret
3340}
3341
3342define i64 @test196(i64* %ptr, i64 %val) {
3343; PPC64LE-LABEL: test196:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3344; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3345; PPC64LE-NEXT: mr 5, 3
3346; PPC64LE-NEXT: .LBB196_1:
3347; PPC64LE-NEXT: ldarx 3, 0, 5
3348; PPC64LE-NEXT: and 6, 4, 3
3349; PPC64LE-NEXT: stdcx. 6, 0, 5
3350; PPC64LE-NEXT: bne 0, .LBB196_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3351; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3352; PPC64LE-NEXT: lwsync
3353; PPC64LE-NEXT: blr
3354 %ret = atomicrmw and i64* %ptr, i64 %val acquire
3355 ret i64 %ret
3356}
3357
3358define i64 @test197(i64* %ptr, i64 %val) {
3359; PPC64LE-LABEL: test197:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3360; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3361; PPC64LE-NEXT: lwsync
3362; PPC64LE-NEXT: .LBB197_1:
3363; PPC64LE-NEXT: ldarx 5, 0, 3
3364; PPC64LE-NEXT: and 6, 4, 5
3365; PPC64LE-NEXT: stdcx. 6, 0, 3
3366; PPC64LE-NEXT: bne 0, .LBB197_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3367; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3368; PPC64LE-NEXT: mr 3, 5
3369; PPC64LE-NEXT: blr
3370 %ret = atomicrmw and i64* %ptr, i64 %val release
3371 ret i64 %ret
3372}
3373
3374define i64 @test198(i64* %ptr, i64 %val) {
3375; PPC64LE-LABEL: test198:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3376; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3377; PPC64LE-NEXT: lwsync
3378; PPC64LE-NEXT: .LBB198_1:
3379; PPC64LE-NEXT: ldarx 5, 0, 3
3380; PPC64LE-NEXT: and 6, 4, 5
3381; PPC64LE-NEXT: stdcx. 6, 0, 3
3382; PPC64LE-NEXT: bne 0, .LBB198_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3383; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3384; PPC64LE-NEXT: mr 3, 5
3385; PPC64LE-NEXT: lwsync
3386; PPC64LE-NEXT: blr
3387 %ret = atomicrmw and i64* %ptr, i64 %val acq_rel
3388 ret i64 %ret
3389}
3390
3391define i64 @test199(i64* %ptr, i64 %val) {
3392; PPC64LE-LABEL: test199:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3393; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3394; PPC64LE-NEXT: sync
3395; PPC64LE-NEXT: .LBB199_1:
3396; PPC64LE-NEXT: ldarx 5, 0, 3
3397; PPC64LE-NEXT: and 6, 4, 5
3398; PPC64LE-NEXT: stdcx. 6, 0, 3
3399; PPC64LE-NEXT: bne 0, .LBB199_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3400; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3401; PPC64LE-NEXT: mr 3, 5
3402; PPC64LE-NEXT: lwsync
3403; PPC64LE-NEXT: blr
3404 %ret = atomicrmw and i64* %ptr, i64 %val seq_cst
3405 ret i64 %ret
3406}
3407
3408define i8 @test200(i8* %ptr, i8 %val) {
3409; PPC64LE-LABEL: test200:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3410; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3411; PPC64LE-NEXT: .LBB200_1:
3412; PPC64LE-NEXT: lbarx 5, 0, 3
3413; PPC64LE-NEXT: nand 6, 4, 5
3414; PPC64LE-NEXT: stbcx. 6, 0, 3
3415; PPC64LE-NEXT: bne 0, .LBB200_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3416; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3417; PPC64LE-NEXT: mr 3, 5
3418; PPC64LE-NEXT: blr
3419 %ret = atomicrmw nand i8* %ptr, i8 %val monotonic
3420 ret i8 %ret
3421}
3422
3423define i8 @test201(i8* %ptr, i8 %val) {
3424; PPC64LE-LABEL: test201:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3425; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3426; PPC64LE-NEXT: mr 5, 3
3427; PPC64LE-NEXT: .LBB201_1:
3428; PPC64LE-NEXT: lbarx 3, 0, 5
3429; PPC64LE-NEXT: nand 6, 4, 3
3430; PPC64LE-NEXT: stbcx. 6, 0, 5
3431; PPC64LE-NEXT: bne 0, .LBB201_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3432; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3433; PPC64LE-NEXT: lwsync
3434; PPC64LE-NEXT: blr
3435 %ret = atomicrmw nand i8* %ptr, i8 %val acquire
3436 ret i8 %ret
3437}
3438
3439define i8 @test202(i8* %ptr, i8 %val) {
3440; PPC64LE-LABEL: test202:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3441; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3442; PPC64LE-NEXT: lwsync
3443; PPC64LE-NEXT: .LBB202_1:
3444; PPC64LE-NEXT: lbarx 5, 0, 3
3445; PPC64LE-NEXT: nand 6, 4, 5
3446; PPC64LE-NEXT: stbcx. 6, 0, 3
3447; PPC64LE-NEXT: bne 0, .LBB202_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3448; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3449; PPC64LE-NEXT: mr 3, 5
3450; PPC64LE-NEXT: blr
3451 %ret = atomicrmw nand i8* %ptr, i8 %val release
3452 ret i8 %ret
3453}
3454
3455define i8 @test203(i8* %ptr, i8 %val) {
3456; PPC64LE-LABEL: test203:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3457; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3458; PPC64LE-NEXT: lwsync
3459; PPC64LE-NEXT: .LBB203_1:
3460; PPC64LE-NEXT: lbarx 5, 0, 3
3461; PPC64LE-NEXT: nand 6, 4, 5
3462; PPC64LE-NEXT: stbcx. 6, 0, 3
3463; PPC64LE-NEXT: bne 0, .LBB203_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3464; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3465; PPC64LE-NEXT: mr 3, 5
3466; PPC64LE-NEXT: lwsync
3467; PPC64LE-NEXT: blr
3468 %ret = atomicrmw nand i8* %ptr, i8 %val acq_rel
3469 ret i8 %ret
3470}
3471
3472define i8 @test204(i8* %ptr, i8 %val) {
3473; PPC64LE-LABEL: test204:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3474; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3475; PPC64LE-NEXT: sync
3476; PPC64LE-NEXT: .LBB204_1:
3477; PPC64LE-NEXT: lbarx 5, 0, 3
3478; PPC64LE-NEXT: nand 6, 4, 5
3479; PPC64LE-NEXT: stbcx. 6, 0, 3
3480; PPC64LE-NEXT: bne 0, .LBB204_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3481; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3482; PPC64LE-NEXT: mr 3, 5
3483; PPC64LE-NEXT: lwsync
3484; PPC64LE-NEXT: blr
3485 %ret = atomicrmw nand i8* %ptr, i8 %val seq_cst
3486 ret i8 %ret
3487}
3488
3489define i16 @test205(i16* %ptr, i16 %val) {
3490; PPC64LE-LABEL: test205:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3491; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3492; PPC64LE-NEXT: .LBB205_1:
3493; PPC64LE-NEXT: lharx 5, 0, 3
3494; PPC64LE-NEXT: nand 6, 4, 5
3495; PPC64LE-NEXT: sthcx. 6, 0, 3
3496; PPC64LE-NEXT: bne 0, .LBB205_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3497; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3498; PPC64LE-NEXT: mr 3, 5
3499; PPC64LE-NEXT: blr
3500 %ret = atomicrmw nand i16* %ptr, i16 %val monotonic
3501 ret i16 %ret
3502}
3503
3504define i16 @test206(i16* %ptr, i16 %val) {
3505; PPC64LE-LABEL: test206:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3506; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3507; PPC64LE-NEXT: mr 5, 3
3508; PPC64LE-NEXT: .LBB206_1:
3509; PPC64LE-NEXT: lharx 3, 0, 5
3510; PPC64LE-NEXT: nand 6, 4, 3
3511; PPC64LE-NEXT: sthcx. 6, 0, 5
3512; PPC64LE-NEXT: bne 0, .LBB206_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3513; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3514; PPC64LE-NEXT: lwsync
3515; PPC64LE-NEXT: blr
3516 %ret = atomicrmw nand i16* %ptr, i16 %val acquire
3517 ret i16 %ret
3518}
3519
3520define i16 @test207(i16* %ptr, i16 %val) {
3521; PPC64LE-LABEL: test207:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3522; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3523; PPC64LE-NEXT: lwsync
3524; PPC64LE-NEXT: .LBB207_1:
3525; PPC64LE-NEXT: lharx 5, 0, 3
3526; PPC64LE-NEXT: nand 6, 4, 5
3527; PPC64LE-NEXT: sthcx. 6, 0, 3
3528; PPC64LE-NEXT: bne 0, .LBB207_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3529; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3530; PPC64LE-NEXT: mr 3, 5
3531; PPC64LE-NEXT: blr
3532 %ret = atomicrmw nand i16* %ptr, i16 %val release
3533 ret i16 %ret
3534}
3535
3536define i16 @test208(i16* %ptr, i16 %val) {
3537; PPC64LE-LABEL: test208:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3538; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3539; PPC64LE-NEXT: lwsync
3540; PPC64LE-NEXT: .LBB208_1:
3541; PPC64LE-NEXT: lharx 5, 0, 3
3542; PPC64LE-NEXT: nand 6, 4, 5
3543; PPC64LE-NEXT: sthcx. 6, 0, 3
3544; PPC64LE-NEXT: bne 0, .LBB208_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3545; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3546; PPC64LE-NEXT: mr 3, 5
3547; PPC64LE-NEXT: lwsync
3548; PPC64LE-NEXT: blr
3549 %ret = atomicrmw nand i16* %ptr, i16 %val acq_rel
3550 ret i16 %ret
3551}
3552
3553define i16 @test209(i16* %ptr, i16 %val) {
3554; PPC64LE-LABEL: test209:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3555; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3556; PPC64LE-NEXT: sync
3557; PPC64LE-NEXT: .LBB209_1:
3558; PPC64LE-NEXT: lharx 5, 0, 3
3559; PPC64LE-NEXT: nand 6, 4, 5
3560; PPC64LE-NEXT: sthcx. 6, 0, 3
3561; PPC64LE-NEXT: bne 0, .LBB209_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3562; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3563; PPC64LE-NEXT: mr 3, 5
3564; PPC64LE-NEXT: lwsync
3565; PPC64LE-NEXT: blr
3566 %ret = atomicrmw nand i16* %ptr, i16 %val seq_cst
3567 ret i16 %ret
3568}
3569
3570define i32 @test210(i32* %ptr, i32 %val) {
3571; PPC64LE-LABEL: test210:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3572; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3573; PPC64LE-NEXT: .LBB210_1:
3574; PPC64LE-NEXT: lwarx 5, 0, 3
3575; PPC64LE-NEXT: nand 6, 4, 5
3576; PPC64LE-NEXT: stwcx. 6, 0, 3
3577; PPC64LE-NEXT: bne 0, .LBB210_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3578; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3579; PPC64LE-NEXT: mr 3, 5
3580; PPC64LE-NEXT: blr
3581 %ret = atomicrmw nand i32* %ptr, i32 %val monotonic
3582 ret i32 %ret
3583}
3584
3585define i32 @test211(i32* %ptr, i32 %val) {
3586; PPC64LE-LABEL: test211:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3587; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3588; PPC64LE-NEXT: mr 5, 3
3589; PPC64LE-NEXT: .LBB211_1:
3590; PPC64LE-NEXT: lwarx 3, 0, 5
3591; PPC64LE-NEXT: nand 6, 4, 3
3592; PPC64LE-NEXT: stwcx. 6, 0, 5
3593; PPC64LE-NEXT: bne 0, .LBB211_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3594; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3595; PPC64LE-NEXT: lwsync
3596; PPC64LE-NEXT: blr
3597 %ret = atomicrmw nand i32* %ptr, i32 %val acquire
3598 ret i32 %ret
3599}
3600
3601define i32 @test212(i32* %ptr, i32 %val) {
3602; PPC64LE-LABEL: test212:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3603; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3604; PPC64LE-NEXT: lwsync
3605; PPC64LE-NEXT: .LBB212_1:
3606; PPC64LE-NEXT: lwarx 5, 0, 3
3607; PPC64LE-NEXT: nand 6, 4, 5
3608; PPC64LE-NEXT: stwcx. 6, 0, 3
3609; PPC64LE-NEXT: bne 0, .LBB212_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3610; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3611; PPC64LE-NEXT: mr 3, 5
3612; PPC64LE-NEXT: blr
3613 %ret = atomicrmw nand i32* %ptr, i32 %val release
3614 ret i32 %ret
3615}
3616
3617define i32 @test213(i32* %ptr, i32 %val) {
3618; PPC64LE-LABEL: test213:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3619; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3620; PPC64LE-NEXT: lwsync
3621; PPC64LE-NEXT: .LBB213_1:
3622; PPC64LE-NEXT: lwarx 5, 0, 3
3623; PPC64LE-NEXT: nand 6, 4, 5
3624; PPC64LE-NEXT: stwcx. 6, 0, 3
3625; PPC64LE-NEXT: bne 0, .LBB213_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3626; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3627; PPC64LE-NEXT: mr 3, 5
3628; PPC64LE-NEXT: lwsync
3629; PPC64LE-NEXT: blr
3630 %ret = atomicrmw nand i32* %ptr, i32 %val acq_rel
3631 ret i32 %ret
3632}
3633
3634define i32 @test214(i32* %ptr, i32 %val) {
3635; PPC64LE-LABEL: test214:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3636; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3637; PPC64LE-NEXT: sync
3638; PPC64LE-NEXT: .LBB214_1:
3639; PPC64LE-NEXT: lwarx 5, 0, 3
3640; PPC64LE-NEXT: nand 6, 4, 5
3641; PPC64LE-NEXT: stwcx. 6, 0, 3
3642; PPC64LE-NEXT: bne 0, .LBB214_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3643; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3644; PPC64LE-NEXT: mr 3, 5
3645; PPC64LE-NEXT: lwsync
3646; PPC64LE-NEXT: blr
3647 %ret = atomicrmw nand i32* %ptr, i32 %val seq_cst
3648 ret i32 %ret
3649}
3650
3651define i64 @test215(i64* %ptr, i64 %val) {
3652; PPC64LE-LABEL: test215:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3653; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3654; PPC64LE-NEXT: .LBB215_1:
3655; PPC64LE-NEXT: ldarx 5, 0, 3
3656; PPC64LE-NEXT: nand 6, 4, 5
3657; PPC64LE-NEXT: stdcx. 6, 0, 3
3658; PPC64LE-NEXT: bne 0, .LBB215_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3659; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3660; PPC64LE-NEXT: mr 3, 5
3661; PPC64LE-NEXT: blr
3662 %ret = atomicrmw nand i64* %ptr, i64 %val monotonic
3663 ret i64 %ret
3664}
3665
3666define i64 @test216(i64* %ptr, i64 %val) {
3667; PPC64LE-LABEL: test216:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3668; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3669; PPC64LE-NEXT: mr 5, 3
3670; PPC64LE-NEXT: .LBB216_1:
3671; PPC64LE-NEXT: ldarx 3, 0, 5
3672; PPC64LE-NEXT: nand 6, 4, 3
3673; PPC64LE-NEXT: stdcx. 6, 0, 5
3674; PPC64LE-NEXT: bne 0, .LBB216_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3675; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3676; PPC64LE-NEXT: lwsync
3677; PPC64LE-NEXT: blr
3678 %ret = atomicrmw nand i64* %ptr, i64 %val acquire
3679 ret i64 %ret
3680}
3681
3682define i64 @test217(i64* %ptr, i64 %val) {
3683; PPC64LE-LABEL: test217:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3684; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3685; PPC64LE-NEXT: lwsync
3686; PPC64LE-NEXT: .LBB217_1:
3687; PPC64LE-NEXT: ldarx 5, 0, 3
3688; PPC64LE-NEXT: nand 6, 4, 5
3689; PPC64LE-NEXT: stdcx. 6, 0, 3
3690; PPC64LE-NEXT: bne 0, .LBB217_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3691; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3692; PPC64LE-NEXT: mr 3, 5
3693; PPC64LE-NEXT: blr
3694 %ret = atomicrmw nand i64* %ptr, i64 %val release
3695 ret i64 %ret
3696}
3697
3698define i64 @test218(i64* %ptr, i64 %val) {
3699; PPC64LE-LABEL: test218:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3700; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3701; PPC64LE-NEXT: lwsync
3702; PPC64LE-NEXT: .LBB218_1:
3703; PPC64LE-NEXT: ldarx 5, 0, 3
3704; PPC64LE-NEXT: nand 6, 4, 5
3705; PPC64LE-NEXT: stdcx. 6, 0, 3
3706; PPC64LE-NEXT: bne 0, .LBB218_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3707; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3708; PPC64LE-NEXT: mr 3, 5
3709; PPC64LE-NEXT: lwsync
3710; PPC64LE-NEXT: blr
3711 %ret = atomicrmw nand i64* %ptr, i64 %val acq_rel
3712 ret i64 %ret
3713}
3714
3715define i64 @test219(i64* %ptr, i64 %val) {
3716; PPC64LE-LABEL: test219:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3717; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3718; PPC64LE-NEXT: sync
3719; PPC64LE-NEXT: .LBB219_1:
3720; PPC64LE-NEXT: ldarx 5, 0, 3
3721; PPC64LE-NEXT: nand 6, 4, 5
3722; PPC64LE-NEXT: stdcx. 6, 0, 3
3723; PPC64LE-NEXT: bne 0, .LBB219_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3724; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3725; PPC64LE-NEXT: mr 3, 5
3726; PPC64LE-NEXT: lwsync
3727; PPC64LE-NEXT: blr
3728 %ret = atomicrmw nand i64* %ptr, i64 %val seq_cst
3729 ret i64 %ret
3730}
3731
3732define i8 @test220(i8* %ptr, i8 %val) {
3733; PPC64LE-LABEL: test220:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3734; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3735; PPC64LE-NEXT: .LBB220_1:
3736; PPC64LE-NEXT: lbarx 5, 0, 3
3737; PPC64LE-NEXT: or 6, 4, 5
3738; PPC64LE-NEXT: stbcx. 6, 0, 3
3739; PPC64LE-NEXT: bne 0, .LBB220_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3740; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3741; PPC64LE-NEXT: mr 3, 5
3742; PPC64LE-NEXT: blr
3743 %ret = atomicrmw or i8* %ptr, i8 %val monotonic
3744 ret i8 %ret
3745}
3746
3747define i8 @test221(i8* %ptr, i8 %val) {
3748; PPC64LE-LABEL: test221:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3749; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3750; PPC64LE-NEXT: mr 5, 3
3751; PPC64LE-NEXT: .LBB221_1:
3752; PPC64LE-NEXT: lbarx 3, 0, 5
3753; PPC64LE-NEXT: or 6, 4, 3
3754; PPC64LE-NEXT: stbcx. 6, 0, 5
3755; PPC64LE-NEXT: bne 0, .LBB221_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3756; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3757; PPC64LE-NEXT: lwsync
3758; PPC64LE-NEXT: blr
3759 %ret = atomicrmw or i8* %ptr, i8 %val acquire
3760 ret i8 %ret
3761}
3762
3763define i8 @test222(i8* %ptr, i8 %val) {
3764; PPC64LE-LABEL: test222:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3765; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3766; PPC64LE-NEXT: lwsync
3767; PPC64LE-NEXT: .LBB222_1:
3768; PPC64LE-NEXT: lbarx 5, 0, 3
3769; PPC64LE-NEXT: or 6, 4, 5
3770; PPC64LE-NEXT: stbcx. 6, 0, 3
3771; PPC64LE-NEXT: bne 0, .LBB222_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3772; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3773; PPC64LE-NEXT: mr 3, 5
3774; PPC64LE-NEXT: blr
3775 %ret = atomicrmw or i8* %ptr, i8 %val release
3776 ret i8 %ret
3777}
3778
3779define i8 @test223(i8* %ptr, i8 %val) {
3780; PPC64LE-LABEL: test223:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3781; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3782; PPC64LE-NEXT: lwsync
3783; PPC64LE-NEXT: .LBB223_1:
3784; PPC64LE-NEXT: lbarx 5, 0, 3
3785; PPC64LE-NEXT: or 6, 4, 5
3786; PPC64LE-NEXT: stbcx. 6, 0, 3
3787; PPC64LE-NEXT: bne 0, .LBB223_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3788; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3789; PPC64LE-NEXT: mr 3, 5
3790; PPC64LE-NEXT: lwsync
3791; PPC64LE-NEXT: blr
3792 %ret = atomicrmw or i8* %ptr, i8 %val acq_rel
3793 ret i8 %ret
3794}
3795
3796define i8 @test224(i8* %ptr, i8 %val) {
3797; PPC64LE-LABEL: test224:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3798; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3799; PPC64LE-NEXT: sync
3800; PPC64LE-NEXT: .LBB224_1:
3801; PPC64LE-NEXT: lbarx 5, 0, 3
3802; PPC64LE-NEXT: or 6, 4, 5
3803; PPC64LE-NEXT: stbcx. 6, 0, 3
3804; PPC64LE-NEXT: bne 0, .LBB224_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3805; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3806; PPC64LE-NEXT: mr 3, 5
3807; PPC64LE-NEXT: lwsync
3808; PPC64LE-NEXT: blr
3809 %ret = atomicrmw or i8* %ptr, i8 %val seq_cst
3810 ret i8 %ret
3811}
3812
3813define i16 @test225(i16* %ptr, i16 %val) {
3814; PPC64LE-LABEL: test225:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3815; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3816; PPC64LE-NEXT: .LBB225_1:
3817; PPC64LE-NEXT: lharx 5, 0, 3
3818; PPC64LE-NEXT: or 6, 4, 5
3819; PPC64LE-NEXT: sthcx. 6, 0, 3
3820; PPC64LE-NEXT: bne 0, .LBB225_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3821; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3822; PPC64LE-NEXT: mr 3, 5
3823; PPC64LE-NEXT: blr
3824 %ret = atomicrmw or i16* %ptr, i16 %val monotonic
3825 ret i16 %ret
3826}
3827
3828define i16 @test226(i16* %ptr, i16 %val) {
3829; PPC64LE-LABEL: test226:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3830; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3831; PPC64LE-NEXT: mr 5, 3
3832; PPC64LE-NEXT: .LBB226_1:
3833; PPC64LE-NEXT: lharx 3, 0, 5
3834; PPC64LE-NEXT: or 6, 4, 3
3835; PPC64LE-NEXT: sthcx. 6, 0, 5
3836; PPC64LE-NEXT: bne 0, .LBB226_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3837; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3838; PPC64LE-NEXT: lwsync
3839; PPC64LE-NEXT: blr
3840 %ret = atomicrmw or i16* %ptr, i16 %val acquire
3841 ret i16 %ret
3842}
3843
3844define i16 @test227(i16* %ptr, i16 %val) {
3845; PPC64LE-LABEL: test227:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3846; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3847; PPC64LE-NEXT: lwsync
3848; PPC64LE-NEXT: .LBB227_1:
3849; PPC64LE-NEXT: lharx 5, 0, 3
3850; PPC64LE-NEXT: or 6, 4, 5
3851; PPC64LE-NEXT: sthcx. 6, 0, 3
3852; PPC64LE-NEXT: bne 0, .LBB227_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3853; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3854; PPC64LE-NEXT: mr 3, 5
3855; PPC64LE-NEXT: blr
3856 %ret = atomicrmw or i16* %ptr, i16 %val release
3857 ret i16 %ret
3858}
3859
3860define i16 @test228(i16* %ptr, i16 %val) {
3861; PPC64LE-LABEL: test228:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3862; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3863; PPC64LE-NEXT: lwsync
3864; PPC64LE-NEXT: .LBB228_1:
3865; PPC64LE-NEXT: lharx 5, 0, 3
3866; PPC64LE-NEXT: or 6, 4, 5
3867; PPC64LE-NEXT: sthcx. 6, 0, 3
3868; PPC64LE-NEXT: bne 0, .LBB228_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3869; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3870; PPC64LE-NEXT: mr 3, 5
3871; PPC64LE-NEXT: lwsync
3872; PPC64LE-NEXT: blr
3873 %ret = atomicrmw or i16* %ptr, i16 %val acq_rel
3874 ret i16 %ret
3875}
3876
3877define i16 @test229(i16* %ptr, i16 %val) {
3878; PPC64LE-LABEL: test229:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3879; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3880; PPC64LE-NEXT: sync
3881; PPC64LE-NEXT: .LBB229_1:
3882; PPC64LE-NEXT: lharx 5, 0, 3
3883; PPC64LE-NEXT: or 6, 4, 5
3884; PPC64LE-NEXT: sthcx. 6, 0, 3
3885; PPC64LE-NEXT: bne 0, .LBB229_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3886; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3887; PPC64LE-NEXT: mr 3, 5
3888; PPC64LE-NEXT: lwsync
3889; PPC64LE-NEXT: blr
3890 %ret = atomicrmw or i16* %ptr, i16 %val seq_cst
3891 ret i16 %ret
3892}
3893
3894define i32 @test230(i32* %ptr, i32 %val) {
3895; PPC64LE-LABEL: test230:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3896; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3897; PPC64LE-NEXT: .LBB230_1:
3898; PPC64LE-NEXT: lwarx 5, 0, 3
3899; PPC64LE-NEXT: or 6, 4, 5
3900; PPC64LE-NEXT: stwcx. 6, 0, 3
3901; PPC64LE-NEXT: bne 0, .LBB230_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3902; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3903; PPC64LE-NEXT: mr 3, 5
3904; PPC64LE-NEXT: blr
3905 %ret = atomicrmw or i32* %ptr, i32 %val monotonic
3906 ret i32 %ret
3907}
3908
3909define i32 @test231(i32* %ptr, i32 %val) {
3910; PPC64LE-LABEL: test231:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3911; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3912; PPC64LE-NEXT: mr 5, 3
3913; PPC64LE-NEXT: .LBB231_1:
3914; PPC64LE-NEXT: lwarx 3, 0, 5
3915; PPC64LE-NEXT: or 6, 4, 3
3916; PPC64LE-NEXT: stwcx. 6, 0, 5
3917; PPC64LE-NEXT: bne 0, .LBB231_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3918; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3919; PPC64LE-NEXT: lwsync
3920; PPC64LE-NEXT: blr
3921 %ret = atomicrmw or i32* %ptr, i32 %val acquire
3922 ret i32 %ret
3923}
3924
3925define i32 @test232(i32* %ptr, i32 %val) {
3926; PPC64LE-LABEL: test232:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3927; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3928; PPC64LE-NEXT: lwsync
3929; PPC64LE-NEXT: .LBB232_1:
3930; PPC64LE-NEXT: lwarx 5, 0, 3
3931; PPC64LE-NEXT: or 6, 4, 5
3932; PPC64LE-NEXT: stwcx. 6, 0, 3
3933; PPC64LE-NEXT: bne 0, .LBB232_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3934; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3935; PPC64LE-NEXT: mr 3, 5
3936; PPC64LE-NEXT: blr
3937 %ret = atomicrmw or i32* %ptr, i32 %val release
3938 ret i32 %ret
3939}
3940
3941define i32 @test233(i32* %ptr, i32 %val) {
3942; PPC64LE-LABEL: test233:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3943; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3944; PPC64LE-NEXT: lwsync
3945; PPC64LE-NEXT: .LBB233_1:
3946; PPC64LE-NEXT: lwarx 5, 0, 3
3947; PPC64LE-NEXT: or 6, 4, 5
3948; PPC64LE-NEXT: stwcx. 6, 0, 3
3949; PPC64LE-NEXT: bne 0, .LBB233_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3950; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3951; PPC64LE-NEXT: mr 3, 5
3952; PPC64LE-NEXT: lwsync
3953; PPC64LE-NEXT: blr
3954 %ret = atomicrmw or i32* %ptr, i32 %val acq_rel
3955 ret i32 %ret
3956}
3957
3958define i32 @test234(i32* %ptr, i32 %val) {
3959; PPC64LE-LABEL: test234:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3960; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3961; PPC64LE-NEXT: sync
3962; PPC64LE-NEXT: .LBB234_1:
3963; PPC64LE-NEXT: lwarx 5, 0, 3
3964; PPC64LE-NEXT: or 6, 4, 5
3965; PPC64LE-NEXT: stwcx. 6, 0, 3
3966; PPC64LE-NEXT: bne 0, .LBB234_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3967; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3968; PPC64LE-NEXT: mr 3, 5
3969; PPC64LE-NEXT: lwsync
3970; PPC64LE-NEXT: blr
3971 %ret = atomicrmw or i32* %ptr, i32 %val seq_cst
3972 ret i32 %ret
3973}
3974
3975define i64 @test235(i64* %ptr, i64 %val) {
3976; PPC64LE-LABEL: test235:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3977; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3978; PPC64LE-NEXT: .LBB235_1:
3979; PPC64LE-NEXT: ldarx 5, 0, 3
3980; PPC64LE-NEXT: or 6, 4, 5
3981; PPC64LE-NEXT: stdcx. 6, 0, 3
3982; PPC64LE-NEXT: bne 0, .LBB235_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3983; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3984; PPC64LE-NEXT: mr 3, 5
3985; PPC64LE-NEXT: blr
3986 %ret = atomicrmw or i64* %ptr, i64 %val monotonic
3987 ret i64 %ret
3988}
3989
3990define i64 @test236(i64* %ptr, i64 %val) {
3991; PPC64LE-LABEL: test236:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3992; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]3993; PPC64LE-NEXT: mr 5, 3
3994; PPC64LE-NEXT: .LBB236_1:
3995; PPC64LE-NEXT: ldarx 3, 0, 5
3996; PPC64LE-NEXT: or 6, 4, 3
3997; PPC64LE-NEXT: stdcx. 6, 0, 5
3998; PPC64LE-NEXT: bne 0, .LBB236_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]3999; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4000; PPC64LE-NEXT: lwsync
4001; PPC64LE-NEXT: blr
4002 %ret = atomicrmw or i64* %ptr, i64 %val acquire
4003 ret i64 %ret
4004}
4005
4006define i64 @test237(i64* %ptr, i64 %val) {
4007; PPC64LE-LABEL: test237:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4008; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4009; PPC64LE-NEXT: lwsync
4010; PPC64LE-NEXT: .LBB237_1:
4011; PPC64LE-NEXT: ldarx 5, 0, 3
4012; PPC64LE-NEXT: or 6, 4, 5
4013; PPC64LE-NEXT: stdcx. 6, 0, 3
4014; PPC64LE-NEXT: bne 0, .LBB237_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4015; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4016; PPC64LE-NEXT: mr 3, 5
4017; PPC64LE-NEXT: blr
4018 %ret = atomicrmw or i64* %ptr, i64 %val release
4019 ret i64 %ret
4020}
4021
4022define i64 @test238(i64* %ptr, i64 %val) {
4023; PPC64LE-LABEL: test238:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4024; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4025; PPC64LE-NEXT: lwsync
4026; PPC64LE-NEXT: .LBB238_1:
4027; PPC64LE-NEXT: ldarx 5, 0, 3
4028; PPC64LE-NEXT: or 6, 4, 5
4029; PPC64LE-NEXT: stdcx. 6, 0, 3
4030; PPC64LE-NEXT: bne 0, .LBB238_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4031; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4032; PPC64LE-NEXT: mr 3, 5
4033; PPC64LE-NEXT: lwsync
4034; PPC64LE-NEXT: blr
4035 %ret = atomicrmw or i64* %ptr, i64 %val acq_rel
4036 ret i64 %ret
4037}
4038
4039define i64 @test239(i64* %ptr, i64 %val) {
4040; PPC64LE-LABEL: test239:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4041; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4042; PPC64LE-NEXT: sync
4043; PPC64LE-NEXT: .LBB239_1:
4044; PPC64LE-NEXT: ldarx 5, 0, 3
4045; PPC64LE-NEXT: or 6, 4, 5
4046; PPC64LE-NEXT: stdcx. 6, 0, 3
4047; PPC64LE-NEXT: bne 0, .LBB239_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4048; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4049; PPC64LE-NEXT: mr 3, 5
4050; PPC64LE-NEXT: lwsync
4051; PPC64LE-NEXT: blr
4052 %ret = atomicrmw or i64* %ptr, i64 %val seq_cst
4053 ret i64 %ret
4054}
4055
4056define i8 @test240(i8* %ptr, i8 %val) {
4057; PPC64LE-LABEL: test240:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4058; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4059; PPC64LE-NEXT: .LBB240_1:
4060; PPC64LE-NEXT: lbarx 5, 0, 3
4061; PPC64LE-NEXT: xor 6, 4, 5
4062; PPC64LE-NEXT: stbcx. 6, 0, 3
4063; PPC64LE-NEXT: bne 0, .LBB240_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4064; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4065; PPC64LE-NEXT: mr 3, 5
4066; PPC64LE-NEXT: blr
4067 %ret = atomicrmw xor i8* %ptr, i8 %val monotonic
4068 ret i8 %ret
4069}
4070
4071define i8 @test241(i8* %ptr, i8 %val) {
4072; PPC64LE-LABEL: test241:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4073; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4074; PPC64LE-NEXT: mr 5, 3
4075; PPC64LE-NEXT: .LBB241_1:
4076; PPC64LE-NEXT: lbarx 3, 0, 5
4077; PPC64LE-NEXT: xor 6, 4, 3
4078; PPC64LE-NEXT: stbcx. 6, 0, 5
4079; PPC64LE-NEXT: bne 0, .LBB241_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4080; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4081; PPC64LE-NEXT: lwsync
4082; PPC64LE-NEXT: blr
4083 %ret = atomicrmw xor i8* %ptr, i8 %val acquire
4084 ret i8 %ret
4085}
4086
4087define i8 @test242(i8* %ptr, i8 %val) {
4088; PPC64LE-LABEL: test242:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4089; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4090; PPC64LE-NEXT: lwsync
4091; PPC64LE-NEXT: .LBB242_1:
4092; PPC64LE-NEXT: lbarx 5, 0, 3
4093; PPC64LE-NEXT: xor 6, 4, 5
4094; PPC64LE-NEXT: stbcx. 6, 0, 3
4095; PPC64LE-NEXT: bne 0, .LBB242_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4096; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4097; PPC64LE-NEXT: mr 3, 5
4098; PPC64LE-NEXT: blr
4099 %ret = atomicrmw xor i8* %ptr, i8 %val release
4100 ret i8 %ret
4101}
4102
4103define i8 @test243(i8* %ptr, i8 %val) {
4104; PPC64LE-LABEL: test243:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4105; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4106; PPC64LE-NEXT: lwsync
4107; PPC64LE-NEXT: .LBB243_1:
4108; PPC64LE-NEXT: lbarx 5, 0, 3
4109; PPC64LE-NEXT: xor 6, 4, 5
4110; PPC64LE-NEXT: stbcx. 6, 0, 3
4111; PPC64LE-NEXT: bne 0, .LBB243_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4112; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4113; PPC64LE-NEXT: mr 3, 5
4114; PPC64LE-NEXT: lwsync
4115; PPC64LE-NEXT: blr
4116 %ret = atomicrmw xor i8* %ptr, i8 %val acq_rel
4117 ret i8 %ret
4118}
4119
4120define i8 @test244(i8* %ptr, i8 %val) {
4121; PPC64LE-LABEL: test244:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4122; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4123; PPC64LE-NEXT: sync
4124; PPC64LE-NEXT: .LBB244_1:
4125; PPC64LE-NEXT: lbarx 5, 0, 3
4126; PPC64LE-NEXT: xor 6, 4, 5
4127; PPC64LE-NEXT: stbcx. 6, 0, 3
4128; PPC64LE-NEXT: bne 0, .LBB244_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4129; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4130; PPC64LE-NEXT: mr 3, 5
4131; PPC64LE-NEXT: lwsync
4132; PPC64LE-NEXT: blr
4133 %ret = atomicrmw xor i8* %ptr, i8 %val seq_cst
4134 ret i8 %ret
4135}
4136
4137define i16 @test245(i16* %ptr, i16 %val) {
4138; PPC64LE-LABEL: test245:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4139; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4140; PPC64LE-NEXT: .LBB245_1:
4141; PPC64LE-NEXT: lharx 5, 0, 3
4142; PPC64LE-NEXT: xor 6, 4, 5
4143; PPC64LE-NEXT: sthcx. 6, 0, 3
4144; PPC64LE-NEXT: bne 0, .LBB245_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4145; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4146; PPC64LE-NEXT: mr 3, 5
4147; PPC64LE-NEXT: blr
4148 %ret = atomicrmw xor i16* %ptr, i16 %val monotonic
4149 ret i16 %ret
4150}
4151
4152define i16 @test246(i16* %ptr, i16 %val) {
4153; PPC64LE-LABEL: test246:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4154; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4155; PPC64LE-NEXT: mr 5, 3
4156; PPC64LE-NEXT: .LBB246_1:
4157; PPC64LE-NEXT: lharx 3, 0, 5
4158; PPC64LE-NEXT: xor 6, 4, 3
4159; PPC64LE-NEXT: sthcx. 6, 0, 5
4160; PPC64LE-NEXT: bne 0, .LBB246_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4161; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4162; PPC64LE-NEXT: lwsync
4163; PPC64LE-NEXT: blr
4164 %ret = atomicrmw xor i16* %ptr, i16 %val acquire
4165 ret i16 %ret
4166}
4167
4168define i16 @test247(i16* %ptr, i16 %val) {
4169; PPC64LE-LABEL: test247:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4170; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4171; PPC64LE-NEXT: lwsync
4172; PPC64LE-NEXT: .LBB247_1:
4173; PPC64LE-NEXT: lharx 5, 0, 3
4174; PPC64LE-NEXT: xor 6, 4, 5
4175; PPC64LE-NEXT: sthcx. 6, 0, 3
4176; PPC64LE-NEXT: bne 0, .LBB247_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4177; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4178; PPC64LE-NEXT: mr 3, 5
4179; PPC64LE-NEXT: blr
4180 %ret = atomicrmw xor i16* %ptr, i16 %val release
4181 ret i16 %ret
4182}
4183
4184define i16 @test248(i16* %ptr, i16 %val) {
4185; PPC64LE-LABEL: test248:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4186; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4187; PPC64LE-NEXT: lwsync
4188; PPC64LE-NEXT: .LBB248_1:
4189; PPC64LE-NEXT: lharx 5, 0, 3
4190; PPC64LE-NEXT: xor 6, 4, 5
4191; PPC64LE-NEXT: sthcx. 6, 0, 3
4192; PPC64LE-NEXT: bne 0, .LBB248_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4193; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4194; PPC64LE-NEXT: mr 3, 5
4195; PPC64LE-NEXT: lwsync
4196; PPC64LE-NEXT: blr
4197 %ret = atomicrmw xor i16* %ptr, i16 %val acq_rel
4198 ret i16 %ret
4199}
4200
4201define i16 @test249(i16* %ptr, i16 %val) {
4202; PPC64LE-LABEL: test249:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4203; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4204; PPC64LE-NEXT: sync
4205; PPC64LE-NEXT: .LBB249_1:
4206; PPC64LE-NEXT: lharx 5, 0, 3
4207; PPC64LE-NEXT: xor 6, 4, 5
4208; PPC64LE-NEXT: sthcx. 6, 0, 3
4209; PPC64LE-NEXT: bne 0, .LBB249_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4210; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4211; PPC64LE-NEXT: mr 3, 5
4212; PPC64LE-NEXT: lwsync
4213; PPC64LE-NEXT: blr
4214 %ret = atomicrmw xor i16* %ptr, i16 %val seq_cst
4215 ret i16 %ret
4216}
4217
4218define i32 @test250(i32* %ptr, i32 %val) {
4219; PPC64LE-LABEL: test250:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4220; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4221; PPC64LE-NEXT: .LBB250_1:
4222; PPC64LE-NEXT: lwarx 5, 0, 3
4223; PPC64LE-NEXT: xor 6, 4, 5
4224; PPC64LE-NEXT: stwcx. 6, 0, 3
4225; PPC64LE-NEXT: bne 0, .LBB250_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4226; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4227; PPC64LE-NEXT: mr 3, 5
4228; PPC64LE-NEXT: blr
4229 %ret = atomicrmw xor i32* %ptr, i32 %val monotonic
4230 ret i32 %ret
4231}
4232
4233define i32 @test251(i32* %ptr, i32 %val) {
4234; PPC64LE-LABEL: test251:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4235; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4236; PPC64LE-NEXT: mr 5, 3
4237; PPC64LE-NEXT: .LBB251_1:
4238; PPC64LE-NEXT: lwarx 3, 0, 5
4239; PPC64LE-NEXT: xor 6, 4, 3
4240; PPC64LE-NEXT: stwcx. 6, 0, 5
4241; PPC64LE-NEXT: bne 0, .LBB251_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4242; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4243; PPC64LE-NEXT: lwsync
4244; PPC64LE-NEXT: blr
4245 %ret = atomicrmw xor i32* %ptr, i32 %val acquire
4246 ret i32 %ret
4247}
4248
4249define i32 @test252(i32* %ptr, i32 %val) {
4250; PPC64LE-LABEL: test252:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4251; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4252; PPC64LE-NEXT: lwsync
4253; PPC64LE-NEXT: .LBB252_1:
4254; PPC64LE-NEXT: lwarx 5, 0, 3
4255; PPC64LE-NEXT: xor 6, 4, 5
4256; PPC64LE-NEXT: stwcx. 6, 0, 3
4257; PPC64LE-NEXT: bne 0, .LBB252_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4258; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4259; PPC64LE-NEXT: mr 3, 5
4260; PPC64LE-NEXT: blr
4261 %ret = atomicrmw xor i32* %ptr, i32 %val release
4262 ret i32 %ret
4263}
4264
4265define i32 @test253(i32* %ptr, i32 %val) {
4266; PPC64LE-LABEL: test253:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4267; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4268; PPC64LE-NEXT: lwsync
4269; PPC64LE-NEXT: .LBB253_1:
4270; PPC64LE-NEXT: lwarx 5, 0, 3
4271; PPC64LE-NEXT: xor 6, 4, 5
4272; PPC64LE-NEXT: stwcx. 6, 0, 3
4273; PPC64LE-NEXT: bne 0, .LBB253_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4274; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4275; PPC64LE-NEXT: mr 3, 5
4276; PPC64LE-NEXT: lwsync
4277; PPC64LE-NEXT: blr
4278 %ret = atomicrmw xor i32* %ptr, i32 %val acq_rel
4279 ret i32 %ret
4280}
4281
4282define i32 @test254(i32* %ptr, i32 %val) {
4283; PPC64LE-LABEL: test254:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4284; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4285; PPC64LE-NEXT: sync
4286; PPC64LE-NEXT: .LBB254_1:
4287; PPC64LE-NEXT: lwarx 5, 0, 3
4288; PPC64LE-NEXT: xor 6, 4, 5
4289; PPC64LE-NEXT: stwcx. 6, 0, 3
4290; PPC64LE-NEXT: bne 0, .LBB254_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4291; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4292; PPC64LE-NEXT: mr 3, 5
4293; PPC64LE-NEXT: lwsync
4294; PPC64LE-NEXT: blr
4295 %ret = atomicrmw xor i32* %ptr, i32 %val seq_cst
4296 ret i32 %ret
4297}
4298
4299define i64 @test255(i64* %ptr, i64 %val) {
4300; PPC64LE-LABEL: test255:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4301; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4302; PPC64LE-NEXT: .LBB255_1:
4303; PPC64LE-NEXT: ldarx 5, 0, 3
4304; PPC64LE-NEXT: xor 6, 4, 5
4305; PPC64LE-NEXT: stdcx. 6, 0, 3
4306; PPC64LE-NEXT: bne 0, .LBB255_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4307; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4308; PPC64LE-NEXT: mr 3, 5
4309; PPC64LE-NEXT: blr
4310 %ret = atomicrmw xor i64* %ptr, i64 %val monotonic
4311 ret i64 %ret
4312}
4313
4314define i64 @test256(i64* %ptr, i64 %val) {
4315; PPC64LE-LABEL: test256:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4316; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4317; PPC64LE-NEXT: mr 5, 3
4318; PPC64LE-NEXT: .LBB256_1:
4319; PPC64LE-NEXT: ldarx 3, 0, 5
4320; PPC64LE-NEXT: xor 6, 4, 3
4321; PPC64LE-NEXT: stdcx. 6, 0, 5
4322; PPC64LE-NEXT: bne 0, .LBB256_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4323; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4324; PPC64LE-NEXT: lwsync
4325; PPC64LE-NEXT: blr
4326 %ret = atomicrmw xor i64* %ptr, i64 %val acquire
4327 ret i64 %ret
4328}
4329
4330define i64 @test257(i64* %ptr, i64 %val) {
4331; PPC64LE-LABEL: test257:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4332; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4333; PPC64LE-NEXT: lwsync
4334; PPC64LE-NEXT: .LBB257_1:
4335; PPC64LE-NEXT: ldarx 5, 0, 3
4336; PPC64LE-NEXT: xor 6, 4, 5
4337; PPC64LE-NEXT: stdcx. 6, 0, 3
4338; PPC64LE-NEXT: bne 0, .LBB257_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4339; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4340; PPC64LE-NEXT: mr 3, 5
4341; PPC64LE-NEXT: blr
4342 %ret = atomicrmw xor i64* %ptr, i64 %val release
4343 ret i64 %ret
4344}
4345
4346define i64 @test258(i64* %ptr, i64 %val) {
4347; PPC64LE-LABEL: test258:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4348; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4349; PPC64LE-NEXT: lwsync
4350; PPC64LE-NEXT: .LBB258_1:
4351; PPC64LE-NEXT: ldarx 5, 0, 3
4352; PPC64LE-NEXT: xor 6, 4, 5
4353; PPC64LE-NEXT: stdcx. 6, 0, 3
4354; PPC64LE-NEXT: bne 0, .LBB258_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4355; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4356; PPC64LE-NEXT: mr 3, 5
4357; PPC64LE-NEXT: lwsync
4358; PPC64LE-NEXT: blr
4359 %ret = atomicrmw xor i64* %ptr, i64 %val acq_rel
4360 ret i64 %ret
4361}
4362
4363define i64 @test259(i64* %ptr, i64 %val) {
4364; PPC64LE-LABEL: test259:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4365; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4366; PPC64LE-NEXT: sync
4367; PPC64LE-NEXT: .LBB259_1:
4368; PPC64LE-NEXT: ldarx 5, 0, 3
4369; PPC64LE-NEXT: xor 6, 4, 5
4370; PPC64LE-NEXT: stdcx. 6, 0, 3
4371; PPC64LE-NEXT: bne 0, .LBB259_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4372; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4373; PPC64LE-NEXT: mr 3, 5
4374; PPC64LE-NEXT: lwsync
4375; PPC64LE-NEXT: blr
4376 %ret = atomicrmw xor i64* %ptr, i64 %val seq_cst
4377 ret i64 %ret
4378}
4379
4380define i8 @test260(i8* %ptr, i8 %val) {
4381; PPC64LE-LABEL: test260:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4382; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4383; PPC64LE-NEXT: .LBB260_1:
4384; PPC64LE-NEXT: lbarx 5, 0, 3
4385; PPC64LE-NEXT: extsb 6, 5
4386; PPC64LE-NEXT: cmpw 4, 6
4387; PPC64LE-NEXT: ble 0, .LBB260_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4388; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4389; PPC64LE-NEXT: stbcx. 4, 0, 3
4390; PPC64LE-NEXT: bne 0, .LBB260_1
4391; PPC64LE-NEXT: .LBB260_3:
4392; PPC64LE-NEXT: mr 3, 5
4393; PPC64LE-NEXT: blr
4394 %ret = atomicrmw max i8* %ptr, i8 %val monotonic
4395 ret i8 %ret
4396}
4397
4398define i8 @test261(i8* %ptr, i8 %val) {
4399; PPC64LE-LABEL: test261:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4400; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4401; PPC64LE-NEXT: mr 5, 3
4402; PPC64LE-NEXT: .LBB261_1:
4403; PPC64LE-NEXT: lbarx 3, 0, 5
4404; PPC64LE-NEXT: extsb 6, 3
4405; PPC64LE-NEXT: cmpw 4, 6
4406; PPC64LE-NEXT: ble 0, .LBB261_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4407; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4408; PPC64LE-NEXT: stbcx. 4, 0, 5
4409; PPC64LE-NEXT: bne 0, .LBB261_1
4410; PPC64LE-NEXT: .LBB261_3:
4411; PPC64LE-NEXT: lwsync
4412; PPC64LE-NEXT: blr
4413 %ret = atomicrmw max i8* %ptr, i8 %val acquire
4414 ret i8 %ret
4415}
4416
4417define i8 @test262(i8* %ptr, i8 %val) {
4418; PPC64LE-LABEL: test262:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4419; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4420; PPC64LE-NEXT: lwsync
4421; PPC64LE-NEXT: .LBB262_1:
4422; PPC64LE-NEXT: lbarx 5, 0, 3
4423; PPC64LE-NEXT: extsb 6, 5
4424; PPC64LE-NEXT: cmpw 4, 6
4425; PPC64LE-NEXT: ble 0, .LBB262_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4426; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4427; PPC64LE-NEXT: stbcx. 4, 0, 3
4428; PPC64LE-NEXT: bne 0, .LBB262_1
4429; PPC64LE-NEXT: .LBB262_3:
4430; PPC64LE-NEXT: mr 3, 5
4431; PPC64LE-NEXT: blr
4432 %ret = atomicrmw max i8* %ptr, i8 %val release
4433 ret i8 %ret
4434}
4435
4436define i8 @test263(i8* %ptr, i8 %val) {
4437; PPC64LE-LABEL: test263:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4438; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4439; PPC64LE-NEXT: lwsync
4440; PPC64LE-NEXT: .LBB263_1:
4441; PPC64LE-NEXT: lbarx 5, 0, 3
4442; PPC64LE-NEXT: extsb 6, 5
4443; PPC64LE-NEXT: cmpw 4, 6
4444; PPC64LE-NEXT: ble 0, .LBB263_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4445; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4446; PPC64LE-NEXT: stbcx. 4, 0, 3
4447; PPC64LE-NEXT: bne 0, .LBB263_1
4448; PPC64LE-NEXT: .LBB263_3:
4449; PPC64LE-NEXT: mr 3, 5
4450; PPC64LE-NEXT: lwsync
4451; PPC64LE-NEXT: blr
4452 %ret = atomicrmw max i8* %ptr, i8 %val acq_rel
4453 ret i8 %ret
4454}
4455
4456define i8 @test264(i8* %ptr, i8 %val) {
4457; PPC64LE-LABEL: test264:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4458; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4459; PPC64LE-NEXT: sync
4460; PPC64LE-NEXT: .LBB264_1:
4461; PPC64LE-NEXT: lbarx 5, 0, 3
4462; PPC64LE-NEXT: extsb 6, 5
4463; PPC64LE-NEXT: cmpw 4, 6
4464; PPC64LE-NEXT: ble 0, .LBB264_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4465; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4466; PPC64LE-NEXT: stbcx. 4, 0, 3
4467; PPC64LE-NEXT: bne 0, .LBB264_1
4468; PPC64LE-NEXT: .LBB264_3:
4469; PPC64LE-NEXT: mr 3, 5
4470; PPC64LE-NEXT: lwsync
4471; PPC64LE-NEXT: blr
4472 %ret = atomicrmw max i8* %ptr, i8 %val seq_cst
4473 ret i8 %ret
4474}
4475
4476define i16 @test265(i16* %ptr, i16 %val) {
4477; PPC64LE-LABEL: test265:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4478; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4479; PPC64LE-NEXT: .LBB265_1:
4480; PPC64LE-NEXT: lharx 5, 0, 3
4481; PPC64LE-NEXT: extsh 6, 5
4482; PPC64LE-NEXT: cmpw 4, 6
4483; PPC64LE-NEXT: ble 0, .LBB265_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4484; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4485; PPC64LE-NEXT: sthcx. 4, 0, 3
4486; PPC64LE-NEXT: bne 0, .LBB265_1
4487; PPC64LE-NEXT: .LBB265_3:
4488; PPC64LE-NEXT: mr 3, 5
4489; PPC64LE-NEXT: blr
4490 %ret = atomicrmw max i16* %ptr, i16 %val monotonic
4491 ret i16 %ret
4492}
4493
4494define i16 @test266(i16* %ptr, i16 %val) {
4495; PPC64LE-LABEL: test266:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4496; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4497; PPC64LE-NEXT: mr 5, 3
4498; PPC64LE-NEXT: .LBB266_1:
4499; PPC64LE-NEXT: lharx 3, 0, 5
4500; PPC64LE-NEXT: extsh 6, 3
4501; PPC64LE-NEXT: cmpw 4, 6
4502; PPC64LE-NEXT: ble 0, .LBB266_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4503; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4504; PPC64LE-NEXT: sthcx. 4, 0, 5
4505; PPC64LE-NEXT: bne 0, .LBB266_1
4506; PPC64LE-NEXT: .LBB266_3:
4507; PPC64LE-NEXT: lwsync
4508; PPC64LE-NEXT: blr
4509 %ret = atomicrmw max i16* %ptr, i16 %val acquire
4510 ret i16 %ret
4511}
4512
4513define i16 @test267(i16* %ptr, i16 %val) {
4514; PPC64LE-LABEL: test267:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4515; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4516; PPC64LE-NEXT: lwsync
4517; PPC64LE-NEXT: .LBB267_1:
4518; PPC64LE-NEXT: lharx 5, 0, 3
4519; PPC64LE-NEXT: extsh 6, 5
4520; PPC64LE-NEXT: cmpw 4, 6
4521; PPC64LE-NEXT: ble 0, .LBB267_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4522; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4523; PPC64LE-NEXT: sthcx. 4, 0, 3
4524; PPC64LE-NEXT: bne 0, .LBB267_1
4525; PPC64LE-NEXT: .LBB267_3:
4526; PPC64LE-NEXT: mr 3, 5
4527; PPC64LE-NEXT: blr
4528 %ret = atomicrmw max i16* %ptr, i16 %val release
4529 ret i16 %ret
4530}
4531
4532define i16 @test268(i16* %ptr, i16 %val) {
4533; PPC64LE-LABEL: test268:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4534; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4535; PPC64LE-NEXT: lwsync
4536; PPC64LE-NEXT: .LBB268_1:
4537; PPC64LE-NEXT: lharx 5, 0, 3
4538; PPC64LE-NEXT: extsh 6, 5
4539; PPC64LE-NEXT: cmpw 4, 6
4540; PPC64LE-NEXT: ble 0, .LBB268_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4541; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4542; PPC64LE-NEXT: sthcx. 4, 0, 3
4543; PPC64LE-NEXT: bne 0, .LBB268_1
4544; PPC64LE-NEXT: .LBB268_3:
4545; PPC64LE-NEXT: mr 3, 5
4546; PPC64LE-NEXT: lwsync
4547; PPC64LE-NEXT: blr
4548 %ret = atomicrmw max i16* %ptr, i16 %val acq_rel
4549 ret i16 %ret
4550}
4551
4552define i16 @test269(i16* %ptr, i16 %val) {
4553; PPC64LE-LABEL: test269:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4554; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4555; PPC64LE-NEXT: sync
4556; PPC64LE-NEXT: .LBB269_1:
4557; PPC64LE-NEXT: lharx 5, 0, 3
4558; PPC64LE-NEXT: extsh 6, 5
4559; PPC64LE-NEXT: cmpw 4, 6
4560; PPC64LE-NEXT: ble 0, .LBB269_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4561; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4562; PPC64LE-NEXT: sthcx. 4, 0, 3
4563; PPC64LE-NEXT: bne 0, .LBB269_1
4564; PPC64LE-NEXT: .LBB269_3:
4565; PPC64LE-NEXT: mr 3, 5
4566; PPC64LE-NEXT: lwsync
4567; PPC64LE-NEXT: blr
4568 %ret = atomicrmw max i16* %ptr, i16 %val seq_cst
4569 ret i16 %ret
4570}
4571
4572define i32 @test270(i32* %ptr, i32 %val) {
4573; PPC64LE-LABEL: test270:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4574; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4575; PPC64LE-NEXT: .LBB270_1:
4576; PPC64LE-NEXT: lwarx 5, 0, 3
4577; PPC64LE-NEXT: cmpw 4, 5
4578; PPC64LE-NEXT: ble 0, .LBB270_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4579; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4580; PPC64LE-NEXT: stwcx. 4, 0, 3
4581; PPC64LE-NEXT: bne 0, .LBB270_1
4582; PPC64LE-NEXT: .LBB270_3:
4583; PPC64LE-NEXT: mr 3, 5
4584; PPC64LE-NEXT: blr
4585 %ret = atomicrmw max i32* %ptr, i32 %val monotonic
4586 ret i32 %ret
4587}
4588
4589define i32 @test271(i32* %ptr, i32 %val) {
4590; PPC64LE-LABEL: test271:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4591; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4592; PPC64LE-NEXT: mr 5, 3
4593; PPC64LE-NEXT: .LBB271_1:
4594; PPC64LE-NEXT: lwarx 3, 0, 5
4595; PPC64LE-NEXT: cmpw 4, 3
4596; PPC64LE-NEXT: ble 0, .LBB271_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4597; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4598; PPC64LE-NEXT: stwcx. 4, 0, 5
4599; PPC64LE-NEXT: bne 0, .LBB271_1
4600; PPC64LE-NEXT: .LBB271_3:
4601; PPC64LE-NEXT: lwsync
4602; PPC64LE-NEXT: blr
4603 %ret = atomicrmw max i32* %ptr, i32 %val acquire
4604 ret i32 %ret
4605}
4606
4607define i32 @test272(i32* %ptr, i32 %val) {
4608; PPC64LE-LABEL: test272:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4609; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4610; PPC64LE-NEXT: lwsync
4611; PPC64LE-NEXT: .LBB272_1:
4612; PPC64LE-NEXT: lwarx 5, 0, 3
4613; PPC64LE-NEXT: cmpw 4, 5
4614; PPC64LE-NEXT: ble 0, .LBB272_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4615; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4616; PPC64LE-NEXT: stwcx. 4, 0, 3
4617; PPC64LE-NEXT: bne 0, .LBB272_1
4618; PPC64LE-NEXT: .LBB272_3:
4619; PPC64LE-NEXT: mr 3, 5
4620; PPC64LE-NEXT: blr
4621 %ret = atomicrmw max i32* %ptr, i32 %val release
4622 ret i32 %ret
4623}
4624
4625define i32 @test273(i32* %ptr, i32 %val) {
4626; PPC64LE-LABEL: test273:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4627; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4628; PPC64LE-NEXT: lwsync
4629; PPC64LE-NEXT: .LBB273_1:
4630; PPC64LE-NEXT: lwarx 5, 0, 3
4631; PPC64LE-NEXT: cmpw 4, 5
4632; PPC64LE-NEXT: ble 0, .LBB273_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4633; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4634; PPC64LE-NEXT: stwcx. 4, 0, 3
4635; PPC64LE-NEXT: bne 0, .LBB273_1
4636; PPC64LE-NEXT: .LBB273_3:
4637; PPC64LE-NEXT: mr 3, 5
4638; PPC64LE-NEXT: lwsync
4639; PPC64LE-NEXT: blr
4640 %ret = atomicrmw max i32* %ptr, i32 %val acq_rel
4641 ret i32 %ret
4642}
4643
4644define i32 @test274(i32* %ptr, i32 %val) {
4645; PPC64LE-LABEL: test274:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4646; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4647; PPC64LE-NEXT: sync
4648; PPC64LE-NEXT: .LBB274_1:
4649; PPC64LE-NEXT: lwarx 5, 0, 3
4650; PPC64LE-NEXT: cmpw 4, 5
4651; PPC64LE-NEXT: ble 0, .LBB274_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4652; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4653; PPC64LE-NEXT: stwcx. 4, 0, 3
4654; PPC64LE-NEXT: bne 0, .LBB274_1
4655; PPC64LE-NEXT: .LBB274_3:
4656; PPC64LE-NEXT: mr 3, 5
4657; PPC64LE-NEXT: lwsync
4658; PPC64LE-NEXT: blr
4659 %ret = atomicrmw max i32* %ptr, i32 %val seq_cst
4660 ret i32 %ret
4661}
4662
4663define i64 @test275(i64* %ptr, i64 %val) {
4664; PPC64LE-LABEL: test275:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4665; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4666; PPC64LE-NEXT: .LBB275_1:
4667; PPC64LE-NEXT: ldarx 5, 0, 3
4668; PPC64LE-NEXT: cmpd 4, 5
4669; PPC64LE-NEXT: ble 0, .LBB275_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4670; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4671; PPC64LE-NEXT: stdcx. 4, 0, 3
4672; PPC64LE-NEXT: bne 0, .LBB275_1
4673; PPC64LE-NEXT: .LBB275_3:
4674; PPC64LE-NEXT: mr 3, 5
4675; PPC64LE-NEXT: blr
4676 %ret = atomicrmw max i64* %ptr, i64 %val monotonic
4677 ret i64 %ret
4678}
4679
4680define i64 @test276(i64* %ptr, i64 %val) {
4681; PPC64LE-LABEL: test276:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4682; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4683; PPC64LE-NEXT: mr 5, 3
4684; PPC64LE-NEXT: .LBB276_1:
4685; PPC64LE-NEXT: ldarx 3, 0, 5
4686; PPC64LE-NEXT: cmpd 4, 3
4687; PPC64LE-NEXT: ble 0, .LBB276_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4688; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4689; PPC64LE-NEXT: stdcx. 4, 0, 5
4690; PPC64LE-NEXT: bne 0, .LBB276_1
4691; PPC64LE-NEXT: .LBB276_3:
4692; PPC64LE-NEXT: lwsync
4693; PPC64LE-NEXT: blr
4694 %ret = atomicrmw max i64* %ptr, i64 %val acquire
4695 ret i64 %ret
4696}
4697
4698define i64 @test277(i64* %ptr, i64 %val) {
4699; PPC64LE-LABEL: test277:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4700; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4701; PPC64LE-NEXT: lwsync
4702; PPC64LE-NEXT: .LBB277_1:
4703; PPC64LE-NEXT: ldarx 5, 0, 3
4704; PPC64LE-NEXT: cmpd 4, 5
4705; PPC64LE-NEXT: ble 0, .LBB277_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4706; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4707; PPC64LE-NEXT: stdcx. 4, 0, 3
4708; PPC64LE-NEXT: bne 0, .LBB277_1
4709; PPC64LE-NEXT: .LBB277_3:
4710; PPC64LE-NEXT: mr 3, 5
4711; PPC64LE-NEXT: blr
4712 %ret = atomicrmw max i64* %ptr, i64 %val release
4713 ret i64 %ret
4714}
4715
4716define i64 @test278(i64* %ptr, i64 %val) {
4717; PPC64LE-LABEL: test278:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4718; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4719; PPC64LE-NEXT: lwsync
4720; PPC64LE-NEXT: .LBB278_1:
4721; PPC64LE-NEXT: ldarx 5, 0, 3
4722; PPC64LE-NEXT: cmpd 4, 5
4723; PPC64LE-NEXT: ble 0, .LBB278_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4724; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4725; PPC64LE-NEXT: stdcx. 4, 0, 3
4726; PPC64LE-NEXT: bne 0, .LBB278_1
4727; PPC64LE-NEXT: .LBB278_3:
4728; PPC64LE-NEXT: mr 3, 5
4729; PPC64LE-NEXT: lwsync
4730; PPC64LE-NEXT: blr
4731 %ret = atomicrmw max i64* %ptr, i64 %val acq_rel
4732 ret i64 %ret
4733}
4734
4735define i64 @test279(i64* %ptr, i64 %val) {
4736; PPC64LE-LABEL: test279:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4737; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4738; PPC64LE-NEXT: sync
4739; PPC64LE-NEXT: .LBB279_1:
4740; PPC64LE-NEXT: ldarx 5, 0, 3
4741; PPC64LE-NEXT: cmpd 4, 5
4742; PPC64LE-NEXT: ble 0, .LBB279_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4743; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4744; PPC64LE-NEXT: stdcx. 4, 0, 3
4745; PPC64LE-NEXT: bne 0, .LBB279_1
4746; PPC64LE-NEXT: .LBB279_3:
4747; PPC64LE-NEXT: mr 3, 5
4748; PPC64LE-NEXT: lwsync
4749; PPC64LE-NEXT: blr
4750 %ret = atomicrmw max i64* %ptr, i64 %val seq_cst
4751 ret i64 %ret
4752}
4753
4754define i8 @test280(i8* %ptr, i8 %val) {
4755; PPC64LE-LABEL: test280:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4756; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4757; PPC64LE-NEXT: .LBB280_1:
4758; PPC64LE-NEXT: lbarx 5, 0, 3
4759; PPC64LE-NEXT: extsb 6, 5
4760; PPC64LE-NEXT: cmpw 4, 6
4761; PPC64LE-NEXT: bge 0, .LBB280_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4762; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4763; PPC64LE-NEXT: stbcx. 4, 0, 3
4764; PPC64LE-NEXT: bne 0, .LBB280_1
4765; PPC64LE-NEXT: .LBB280_3:
4766; PPC64LE-NEXT: mr 3, 5
4767; PPC64LE-NEXT: blr
4768 %ret = atomicrmw min i8* %ptr, i8 %val monotonic
4769 ret i8 %ret
4770}
4771
4772define i8 @test281(i8* %ptr, i8 %val) {
4773; PPC64LE-LABEL: test281:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4774; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4775; PPC64LE-NEXT: mr 5, 3
4776; PPC64LE-NEXT: .LBB281_1:
4777; PPC64LE-NEXT: lbarx 3, 0, 5
4778; PPC64LE-NEXT: extsb 6, 3
4779; PPC64LE-NEXT: cmpw 4, 6
4780; PPC64LE-NEXT: bge 0, .LBB281_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4781; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4782; PPC64LE-NEXT: stbcx. 4, 0, 5
4783; PPC64LE-NEXT: bne 0, .LBB281_1
4784; PPC64LE-NEXT: .LBB281_3:
4785; PPC64LE-NEXT: lwsync
4786; PPC64LE-NEXT: blr
4787 %ret = atomicrmw min i8* %ptr, i8 %val acquire
4788 ret i8 %ret
4789}
4790
4791define i8 @test282(i8* %ptr, i8 %val) {
4792; PPC64LE-LABEL: test282:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4793; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4794; PPC64LE-NEXT: lwsync
4795; PPC64LE-NEXT: .LBB282_1:
4796; PPC64LE-NEXT: lbarx 5, 0, 3
4797; PPC64LE-NEXT: extsb 6, 5
4798; PPC64LE-NEXT: cmpw 4, 6
4799; PPC64LE-NEXT: bge 0, .LBB282_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4800; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4801; PPC64LE-NEXT: stbcx. 4, 0, 3
4802; PPC64LE-NEXT: bne 0, .LBB282_1
4803; PPC64LE-NEXT: .LBB282_3:
4804; PPC64LE-NEXT: mr 3, 5
4805; PPC64LE-NEXT: blr
4806 %ret = atomicrmw min i8* %ptr, i8 %val release
4807 ret i8 %ret
4808}
4809
4810define i8 @test283(i8* %ptr, i8 %val) {
4811; PPC64LE-LABEL: test283:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4812; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4813; PPC64LE-NEXT: lwsync
4814; PPC64LE-NEXT: .LBB283_1:
4815; PPC64LE-NEXT: lbarx 5, 0, 3
4816; PPC64LE-NEXT: extsb 6, 5
4817; PPC64LE-NEXT: cmpw 4, 6
4818; PPC64LE-NEXT: bge 0, .LBB283_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4819; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4820; PPC64LE-NEXT: stbcx. 4, 0, 3
4821; PPC64LE-NEXT: bne 0, .LBB283_1
4822; PPC64LE-NEXT: .LBB283_3:
4823; PPC64LE-NEXT: mr 3, 5
4824; PPC64LE-NEXT: lwsync
4825; PPC64LE-NEXT: blr
4826 %ret = atomicrmw min i8* %ptr, i8 %val acq_rel
4827 ret i8 %ret
4828}
4829
4830define i8 @test284(i8* %ptr, i8 %val) {
4831; PPC64LE-LABEL: test284:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4832; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4833; PPC64LE-NEXT: sync
4834; PPC64LE-NEXT: .LBB284_1:
4835; PPC64LE-NEXT: lbarx 5, 0, 3
4836; PPC64LE-NEXT: extsb 6, 5
4837; PPC64LE-NEXT: cmpw 4, 6
4838; PPC64LE-NEXT: bge 0, .LBB284_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4839; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4840; PPC64LE-NEXT: stbcx. 4, 0, 3
4841; PPC64LE-NEXT: bne 0, .LBB284_1
4842; PPC64LE-NEXT: .LBB284_3:
4843; PPC64LE-NEXT: mr 3, 5
4844; PPC64LE-NEXT: lwsync
4845; PPC64LE-NEXT: blr
4846 %ret = atomicrmw min i8* %ptr, i8 %val seq_cst
4847 ret i8 %ret
4848}
4849
4850define i16 @test285(i16* %ptr, i16 %val) {
4851; PPC64LE-LABEL: test285:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4852; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4853; PPC64LE-NEXT: .LBB285_1:
4854; PPC64LE-NEXT: lharx 5, 0, 3
4855; PPC64LE-NEXT: extsh 6, 5
4856; PPC64LE-NEXT: cmpw 4, 6
4857; PPC64LE-NEXT: bge 0, .LBB285_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4858; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4859; PPC64LE-NEXT: sthcx. 4, 0, 3
4860; PPC64LE-NEXT: bne 0, .LBB285_1
4861; PPC64LE-NEXT: .LBB285_3:
4862; PPC64LE-NEXT: mr 3, 5
4863; PPC64LE-NEXT: blr
4864 %ret = atomicrmw min i16* %ptr, i16 %val monotonic
4865 ret i16 %ret
4866}
4867
4868define i16 @test286(i16* %ptr, i16 %val) {
4869; PPC64LE-LABEL: test286:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4870; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4871; PPC64LE-NEXT: mr 5, 3
4872; PPC64LE-NEXT: .LBB286_1:
4873; PPC64LE-NEXT: lharx 3, 0, 5
4874; PPC64LE-NEXT: extsh 6, 3
4875; PPC64LE-NEXT: cmpw 4, 6
4876; PPC64LE-NEXT: bge 0, .LBB286_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4877; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4878; PPC64LE-NEXT: sthcx. 4, 0, 5
4879; PPC64LE-NEXT: bne 0, .LBB286_1
4880; PPC64LE-NEXT: .LBB286_3:
4881; PPC64LE-NEXT: lwsync
4882; PPC64LE-NEXT: blr
4883 %ret = atomicrmw min i16* %ptr, i16 %val acquire
4884 ret i16 %ret
4885}
4886
4887define i16 @test287(i16* %ptr, i16 %val) {
4888; PPC64LE-LABEL: test287:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4889; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4890; PPC64LE-NEXT: lwsync
4891; PPC64LE-NEXT: .LBB287_1:
4892; PPC64LE-NEXT: lharx 5, 0, 3
4893; PPC64LE-NEXT: extsh 6, 5
4894; PPC64LE-NEXT: cmpw 4, 6
4895; PPC64LE-NEXT: bge 0, .LBB287_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4896; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4897; PPC64LE-NEXT: sthcx. 4, 0, 3
4898; PPC64LE-NEXT: bne 0, .LBB287_1
4899; PPC64LE-NEXT: .LBB287_3:
4900; PPC64LE-NEXT: mr 3, 5
4901; PPC64LE-NEXT: blr
4902 %ret = atomicrmw min i16* %ptr, i16 %val release
4903 ret i16 %ret
4904}
4905
4906define i16 @test288(i16* %ptr, i16 %val) {
4907; PPC64LE-LABEL: test288:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4908; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4909; PPC64LE-NEXT: lwsync
4910; PPC64LE-NEXT: .LBB288_1:
4911; PPC64LE-NEXT: lharx 5, 0, 3
4912; PPC64LE-NEXT: extsh 6, 5
4913; PPC64LE-NEXT: cmpw 4, 6
4914; PPC64LE-NEXT: bge 0, .LBB288_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4915; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4916; PPC64LE-NEXT: sthcx. 4, 0, 3
4917; PPC64LE-NEXT: bne 0, .LBB288_1
4918; PPC64LE-NEXT: .LBB288_3:
4919; PPC64LE-NEXT: mr 3, 5
4920; PPC64LE-NEXT: lwsync
4921; PPC64LE-NEXT: blr
4922 %ret = atomicrmw min i16* %ptr, i16 %val acq_rel
4923 ret i16 %ret
4924}
4925
4926define i16 @test289(i16* %ptr, i16 %val) {
4927; PPC64LE-LABEL: test289:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4928; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4929; PPC64LE-NEXT: sync
4930; PPC64LE-NEXT: .LBB289_1:
4931; PPC64LE-NEXT: lharx 5, 0, 3
4932; PPC64LE-NEXT: extsh 6, 5
4933; PPC64LE-NEXT: cmpw 4, 6
4934; PPC64LE-NEXT: bge 0, .LBB289_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4935; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4936; PPC64LE-NEXT: sthcx. 4, 0, 3
4937; PPC64LE-NEXT: bne 0, .LBB289_1
4938; PPC64LE-NEXT: .LBB289_3:
4939; PPC64LE-NEXT: mr 3, 5
4940; PPC64LE-NEXT: lwsync
4941; PPC64LE-NEXT: blr
4942 %ret = atomicrmw min i16* %ptr, i16 %val seq_cst
4943 ret i16 %ret
4944}
4945
4946define i32 @test290(i32* %ptr, i32 %val) {
4947; PPC64LE-LABEL: test290:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4948; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4949; PPC64LE-NEXT: .LBB290_1:
4950; PPC64LE-NEXT: lwarx 5, 0, 3
4951; PPC64LE-NEXT: cmpw 4, 5
4952; PPC64LE-NEXT: bge 0, .LBB290_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4953; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4954; PPC64LE-NEXT: stwcx. 4, 0, 3
4955; PPC64LE-NEXT: bne 0, .LBB290_1
4956; PPC64LE-NEXT: .LBB290_3:
4957; PPC64LE-NEXT: mr 3, 5
4958; PPC64LE-NEXT: blr
4959 %ret = atomicrmw min i32* %ptr, i32 %val monotonic
4960 ret i32 %ret
4961}
4962
4963define i32 @test291(i32* %ptr, i32 %val) {
4964; PPC64LE-LABEL: test291:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4965; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4966; PPC64LE-NEXT: mr 5, 3
4967; PPC64LE-NEXT: .LBB291_1:
4968; PPC64LE-NEXT: lwarx 3, 0, 5
4969; PPC64LE-NEXT: cmpw 4, 3
4970; PPC64LE-NEXT: bge 0, .LBB291_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4971; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4972; PPC64LE-NEXT: stwcx. 4, 0, 5
4973; PPC64LE-NEXT: bne 0, .LBB291_1
4974; PPC64LE-NEXT: .LBB291_3:
4975; PPC64LE-NEXT: lwsync
4976; PPC64LE-NEXT: blr
4977 %ret = atomicrmw min i32* %ptr, i32 %val acquire
4978 ret i32 %ret
4979}
4980
4981define i32 @test292(i32* %ptr, i32 %val) {
4982; PPC64LE-LABEL: test292:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4983; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4984; PPC64LE-NEXT: lwsync
4985; PPC64LE-NEXT: .LBB292_1:
4986; PPC64LE-NEXT: lwarx 5, 0, 3
4987; PPC64LE-NEXT: cmpw 4, 5
4988; PPC64LE-NEXT: bge 0, .LBB292_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]4989; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]4990; PPC64LE-NEXT: stwcx. 4, 0, 3
4991; PPC64LE-NEXT: bne 0, .LBB292_1
4992; PPC64LE-NEXT: .LBB292_3:
4993; PPC64LE-NEXT: mr 3, 5
4994; PPC64LE-NEXT: blr
4995 %ret = atomicrmw min i32* %ptr, i32 %val release
4996 ret i32 %ret
4997}
4998
4999define i32 @test293(i32* %ptr, i32 %val) {
5000; PPC64LE-LABEL: test293:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5001; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5002; PPC64LE-NEXT: lwsync
5003; PPC64LE-NEXT: .LBB293_1:
5004; PPC64LE-NEXT: lwarx 5, 0, 3
5005; PPC64LE-NEXT: cmpw 4, 5
5006; PPC64LE-NEXT: bge 0, .LBB293_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5007; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5008; PPC64LE-NEXT: stwcx. 4, 0, 3
5009; PPC64LE-NEXT: bne 0, .LBB293_1
5010; PPC64LE-NEXT: .LBB293_3:
5011; PPC64LE-NEXT: mr 3, 5
5012; PPC64LE-NEXT: lwsync
5013; PPC64LE-NEXT: blr
5014 %ret = atomicrmw min i32* %ptr, i32 %val acq_rel
5015 ret i32 %ret
5016}
5017
5018define i32 @test294(i32* %ptr, i32 %val) {
5019; PPC64LE-LABEL: test294:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5020; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5021; PPC64LE-NEXT: sync
5022; PPC64LE-NEXT: .LBB294_1:
5023; PPC64LE-NEXT: lwarx 5, 0, 3
5024; PPC64LE-NEXT: cmpw 4, 5
5025; PPC64LE-NEXT: bge 0, .LBB294_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5026; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5027; PPC64LE-NEXT: stwcx. 4, 0, 3
5028; PPC64LE-NEXT: bne 0, .LBB294_1
5029; PPC64LE-NEXT: .LBB294_3:
5030; PPC64LE-NEXT: mr 3, 5
5031; PPC64LE-NEXT: lwsync
5032; PPC64LE-NEXT: blr
5033 %ret = atomicrmw min i32* %ptr, i32 %val seq_cst
5034 ret i32 %ret
5035}
5036
5037define i64 @test295(i64* %ptr, i64 %val) {
5038; PPC64LE-LABEL: test295:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5039; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5040; PPC64LE-NEXT: .LBB295_1:
5041; PPC64LE-NEXT: ldarx 5, 0, 3
5042; PPC64LE-NEXT: cmpd 4, 5
5043; PPC64LE-NEXT: bge 0, .LBB295_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5044; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5045; PPC64LE-NEXT: stdcx. 4, 0, 3
5046; PPC64LE-NEXT: bne 0, .LBB295_1
5047; PPC64LE-NEXT: .LBB295_3:
5048; PPC64LE-NEXT: mr 3, 5
5049; PPC64LE-NEXT: blr
5050 %ret = atomicrmw min i64* %ptr, i64 %val monotonic
5051 ret i64 %ret
5052}
5053
5054define i64 @test296(i64* %ptr, i64 %val) {
5055; PPC64LE-LABEL: test296:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5056; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5057; PPC64LE-NEXT: mr 5, 3
5058; PPC64LE-NEXT: .LBB296_1:
5059; PPC64LE-NEXT: ldarx 3, 0, 5
5060; PPC64LE-NEXT: cmpd 4, 3
5061; PPC64LE-NEXT: bge 0, .LBB296_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5062; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5063; PPC64LE-NEXT: stdcx. 4, 0, 5
5064; PPC64LE-NEXT: bne 0, .LBB296_1
5065; PPC64LE-NEXT: .LBB296_3:
5066; PPC64LE-NEXT: lwsync
5067; PPC64LE-NEXT: blr
5068 %ret = atomicrmw min i64* %ptr, i64 %val acquire
5069 ret i64 %ret
5070}
5071
5072define i64 @test297(i64* %ptr, i64 %val) {
5073; PPC64LE-LABEL: test297:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5074; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5075; PPC64LE-NEXT: lwsync
5076; PPC64LE-NEXT: .LBB297_1:
5077; PPC64LE-NEXT: ldarx 5, 0, 3
5078; PPC64LE-NEXT: cmpd 4, 5
5079; PPC64LE-NEXT: bge 0, .LBB297_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5080; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5081; PPC64LE-NEXT: stdcx. 4, 0, 3
5082; PPC64LE-NEXT: bne 0, .LBB297_1
5083; PPC64LE-NEXT: .LBB297_3:
5084; PPC64LE-NEXT: mr 3, 5
5085; PPC64LE-NEXT: blr
5086 %ret = atomicrmw min i64* %ptr, i64 %val release
5087 ret i64 %ret
5088}
5089
5090define i64 @test298(i64* %ptr, i64 %val) {
5091; PPC64LE-LABEL: test298:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5092; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5093; PPC64LE-NEXT: lwsync
5094; PPC64LE-NEXT: .LBB298_1:
5095; PPC64LE-NEXT: ldarx 5, 0, 3
5096; PPC64LE-NEXT: cmpd 4, 5
5097; PPC64LE-NEXT: bge 0, .LBB298_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5098; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5099; PPC64LE-NEXT: stdcx. 4, 0, 3
5100; PPC64LE-NEXT: bne 0, .LBB298_1
5101; PPC64LE-NEXT: .LBB298_3:
5102; PPC64LE-NEXT: mr 3, 5
5103; PPC64LE-NEXT: lwsync
5104; PPC64LE-NEXT: blr
5105 %ret = atomicrmw min i64* %ptr, i64 %val acq_rel
5106 ret i64 %ret
5107}
5108
5109define i64 @test299(i64* %ptr, i64 %val) {
5110; PPC64LE-LABEL: test299:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5111; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5112; PPC64LE-NEXT: sync
5113; PPC64LE-NEXT: .LBB299_1:
5114; PPC64LE-NEXT: ldarx 5, 0, 3
5115; PPC64LE-NEXT: cmpd 4, 5
5116; PPC64LE-NEXT: bge 0, .LBB299_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5117; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5118; PPC64LE-NEXT: stdcx. 4, 0, 3
5119; PPC64LE-NEXT: bne 0, .LBB299_1
5120; PPC64LE-NEXT: .LBB299_3:
5121; PPC64LE-NEXT: mr 3, 5
5122; PPC64LE-NEXT: lwsync
5123; PPC64LE-NEXT: blr
5124 %ret = atomicrmw min i64* %ptr, i64 %val seq_cst
5125 ret i64 %ret
5126}
5127
5128define i8 @test300(i8* %ptr, i8 %val) {
5129; PPC64LE-LABEL: test300:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5130; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5131; PPC64LE-NEXT: .LBB300_1:
5132; PPC64LE-NEXT: lbarx 5, 0, 3
5133; PPC64LE-NEXT: cmplw 4, 5
5134; PPC64LE-NEXT: ble 0, .LBB300_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5135; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5136; PPC64LE-NEXT: stbcx. 4, 0, 3
5137; PPC64LE-NEXT: bne 0, .LBB300_1
5138; PPC64LE-NEXT: .LBB300_3:
5139; PPC64LE-NEXT: mr 3, 5
5140; PPC64LE-NEXT: blr
5141 %ret = atomicrmw umax i8* %ptr, i8 %val monotonic
5142 ret i8 %ret
5143}
5144
5145define i8 @test301(i8* %ptr, i8 %val) {
5146; PPC64LE-LABEL: test301:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5147; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5148; PPC64LE-NEXT: mr 5, 3
5149; PPC64LE-NEXT: .LBB301_1:
5150; PPC64LE-NEXT: lbarx 3, 0, 5
5151; PPC64LE-NEXT: cmplw 4, 3
5152; PPC64LE-NEXT: ble 0, .LBB301_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5153; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5154; PPC64LE-NEXT: stbcx. 4, 0, 5
5155; PPC64LE-NEXT: bne 0, .LBB301_1
5156; PPC64LE-NEXT: .LBB301_3:
5157; PPC64LE-NEXT: lwsync
5158; PPC64LE-NEXT: blr
5159 %ret = atomicrmw umax i8* %ptr, i8 %val acquire
5160 ret i8 %ret
5161}
5162
5163define i8 @test302(i8* %ptr, i8 %val) {
5164; PPC64LE-LABEL: test302:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5165; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5166; PPC64LE-NEXT: lwsync
5167; PPC64LE-NEXT: .LBB302_1:
5168; PPC64LE-NEXT: lbarx 5, 0, 3
5169; PPC64LE-NEXT: cmplw 4, 5
5170; PPC64LE-NEXT: ble 0, .LBB302_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5171; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5172; PPC64LE-NEXT: stbcx. 4, 0, 3
5173; PPC64LE-NEXT: bne 0, .LBB302_1
5174; PPC64LE-NEXT: .LBB302_3:
5175; PPC64LE-NEXT: mr 3, 5
5176; PPC64LE-NEXT: blr
5177 %ret = atomicrmw umax i8* %ptr, i8 %val release
5178 ret i8 %ret
5179}
5180
5181define i8 @test303(i8* %ptr, i8 %val) {
5182; PPC64LE-LABEL: test303:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5183; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5184; PPC64LE-NEXT: lwsync
5185; PPC64LE-NEXT: .LBB303_1:
5186; PPC64LE-NEXT: lbarx 5, 0, 3
5187; PPC64LE-NEXT: cmplw 4, 5
5188; PPC64LE-NEXT: ble 0, .LBB303_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5189; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5190; PPC64LE-NEXT: stbcx. 4, 0, 3
5191; PPC64LE-NEXT: bne 0, .LBB303_1
5192; PPC64LE-NEXT: .LBB303_3:
5193; PPC64LE-NEXT: mr 3, 5
5194; PPC64LE-NEXT: lwsync
5195; PPC64LE-NEXT: blr
5196 %ret = atomicrmw umax i8* %ptr, i8 %val acq_rel
5197 ret i8 %ret
5198}
5199
5200define i8 @test304(i8* %ptr, i8 %val) {
5201; PPC64LE-LABEL: test304:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5202; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5203; PPC64LE-NEXT: sync
5204; PPC64LE-NEXT: .LBB304_1:
5205; PPC64LE-NEXT: lbarx 5, 0, 3
5206; PPC64LE-NEXT: cmplw 4, 5
5207; PPC64LE-NEXT: ble 0, .LBB304_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5208; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5209; PPC64LE-NEXT: stbcx. 4, 0, 3
5210; PPC64LE-NEXT: bne 0, .LBB304_1
5211; PPC64LE-NEXT: .LBB304_3:
5212; PPC64LE-NEXT: mr 3, 5
5213; PPC64LE-NEXT: lwsync
5214; PPC64LE-NEXT: blr
5215 %ret = atomicrmw umax i8* %ptr, i8 %val seq_cst
5216 ret i8 %ret
5217}
5218
5219define i16 @test305(i16* %ptr, i16 %val) {
5220; PPC64LE-LABEL: test305:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5221; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5222; PPC64LE-NEXT: .LBB305_1:
5223; PPC64LE-NEXT: lharx 5, 0, 3
5224; PPC64LE-NEXT: cmplw 4, 5
5225; PPC64LE-NEXT: ble 0, .LBB305_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5226; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5227; PPC64LE-NEXT: sthcx. 4, 0, 3
5228; PPC64LE-NEXT: bne 0, .LBB305_1
5229; PPC64LE-NEXT: .LBB305_3:
5230; PPC64LE-NEXT: mr 3, 5
5231; PPC64LE-NEXT: blr
5232 %ret = atomicrmw umax i16* %ptr, i16 %val monotonic
5233 ret i16 %ret
5234}
5235
5236define i16 @test306(i16* %ptr, i16 %val) {
5237; PPC64LE-LABEL: test306:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5238; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5239; PPC64LE-NEXT: mr 5, 3
5240; PPC64LE-NEXT: .LBB306_1:
5241; PPC64LE-NEXT: lharx 3, 0, 5
5242; PPC64LE-NEXT: cmplw 4, 3
5243; PPC64LE-NEXT: ble 0, .LBB306_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5244; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5245; PPC64LE-NEXT: sthcx. 4, 0, 5
5246; PPC64LE-NEXT: bne 0, .LBB306_1
5247; PPC64LE-NEXT: .LBB306_3:
5248; PPC64LE-NEXT: lwsync
5249; PPC64LE-NEXT: blr
5250 %ret = atomicrmw umax i16* %ptr, i16 %val acquire
5251 ret i16 %ret
5252}
5253
5254define i16 @test307(i16* %ptr, i16 %val) {
5255; PPC64LE-LABEL: test307:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5256; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5257; PPC64LE-NEXT: lwsync
5258; PPC64LE-NEXT: .LBB307_1:
5259; PPC64LE-NEXT: lharx 5, 0, 3
5260; PPC64LE-NEXT: cmplw 4, 5
5261; PPC64LE-NEXT: ble 0, .LBB307_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5262; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5263; PPC64LE-NEXT: sthcx. 4, 0, 3
5264; PPC64LE-NEXT: bne 0, .LBB307_1
5265; PPC64LE-NEXT: .LBB307_3:
5266; PPC64LE-NEXT: mr 3, 5
5267; PPC64LE-NEXT: blr
5268 %ret = atomicrmw umax i16* %ptr, i16 %val release
5269 ret i16 %ret
5270}
5271
5272define i16 @test308(i16* %ptr, i16 %val) {
5273; PPC64LE-LABEL: test308:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5274; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5275; PPC64LE-NEXT: lwsync
5276; PPC64LE-NEXT: .LBB308_1:
5277; PPC64LE-NEXT: lharx 5, 0, 3
5278; PPC64LE-NEXT: cmplw 4, 5
5279; PPC64LE-NEXT: ble 0, .LBB308_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5280; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5281; PPC64LE-NEXT: sthcx. 4, 0, 3
5282; PPC64LE-NEXT: bne 0, .LBB308_1
5283; PPC64LE-NEXT: .LBB308_3:
5284; PPC64LE-NEXT: mr 3, 5
5285; PPC64LE-NEXT: lwsync
5286; PPC64LE-NEXT: blr
5287 %ret = atomicrmw umax i16* %ptr, i16 %val acq_rel
5288 ret i16 %ret
5289}
5290
5291define i16 @test309(i16* %ptr, i16 %val) {
5292; PPC64LE-LABEL: test309:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5293; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5294; PPC64LE-NEXT: sync
5295; PPC64LE-NEXT: .LBB309_1:
5296; PPC64LE-NEXT: lharx 5, 0, 3
5297; PPC64LE-NEXT: cmplw 4, 5
5298; PPC64LE-NEXT: ble 0, .LBB309_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5299; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5300; PPC64LE-NEXT: sthcx. 4, 0, 3
5301; PPC64LE-NEXT: bne 0, .LBB309_1
5302; PPC64LE-NEXT: .LBB309_3:
5303; PPC64LE-NEXT: mr 3, 5
5304; PPC64LE-NEXT: lwsync
5305; PPC64LE-NEXT: blr
5306 %ret = atomicrmw umax i16* %ptr, i16 %val seq_cst
5307 ret i16 %ret
5308}
5309
5310define i32 @test310(i32* %ptr, i32 %val) {
5311; PPC64LE-LABEL: test310:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5312; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5313; PPC64LE-NEXT: .LBB310_1:
5314; PPC64LE-NEXT: lwarx 5, 0, 3
5315; PPC64LE-NEXT: cmplw 4, 5
5316; PPC64LE-NEXT: ble 0, .LBB310_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5317; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5318; PPC64LE-NEXT: stwcx. 4, 0, 3
5319; PPC64LE-NEXT: bne 0, .LBB310_1
5320; PPC64LE-NEXT: .LBB310_3:
5321; PPC64LE-NEXT: mr 3, 5
5322; PPC64LE-NEXT: blr
5323 %ret = atomicrmw umax i32* %ptr, i32 %val monotonic
5324 ret i32 %ret
5325}
5326
5327define i32 @test311(i32* %ptr, i32 %val) {
5328; PPC64LE-LABEL: test311:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5329; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5330; PPC64LE-NEXT: mr 5, 3
5331; PPC64LE-NEXT: .LBB311_1:
5332; PPC64LE-NEXT: lwarx 3, 0, 5
5333; PPC64LE-NEXT: cmplw 4, 3
5334; PPC64LE-NEXT: ble 0, .LBB311_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5335; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5336; PPC64LE-NEXT: stwcx. 4, 0, 5
5337; PPC64LE-NEXT: bne 0, .LBB311_1
5338; PPC64LE-NEXT: .LBB311_3:
5339; PPC64LE-NEXT: lwsync
5340; PPC64LE-NEXT: blr
5341 %ret = atomicrmw umax i32* %ptr, i32 %val acquire
5342 ret i32 %ret
5343}
5344
5345define i32 @test312(i32* %ptr, i32 %val) {
5346; PPC64LE-LABEL: test312:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5347; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5348; PPC64LE-NEXT: lwsync
5349; PPC64LE-NEXT: .LBB312_1:
5350; PPC64LE-NEXT: lwarx 5, 0, 3
5351; PPC64LE-NEXT: cmplw 4, 5
5352; PPC64LE-NEXT: ble 0, .LBB312_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5353; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5354; PPC64LE-NEXT: stwcx. 4, 0, 3
5355; PPC64LE-NEXT: bne 0, .LBB312_1
5356; PPC64LE-NEXT: .LBB312_3:
5357; PPC64LE-NEXT: mr 3, 5
5358; PPC64LE-NEXT: blr
5359 %ret = atomicrmw umax i32* %ptr, i32 %val release
5360 ret i32 %ret
5361}
5362
5363define i32 @test313(i32* %ptr, i32 %val) {
5364; PPC64LE-LABEL: test313:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5365; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5366; PPC64LE-NEXT: lwsync
5367; PPC64LE-NEXT: .LBB313_1:
5368; PPC64LE-NEXT: lwarx 5, 0, 3
5369; PPC64LE-NEXT: cmplw 4, 5
5370; PPC64LE-NEXT: ble 0, .LBB313_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5371; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5372; PPC64LE-NEXT: stwcx. 4, 0, 3
5373; PPC64LE-NEXT: bne 0, .LBB313_1
5374; PPC64LE-NEXT: .LBB313_3:
5375; PPC64LE-NEXT: mr 3, 5
5376; PPC64LE-NEXT: lwsync
5377; PPC64LE-NEXT: blr
5378 %ret = atomicrmw umax i32* %ptr, i32 %val acq_rel
5379 ret i32 %ret
5380}
5381
5382define i32 @test314(i32* %ptr, i32 %val) {
5383; PPC64LE-LABEL: test314:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5384; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5385; PPC64LE-NEXT: sync
5386; PPC64LE-NEXT: .LBB314_1:
5387; PPC64LE-NEXT: lwarx 5, 0, 3
5388; PPC64LE-NEXT: cmplw 4, 5
5389; PPC64LE-NEXT: ble 0, .LBB314_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5390; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5391; PPC64LE-NEXT: stwcx. 4, 0, 3
5392; PPC64LE-NEXT: bne 0, .LBB314_1
5393; PPC64LE-NEXT: .LBB314_3:
5394; PPC64LE-NEXT: mr 3, 5
5395; PPC64LE-NEXT: lwsync
5396; PPC64LE-NEXT: blr
5397 %ret = atomicrmw umax i32* %ptr, i32 %val seq_cst
5398 ret i32 %ret
5399}
5400
5401define i64 @test315(i64* %ptr, i64 %val) {
5402; PPC64LE-LABEL: test315:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5403; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5404; PPC64LE-NEXT: .LBB315_1:
5405; PPC64LE-NEXT: ldarx 5, 0, 3
5406; PPC64LE-NEXT: cmpld 4, 5
5407; PPC64LE-NEXT: ble 0, .LBB315_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5408; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5409; PPC64LE-NEXT: stdcx. 4, 0, 3
5410; PPC64LE-NEXT: bne 0, .LBB315_1
5411; PPC64LE-NEXT: .LBB315_3:
5412; PPC64LE-NEXT: mr 3, 5
5413; PPC64LE-NEXT: blr
5414 %ret = atomicrmw umax i64* %ptr, i64 %val monotonic
5415 ret i64 %ret
5416}
5417
5418define i64 @test316(i64* %ptr, i64 %val) {
5419; PPC64LE-LABEL: test316:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5420; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5421; PPC64LE-NEXT: mr 5, 3
5422; PPC64LE-NEXT: .LBB316_1:
5423; PPC64LE-NEXT: ldarx 3, 0, 5
5424; PPC64LE-NEXT: cmpld 4, 3
5425; PPC64LE-NEXT: ble 0, .LBB316_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5426; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5427; PPC64LE-NEXT: stdcx. 4, 0, 5
5428; PPC64LE-NEXT: bne 0, .LBB316_1
5429; PPC64LE-NEXT: .LBB316_3:
5430; PPC64LE-NEXT: lwsync
5431; PPC64LE-NEXT: blr
5432 %ret = atomicrmw umax i64* %ptr, i64 %val acquire
5433 ret i64 %ret
5434}
5435
5436define i64 @test317(i64* %ptr, i64 %val) {
5437; PPC64LE-LABEL: test317:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5438; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5439; PPC64LE-NEXT: lwsync
5440; PPC64LE-NEXT: .LBB317_1:
5441; PPC64LE-NEXT: ldarx 5, 0, 3
5442; PPC64LE-NEXT: cmpld 4, 5
5443; PPC64LE-NEXT: ble 0, .LBB317_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5444; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5445; PPC64LE-NEXT: stdcx. 4, 0, 3
5446; PPC64LE-NEXT: bne 0, .LBB317_1
5447; PPC64LE-NEXT: .LBB317_3:
5448; PPC64LE-NEXT: mr 3, 5
5449; PPC64LE-NEXT: blr
5450 %ret = atomicrmw umax i64* %ptr, i64 %val release
5451 ret i64 %ret
5452}
5453
5454define i64 @test318(i64* %ptr, i64 %val) {
5455; PPC64LE-LABEL: test318:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5456; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5457; PPC64LE-NEXT: lwsync
5458; PPC64LE-NEXT: .LBB318_1:
5459; PPC64LE-NEXT: ldarx 5, 0, 3
5460; PPC64LE-NEXT: cmpld 4, 5
5461; PPC64LE-NEXT: ble 0, .LBB318_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5462; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5463; PPC64LE-NEXT: stdcx. 4, 0, 3
5464; PPC64LE-NEXT: bne 0, .LBB318_1
5465; PPC64LE-NEXT: .LBB318_3:
5466; PPC64LE-NEXT: mr 3, 5
5467; PPC64LE-NEXT: lwsync
5468; PPC64LE-NEXT: blr
5469 %ret = atomicrmw umax i64* %ptr, i64 %val acq_rel
5470 ret i64 %ret
5471}
5472
5473define i64 @test319(i64* %ptr, i64 %val) {
5474; PPC64LE-LABEL: test319:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5475; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5476; PPC64LE-NEXT: sync
5477; PPC64LE-NEXT: .LBB319_1:
5478; PPC64LE-NEXT: ldarx 5, 0, 3
5479; PPC64LE-NEXT: cmpld 4, 5
5480; PPC64LE-NEXT: ble 0, .LBB319_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5481; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5482; PPC64LE-NEXT: stdcx. 4, 0, 3
5483; PPC64LE-NEXT: bne 0, .LBB319_1
5484; PPC64LE-NEXT: .LBB319_3:
5485; PPC64LE-NEXT: mr 3, 5
5486; PPC64LE-NEXT: lwsync
5487; PPC64LE-NEXT: blr
5488 %ret = atomicrmw umax i64* %ptr, i64 %val seq_cst
5489 ret i64 %ret
5490}
5491
5492define i8 @test320(i8* %ptr, i8 %val) {
5493; PPC64LE-LABEL: test320:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5494; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5495; PPC64LE-NEXT: .LBB320_1:
5496; PPC64LE-NEXT: lbarx 5, 0, 3
5497; PPC64LE-NEXT: cmplw 4, 5
5498; PPC64LE-NEXT: bge 0, .LBB320_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5499; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5500; PPC64LE-NEXT: stbcx. 4, 0, 3
5501; PPC64LE-NEXT: bne 0, .LBB320_1
5502; PPC64LE-NEXT: .LBB320_3:
5503; PPC64LE-NEXT: mr 3, 5
5504; PPC64LE-NEXT: blr
5505 %ret = atomicrmw umin i8* %ptr, i8 %val monotonic
5506 ret i8 %ret
5507}
5508
5509define i8 @test321(i8* %ptr, i8 %val) {
5510; PPC64LE-LABEL: test321:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5511; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5512; PPC64LE-NEXT: mr 5, 3
5513; PPC64LE-NEXT: .LBB321_1:
5514; PPC64LE-NEXT: lbarx 3, 0, 5
5515; PPC64LE-NEXT: cmplw 4, 3
5516; PPC64LE-NEXT: bge 0, .LBB321_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5517; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5518; PPC64LE-NEXT: stbcx. 4, 0, 5
5519; PPC64LE-NEXT: bne 0, .LBB321_1
5520; PPC64LE-NEXT: .LBB321_3:
5521; PPC64LE-NEXT: lwsync
5522; PPC64LE-NEXT: blr
5523 %ret = atomicrmw umin i8* %ptr, i8 %val acquire
5524 ret i8 %ret
5525}
5526
5527define i8 @test322(i8* %ptr, i8 %val) {
5528; PPC64LE-LABEL: test322:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5529; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5530; PPC64LE-NEXT: lwsync
5531; PPC64LE-NEXT: .LBB322_1:
5532; PPC64LE-NEXT: lbarx 5, 0, 3
5533; PPC64LE-NEXT: cmplw 4, 5
5534; PPC64LE-NEXT: bge 0, .LBB322_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5535; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5536; PPC64LE-NEXT: stbcx. 4, 0, 3
5537; PPC64LE-NEXT: bne 0, .LBB322_1
5538; PPC64LE-NEXT: .LBB322_3:
5539; PPC64LE-NEXT: mr 3, 5
5540; PPC64LE-NEXT: blr
5541 %ret = atomicrmw umin i8* %ptr, i8 %val release
5542 ret i8 %ret
5543}
5544
5545define i8 @test323(i8* %ptr, i8 %val) {
5546; PPC64LE-LABEL: test323:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5547; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5548; PPC64LE-NEXT: lwsync
5549; PPC64LE-NEXT: .LBB323_1:
5550; PPC64LE-NEXT: lbarx 5, 0, 3
5551; PPC64LE-NEXT: cmplw 4, 5
5552; PPC64LE-NEXT: bge 0, .LBB323_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5553; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5554; PPC64LE-NEXT: stbcx. 4, 0, 3
5555; PPC64LE-NEXT: bne 0, .LBB323_1
5556; PPC64LE-NEXT: .LBB323_3:
5557; PPC64LE-NEXT: mr 3, 5
5558; PPC64LE-NEXT: lwsync
5559; PPC64LE-NEXT: blr
5560 %ret = atomicrmw umin i8* %ptr, i8 %val acq_rel
5561 ret i8 %ret
5562}
5563
5564define i8 @test324(i8* %ptr, i8 %val) {
5565; PPC64LE-LABEL: test324:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5566; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5567; PPC64LE-NEXT: sync
5568; PPC64LE-NEXT: .LBB324_1:
5569; PPC64LE-NEXT: lbarx 5, 0, 3
5570; PPC64LE-NEXT: cmplw 4, 5
5571; PPC64LE-NEXT: bge 0, .LBB324_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5572; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5573; PPC64LE-NEXT: stbcx. 4, 0, 3
5574; PPC64LE-NEXT: bne 0, .LBB324_1
5575; PPC64LE-NEXT: .LBB324_3:
5576; PPC64LE-NEXT: mr 3, 5
5577; PPC64LE-NEXT: lwsync
5578; PPC64LE-NEXT: blr
5579 %ret = atomicrmw umin i8* %ptr, i8 %val seq_cst
5580 ret i8 %ret
5581}
5582
5583define i16 @test325(i16* %ptr, i16 %val) {
5584; PPC64LE-LABEL: test325:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5585; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5586; PPC64LE-NEXT: .LBB325_1:
5587; PPC64LE-NEXT: lharx 5, 0, 3
5588; PPC64LE-NEXT: cmplw 4, 5
5589; PPC64LE-NEXT: bge 0, .LBB325_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5590; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5591; PPC64LE-NEXT: sthcx. 4, 0, 3
5592; PPC64LE-NEXT: bne 0, .LBB325_1
5593; PPC64LE-NEXT: .LBB325_3:
5594; PPC64LE-NEXT: mr 3, 5
5595; PPC64LE-NEXT: blr
5596 %ret = atomicrmw umin i16* %ptr, i16 %val monotonic
5597 ret i16 %ret
5598}
5599
5600define i16 @test326(i16* %ptr, i16 %val) {
5601; PPC64LE-LABEL: test326:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5602; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5603; PPC64LE-NEXT: mr 5, 3
5604; PPC64LE-NEXT: .LBB326_1:
5605; PPC64LE-NEXT: lharx 3, 0, 5
5606; PPC64LE-NEXT: cmplw 4, 3
5607; PPC64LE-NEXT: bge 0, .LBB326_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5608; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5609; PPC64LE-NEXT: sthcx. 4, 0, 5
5610; PPC64LE-NEXT: bne 0, .LBB326_1
5611; PPC64LE-NEXT: .LBB326_3:
5612; PPC64LE-NEXT: lwsync
5613; PPC64LE-NEXT: blr
5614 %ret = atomicrmw umin i16* %ptr, i16 %val acquire
5615 ret i16 %ret
5616}
5617
5618define i16 @test327(i16* %ptr, i16 %val) {
5619; PPC64LE-LABEL: test327:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5620; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5621; PPC64LE-NEXT: lwsync
5622; PPC64LE-NEXT: .LBB327_1:
5623; PPC64LE-NEXT: lharx 5, 0, 3
5624; PPC64LE-NEXT: cmplw 4, 5
5625; PPC64LE-NEXT: bge 0, .LBB327_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5626; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5627; PPC64LE-NEXT: sthcx. 4, 0, 3
5628; PPC64LE-NEXT: bne 0, .LBB327_1
5629; PPC64LE-NEXT: .LBB327_3:
5630; PPC64LE-NEXT: mr 3, 5
5631; PPC64LE-NEXT: blr
5632 %ret = atomicrmw umin i16* %ptr, i16 %val release
5633 ret i16 %ret
5634}
5635
5636define i16 @test328(i16* %ptr, i16 %val) {
5637; PPC64LE-LABEL: test328:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5638; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5639; PPC64LE-NEXT: lwsync
5640; PPC64LE-NEXT: .LBB328_1:
5641; PPC64LE-NEXT: lharx 5, 0, 3
5642; PPC64LE-NEXT: cmplw 4, 5
5643; PPC64LE-NEXT: bge 0, .LBB328_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5644; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5645; PPC64LE-NEXT: sthcx. 4, 0, 3
5646; PPC64LE-NEXT: bne 0, .LBB328_1
5647; PPC64LE-NEXT: .LBB328_3:
5648; PPC64LE-NEXT: mr 3, 5
5649; PPC64LE-NEXT: lwsync
5650; PPC64LE-NEXT: blr
5651 %ret = atomicrmw umin i16* %ptr, i16 %val acq_rel
5652 ret i16 %ret
5653}
5654
5655define i16 @test329(i16* %ptr, i16 %val) {
5656; PPC64LE-LABEL: test329:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5657; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5658; PPC64LE-NEXT: sync
5659; PPC64LE-NEXT: .LBB329_1:
5660; PPC64LE-NEXT: lharx 5, 0, 3
5661; PPC64LE-NEXT: cmplw 4, 5
5662; PPC64LE-NEXT: bge 0, .LBB329_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5663; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5664; PPC64LE-NEXT: sthcx. 4, 0, 3
5665; PPC64LE-NEXT: bne 0, .LBB329_1
5666; PPC64LE-NEXT: .LBB329_3:
5667; PPC64LE-NEXT: mr 3, 5
5668; PPC64LE-NEXT: lwsync
5669; PPC64LE-NEXT: blr
5670 %ret = atomicrmw umin i16* %ptr, i16 %val seq_cst
5671 ret i16 %ret
5672}
5673
5674define i32 @test330(i32* %ptr, i32 %val) {
5675; PPC64LE-LABEL: test330:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5676; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5677; PPC64LE-NEXT: .LBB330_1:
5678; PPC64LE-NEXT: lwarx 5, 0, 3
5679; PPC64LE-NEXT: cmplw 4, 5
5680; PPC64LE-NEXT: bge 0, .LBB330_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5681; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5682; PPC64LE-NEXT: stwcx. 4, 0, 3
5683; PPC64LE-NEXT: bne 0, .LBB330_1
5684; PPC64LE-NEXT: .LBB330_3:
5685; PPC64LE-NEXT: mr 3, 5
5686; PPC64LE-NEXT: blr
5687 %ret = atomicrmw umin i32* %ptr, i32 %val monotonic
5688 ret i32 %ret
5689}
5690
5691define i32 @test331(i32* %ptr, i32 %val) {
5692; PPC64LE-LABEL: test331:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5693; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5694; PPC64LE-NEXT: mr 5, 3
5695; PPC64LE-NEXT: .LBB331_1:
5696; PPC64LE-NEXT: lwarx 3, 0, 5
5697; PPC64LE-NEXT: cmplw 4, 3
5698; PPC64LE-NEXT: bge 0, .LBB331_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5699; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5700; PPC64LE-NEXT: stwcx. 4, 0, 5
5701; PPC64LE-NEXT: bne 0, .LBB331_1
5702; PPC64LE-NEXT: .LBB331_3:
5703; PPC64LE-NEXT: lwsync
5704; PPC64LE-NEXT: blr
5705 %ret = atomicrmw umin i32* %ptr, i32 %val acquire
5706 ret i32 %ret
5707}
5708
5709define i32 @test332(i32* %ptr, i32 %val) {
5710; PPC64LE-LABEL: test332:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5711; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5712; PPC64LE-NEXT: lwsync
5713; PPC64LE-NEXT: .LBB332_1:
5714; PPC64LE-NEXT: lwarx 5, 0, 3
5715; PPC64LE-NEXT: cmplw 4, 5
5716; PPC64LE-NEXT: bge 0, .LBB332_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5717; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5718; PPC64LE-NEXT: stwcx. 4, 0, 3
5719; PPC64LE-NEXT: bne 0, .LBB332_1
5720; PPC64LE-NEXT: .LBB332_3:
5721; PPC64LE-NEXT: mr 3, 5
5722; PPC64LE-NEXT: blr
5723 %ret = atomicrmw umin i32* %ptr, i32 %val release
5724 ret i32 %ret
5725}
5726
5727define i32 @test333(i32* %ptr, i32 %val) {
5728; PPC64LE-LABEL: test333:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5729; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5730; PPC64LE-NEXT: lwsync
5731; PPC64LE-NEXT: .LBB333_1:
5732; PPC64LE-NEXT: lwarx 5, 0, 3
5733; PPC64LE-NEXT: cmplw 4, 5
5734; PPC64LE-NEXT: bge 0, .LBB333_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5735; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5736; PPC64LE-NEXT: stwcx. 4, 0, 3
5737; PPC64LE-NEXT: bne 0, .LBB333_1
5738; PPC64LE-NEXT: .LBB333_3:
5739; PPC64LE-NEXT: mr 3, 5
5740; PPC64LE-NEXT: lwsync
5741; PPC64LE-NEXT: blr
5742 %ret = atomicrmw umin i32* %ptr, i32 %val acq_rel
5743 ret i32 %ret
5744}
5745
5746define i32 @test334(i32* %ptr, i32 %val) {
5747; PPC64LE-LABEL: test334:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5748; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5749; PPC64LE-NEXT: sync
5750; PPC64LE-NEXT: .LBB334_1:
5751; PPC64LE-NEXT: lwarx 5, 0, 3
5752; PPC64LE-NEXT: cmplw 4, 5
5753; PPC64LE-NEXT: bge 0, .LBB334_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5754; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5755; PPC64LE-NEXT: stwcx. 4, 0, 3
5756; PPC64LE-NEXT: bne 0, .LBB334_1
5757; PPC64LE-NEXT: .LBB334_3:
5758; PPC64LE-NEXT: mr 3, 5
5759; PPC64LE-NEXT: lwsync
5760; PPC64LE-NEXT: blr
5761 %ret = atomicrmw umin i32* %ptr, i32 %val seq_cst
5762 ret i32 %ret
5763}
5764
5765define i64 @test335(i64* %ptr, i64 %val) {
5766; PPC64LE-LABEL: test335:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5767; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5768; PPC64LE-NEXT: .LBB335_1:
5769; PPC64LE-NEXT: ldarx 5, 0, 3
5770; PPC64LE-NEXT: cmpld 4, 5
5771; PPC64LE-NEXT: bge 0, .LBB335_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5772; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5773; PPC64LE-NEXT: stdcx. 4, 0, 3
5774; PPC64LE-NEXT: bne 0, .LBB335_1
5775; PPC64LE-NEXT: .LBB335_3:
5776; PPC64LE-NEXT: mr 3, 5
5777; PPC64LE-NEXT: blr
5778 %ret = atomicrmw umin i64* %ptr, i64 %val monotonic
5779 ret i64 %ret
5780}
5781
5782define i64 @test336(i64* %ptr, i64 %val) {
5783; PPC64LE-LABEL: test336:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5784; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5785; PPC64LE-NEXT: mr 5, 3
5786; PPC64LE-NEXT: .LBB336_1:
5787; PPC64LE-NEXT: ldarx 3, 0, 5
5788; PPC64LE-NEXT: cmpld 4, 3
5789; PPC64LE-NEXT: bge 0, .LBB336_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5790; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5791; PPC64LE-NEXT: stdcx. 4, 0, 5
5792; PPC64LE-NEXT: bne 0, .LBB336_1
5793; PPC64LE-NEXT: .LBB336_3:
5794; PPC64LE-NEXT: lwsync
5795; PPC64LE-NEXT: blr
5796 %ret = atomicrmw umin i64* %ptr, i64 %val acquire
5797 ret i64 %ret
5798}
5799
5800define i64 @test337(i64* %ptr, i64 %val) {
5801; PPC64LE-LABEL: test337:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5802; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5803; PPC64LE-NEXT: lwsync
5804; PPC64LE-NEXT: .LBB337_1:
5805; PPC64LE-NEXT: ldarx 5, 0, 3
5806; PPC64LE-NEXT: cmpld 4, 5
5807; PPC64LE-NEXT: bge 0, .LBB337_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5808; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5809; PPC64LE-NEXT: stdcx. 4, 0, 3
5810; PPC64LE-NEXT: bne 0, .LBB337_1
5811; PPC64LE-NEXT: .LBB337_3:
5812; PPC64LE-NEXT: mr 3, 5
5813; PPC64LE-NEXT: blr
5814 %ret = atomicrmw umin i64* %ptr, i64 %val release
5815 ret i64 %ret
5816}
5817
5818define i64 @test338(i64* %ptr, i64 %val) {
5819; PPC64LE-LABEL: test338:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5820; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5821; PPC64LE-NEXT: lwsync
5822; PPC64LE-NEXT: .LBB338_1:
5823; PPC64LE-NEXT: ldarx 5, 0, 3
5824; PPC64LE-NEXT: cmpld 4, 5
5825; PPC64LE-NEXT: bge 0, .LBB338_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5826; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5827; PPC64LE-NEXT: stdcx. 4, 0, 3
5828; PPC64LE-NEXT: bne 0, .LBB338_1
5829; PPC64LE-NEXT: .LBB338_3:
5830; PPC64LE-NEXT: mr 3, 5
5831; PPC64LE-NEXT: lwsync
5832; PPC64LE-NEXT: blr
5833 %ret = atomicrmw umin i64* %ptr, i64 %val acq_rel
5834 ret i64 %ret
5835}
5836
5837define i64 @test339(i64* %ptr, i64 %val) {
5838; PPC64LE-LABEL: test339:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5839; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5840; PPC64LE-NEXT: sync
5841; PPC64LE-NEXT: .LBB339_1:
5842; PPC64LE-NEXT: ldarx 5, 0, 3
5843; PPC64LE-NEXT: cmpld 4, 5
5844; PPC64LE-NEXT: bge 0, .LBB339_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5845; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5846; PPC64LE-NEXT: stdcx. 4, 0, 3
5847; PPC64LE-NEXT: bne 0, .LBB339_1
5848; PPC64LE-NEXT: .LBB339_3:
5849; PPC64LE-NEXT: mr 3, 5
5850; PPC64LE-NEXT: lwsync
5851; PPC64LE-NEXT: blr
5852 %ret = atomicrmw umin i64* %ptr, i64 %val seq_cst
5853 ret i64 %ret
5854}
5855
5856define i8 @test340(i8* %ptr, i8 %val) {
5857; PPC64LE-LABEL: test340:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5858; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5859; PPC64LE-NEXT: .LBB340_1:
5860; PPC64LE-NEXT: lbarx 5, 0, 3
5861; PPC64LE-NEXT: stbcx. 4, 0, 3
5862; PPC64LE-NEXT: bne 0, .LBB340_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5863; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5864; PPC64LE-NEXT: mr 3, 5
5865; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5866 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5867 ret i8 %ret
5868}
5869
5870define i8 @test341(i8* %ptr, i8 %val) {
5871; PPC64LE-LABEL: test341:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5872; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5873; PPC64LE-NEXT: mr 5, 3
5874; PPC64LE-NEXT: .LBB341_1:
5875; PPC64LE-NEXT: lbarx 3, 0, 5
5876; PPC64LE-NEXT: stbcx. 4, 0, 5
5877; PPC64LE-NEXT: bne 0, .LBB341_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5878; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5879; PPC64LE-NEXT: lwsync
5880; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5881 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5882 ret i8 %ret
5883}
5884
5885define i8 @test342(i8* %ptr, i8 %val) {
5886; PPC64LE-LABEL: test342:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5887; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5888; PPC64LE-NEXT: lwsync
5889; PPC64LE-NEXT: .LBB342_1:
5890; PPC64LE-NEXT: lbarx 5, 0, 3
5891; PPC64LE-NEXT: stbcx. 4, 0, 3
5892; PPC64LE-NEXT: bne 0, .LBB342_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5893; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5894; PPC64LE-NEXT: mr 3, 5
5895; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5896 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5897 ret i8 %ret
5898}
5899
5900define i8 @test343(i8* %ptr, i8 %val) {
5901; PPC64LE-LABEL: test343:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5902; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5903; PPC64LE-NEXT: lwsync
5904; PPC64LE-NEXT: .LBB343_1:
5905; PPC64LE-NEXT: lbarx 5, 0, 3
5906; PPC64LE-NEXT: stbcx. 4, 0, 3
5907; PPC64LE-NEXT: bne 0, .LBB343_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5908; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5909; PPC64LE-NEXT: mr 3, 5
5910; PPC64LE-NEXT: lwsync
5911; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5912 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5913 ret i8 %ret
5914}
5915
5916define i8 @test344(i8* %ptr, i8 %val) {
5917; PPC64LE-LABEL: test344:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5918; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5919; PPC64LE-NEXT: sync
5920; PPC64LE-NEXT: .LBB344_1:
5921; PPC64LE-NEXT: lbarx 5, 0, 3
5922; PPC64LE-NEXT: stbcx. 4, 0, 3
5923; PPC64LE-NEXT: bne 0, .LBB344_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5924; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5925; PPC64LE-NEXT: mr 3, 5
5926; PPC64LE-NEXT: lwsync
5927; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5928 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5929 ret i8 %ret
5930}
5931
5932define i16 @test345(i16* %ptr, i16 %val) {
5933; PPC64LE-LABEL: test345:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5934; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5935; PPC64LE-NEXT: .LBB345_1:
5936; PPC64LE-NEXT: lharx 5, 0, 3
5937; PPC64LE-NEXT: sthcx. 4, 0, 3
5938; PPC64LE-NEXT: bne 0, .LBB345_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5939; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5940; PPC64LE-NEXT: mr 3, 5
5941; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5942 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5943 ret i16 %ret
5944}
5945
5946define i16 @test346(i16* %ptr, i16 %val) {
5947; PPC64LE-LABEL: test346:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5948; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5949; PPC64LE-NEXT: mr 5, 3
5950; PPC64LE-NEXT: .LBB346_1:
5951; PPC64LE-NEXT: lharx 3, 0, 5
5952; PPC64LE-NEXT: sthcx. 4, 0, 5
5953; PPC64LE-NEXT: bne 0, .LBB346_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5954; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5955; PPC64LE-NEXT: lwsync
5956; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5957 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5958 ret i16 %ret
5959}
5960
5961define i16 @test347(i16* %ptr, i16 %val) {
5962; PPC64LE-LABEL: test347:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5963; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5964; PPC64LE-NEXT: lwsync
5965; PPC64LE-NEXT: .LBB347_1:
5966; PPC64LE-NEXT: lharx 5, 0, 3
5967; PPC64LE-NEXT: sthcx. 4, 0, 3
5968; PPC64LE-NEXT: bne 0, .LBB347_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5969; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5970; PPC64LE-NEXT: mr 3, 5
5971; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5972 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5973 ret i16 %ret
5974}
5975
5976define i16 @test348(i16* %ptr, i16 %val) {
5977; PPC64LE-LABEL: test348:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5978; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5979; PPC64LE-NEXT: lwsync
5980; PPC64LE-NEXT: .LBB348_1:
5981; PPC64LE-NEXT: lharx 5, 0, 3
5982; PPC64LE-NEXT: sthcx. 4, 0, 3
5983; PPC64LE-NEXT: bne 0, .LBB348_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5984; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5985; PPC64LE-NEXT: mr 3, 5
5986; PPC64LE-NEXT: lwsync
5987; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5988 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5989 ret i16 %ret
5990}
5991
5992define i16 @test349(i16* %ptr, i16 %val) {
5993; PPC64LE-LABEL: test349:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]5994; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5995; PPC64LE-NEXT: sync
5996; PPC64LE-NEXT: .LBB349_1:
5997; PPC64LE-NEXT: lharx 5, 0, 3
5998; PPC64LE-NEXT: sthcx. 4, 0, 3
5999; PPC64LE-NEXT: bne 0, .LBB349_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6000; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6001; PPC64LE-NEXT: mr 3, 5
6002; PPC64LE-NEXT: lwsync
6003; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6004 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6005 ret i16 %ret
6006}
6007
6008define i32 @test350(i32* %ptr, i32 %val) {
6009; PPC64LE-LABEL: test350:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6010; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6011; PPC64LE-NEXT: .LBB350_1:
6012; PPC64LE-NEXT: lwarx 5, 0, 3
6013; PPC64LE-NEXT: stwcx. 4, 0, 3
6014; PPC64LE-NEXT: bne 0, .LBB350_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6015; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6016; PPC64LE-NEXT: mr 3, 5
6017; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6018 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6019 ret i32 %ret
6020}
6021
6022define i32 @test351(i32* %ptr, i32 %val) {
6023; PPC64LE-LABEL: test351:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6024; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6025; PPC64LE-NEXT: mr 5, 3
6026; PPC64LE-NEXT: .LBB351_1:
6027; PPC64LE-NEXT: lwarx 3, 0, 5
6028; PPC64LE-NEXT: stwcx. 4, 0, 5
6029; PPC64LE-NEXT: bne 0, .LBB351_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6030; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6031; PPC64LE-NEXT: lwsync
6032; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6033 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6034 ret i32 %ret
6035}
6036
6037define i32 @test352(i32* %ptr, i32 %val) {
6038; PPC64LE-LABEL: test352:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6039; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6040; PPC64LE-NEXT: lwsync
6041; PPC64LE-NEXT: .LBB352_1:
6042; PPC64LE-NEXT: lwarx 5, 0, 3
6043; PPC64LE-NEXT: stwcx. 4, 0, 3
6044; PPC64LE-NEXT: bne 0, .LBB352_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6045; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6046; PPC64LE-NEXT: mr 3, 5
6047; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6048 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6049 ret i32 %ret
6050}
6051
6052define i32 @test353(i32* %ptr, i32 %val) {
6053; PPC64LE-LABEL: test353:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6054; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6055; PPC64LE-NEXT: lwsync
6056; PPC64LE-NEXT: .LBB353_1:
6057; PPC64LE-NEXT: lwarx 5, 0, 3
6058; PPC64LE-NEXT: stwcx. 4, 0, 3
6059; PPC64LE-NEXT: bne 0, .LBB353_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6060; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6061; PPC64LE-NEXT: mr 3, 5
6062; PPC64LE-NEXT: lwsync
6063; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6064 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6065 ret i32 %ret
6066}
6067
6068define i32 @test354(i32* %ptr, i32 %val) {
6069; PPC64LE-LABEL: test354:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6070; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6071; PPC64LE-NEXT: sync
6072; PPC64LE-NEXT: .LBB354_1:
6073; PPC64LE-NEXT: lwarx 5, 0, 3
6074; PPC64LE-NEXT: stwcx. 4, 0, 3
6075; PPC64LE-NEXT: bne 0, .LBB354_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6076; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6077; PPC64LE-NEXT: mr 3, 5
6078; PPC64LE-NEXT: lwsync
6079; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6080 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6081 ret i32 %ret
6082}
6083
6084define i64 @test355(i64* %ptr, i64 %val) {
6085; PPC64LE-LABEL: test355:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6086; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6087; PPC64LE-NEXT: .LBB355_1:
6088; PPC64LE-NEXT: ldarx 5, 0, 3
6089; PPC64LE-NEXT: stdcx. 4, 0, 3
6090; PPC64LE-NEXT: bne 0, .LBB355_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6091; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6092; PPC64LE-NEXT: mr 3, 5
6093; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6094 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6095 ret i64 %ret
6096}
6097
6098define i64 @test356(i64* %ptr, i64 %val) {
6099; PPC64LE-LABEL: test356:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6100; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6101; PPC64LE-NEXT: mr 5, 3
6102; PPC64LE-NEXT: .LBB356_1:
6103; PPC64LE-NEXT: ldarx 3, 0, 5
6104; PPC64LE-NEXT: stdcx. 4, 0, 5
6105; PPC64LE-NEXT: bne 0, .LBB356_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6106; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6107; PPC64LE-NEXT: lwsync
6108; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6109 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6110 ret i64 %ret
6111}
6112
6113define i64 @test357(i64* %ptr, i64 %val) {
6114; PPC64LE-LABEL: test357:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6115; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6116; PPC64LE-NEXT: lwsync
6117; PPC64LE-NEXT: .LBB357_1:
6118; PPC64LE-NEXT: ldarx 5, 0, 3
6119; PPC64LE-NEXT: stdcx. 4, 0, 3
6120; PPC64LE-NEXT: bne 0, .LBB357_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6121; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6122; PPC64LE-NEXT: mr 3, 5
6123; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6124 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6125 ret i64 %ret
6126}
6127
6128define i64 @test358(i64* %ptr, i64 %val) {
6129; PPC64LE-LABEL: test358:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6130; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6131; PPC64LE-NEXT: lwsync
6132; PPC64LE-NEXT: .LBB358_1:
6133; PPC64LE-NEXT: ldarx 5, 0, 3
6134; PPC64LE-NEXT: stdcx. 4, 0, 3
6135; PPC64LE-NEXT: bne 0, .LBB358_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6136; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6137; PPC64LE-NEXT: mr 3, 5
6138; PPC64LE-NEXT: lwsync
6139; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6140 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6141 ret i64 %ret
6142}
6143
6144define i64 @test359(i64* %ptr, i64 %val) {
6145; PPC64LE-LABEL: test359:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6146; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6147; PPC64LE-NEXT: sync
6148; PPC64LE-NEXT: .LBB359_1:
6149; PPC64LE-NEXT: ldarx 5, 0, 3
6150; PPC64LE-NEXT: stdcx. 4, 0, 3
6151; PPC64LE-NEXT: bne 0, .LBB359_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6152; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6153; PPC64LE-NEXT: mr 3, 5
6154; PPC64LE-NEXT: lwsync
6155; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6156 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6157 ret i64 %ret
6158}
6159
6160define i8 @test360(i8* %ptr, i8 %val) {
6161; PPC64LE-LABEL: test360:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6162; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6163; PPC64LE-NEXT: .LBB360_1:
6164; PPC64LE-NEXT: lbarx 5, 0, 3
6165; PPC64LE-NEXT: add 6, 4, 5
6166; PPC64LE-NEXT: stbcx. 6, 0, 3
6167; PPC64LE-NEXT: bne 0, .LBB360_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6168; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6169; PPC64LE-NEXT: mr 3, 5
6170; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6171 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6172 ret i8 %ret
6173}
6174
6175define i8 @test361(i8* %ptr, i8 %val) {
6176; PPC64LE-LABEL: test361:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6177; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6178; PPC64LE-NEXT: mr 5, 3
6179; PPC64LE-NEXT: .LBB361_1:
6180; PPC64LE-NEXT: lbarx 3, 0, 5
6181; PPC64LE-NEXT: add 6, 4, 3
6182; PPC64LE-NEXT: stbcx. 6, 0, 5
6183; PPC64LE-NEXT: bne 0, .LBB361_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6184; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6185; PPC64LE-NEXT: lwsync
6186; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6187 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6188 ret i8 %ret
6189}
6190
6191define i8 @test362(i8* %ptr, i8 %val) {
6192; PPC64LE-LABEL: test362:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6193; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6194; PPC64LE-NEXT: lwsync
6195; PPC64LE-NEXT: .LBB362_1:
6196; PPC64LE-NEXT: lbarx 5, 0, 3
6197; PPC64LE-NEXT: add 6, 4, 5
6198; PPC64LE-NEXT: stbcx. 6, 0, 3
6199; PPC64LE-NEXT: bne 0, .LBB362_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6200; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6201; PPC64LE-NEXT: mr 3, 5
6202; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6203 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6204 ret i8 %ret
6205}
6206
6207define i8 @test363(i8* %ptr, i8 %val) {
6208; PPC64LE-LABEL: test363:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6209; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6210; PPC64LE-NEXT: lwsync
6211; PPC64LE-NEXT: .LBB363_1:
6212; PPC64LE-NEXT: lbarx 5, 0, 3
6213; PPC64LE-NEXT: add 6, 4, 5
6214; PPC64LE-NEXT: stbcx. 6, 0, 3
6215; PPC64LE-NEXT: bne 0, .LBB363_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6216; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6217; PPC64LE-NEXT: mr 3, 5
6218; PPC64LE-NEXT: lwsync
6219; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6220 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6221 ret i8 %ret
6222}
6223
6224define i8 @test364(i8* %ptr, i8 %val) {
6225; PPC64LE-LABEL: test364:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6226; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6227; PPC64LE-NEXT: sync
6228; PPC64LE-NEXT: .LBB364_1:
6229; PPC64LE-NEXT: lbarx 5, 0, 3
6230; PPC64LE-NEXT: add 6, 4, 5
6231; PPC64LE-NEXT: stbcx. 6, 0, 3
6232; PPC64LE-NEXT: bne 0, .LBB364_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6233; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6234; PPC64LE-NEXT: mr 3, 5
6235; PPC64LE-NEXT: lwsync
6236; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6237 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6238 ret i8 %ret
6239}
6240
6241define i16 @test365(i16* %ptr, i16 %val) {
6242; PPC64LE-LABEL: test365:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6243; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6244; PPC64LE-NEXT: .LBB365_1:
6245; PPC64LE-NEXT: lharx 5, 0, 3
6246; PPC64LE-NEXT: add 6, 4, 5
6247; PPC64LE-NEXT: sthcx. 6, 0, 3
6248; PPC64LE-NEXT: bne 0, .LBB365_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6249; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6250; PPC64LE-NEXT: mr 3, 5
6251; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6252 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6253 ret i16 %ret
6254}
6255
6256define i16 @test366(i16* %ptr, i16 %val) {
6257; PPC64LE-LABEL: test366:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6258; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6259; PPC64LE-NEXT: mr 5, 3
6260; PPC64LE-NEXT: .LBB366_1:
6261; PPC64LE-NEXT: lharx 3, 0, 5
6262; PPC64LE-NEXT: add 6, 4, 3
6263; PPC64LE-NEXT: sthcx. 6, 0, 5
6264; PPC64LE-NEXT: bne 0, .LBB366_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6265; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6266; PPC64LE-NEXT: lwsync
6267; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6268 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6269 ret i16 %ret
6270}
6271
6272define i16 @test367(i16* %ptr, i16 %val) {
6273; PPC64LE-LABEL: test367:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6274; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6275; PPC64LE-NEXT: lwsync
6276; PPC64LE-NEXT: .LBB367_1:
6277; PPC64LE-NEXT: lharx 5, 0, 3
6278; PPC64LE-NEXT: add 6, 4, 5
6279; PPC64LE-NEXT: sthcx. 6, 0, 3
6280; PPC64LE-NEXT: bne 0, .LBB367_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6281; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6282; PPC64LE-NEXT: mr 3, 5
6283; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6284 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6285 ret i16 %ret
6286}
6287
6288define i16 @test368(i16* %ptr, i16 %val) {
6289; PPC64LE-LABEL: test368:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6290; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6291; PPC64LE-NEXT: lwsync
6292; PPC64LE-NEXT: .LBB368_1:
6293; PPC64LE-NEXT: lharx 5, 0, 3
6294; PPC64LE-NEXT: add 6, 4, 5
6295; PPC64LE-NEXT: sthcx. 6, 0, 3
6296; PPC64LE-NEXT: bne 0, .LBB368_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6297; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6298; PPC64LE-NEXT: mr 3, 5
6299; PPC64LE-NEXT: lwsync
6300; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6301 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6302 ret i16 %ret
6303}
6304
6305define i16 @test369(i16* %ptr, i16 %val) {
6306; PPC64LE-LABEL: test369:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6307; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6308; PPC64LE-NEXT: sync
6309; PPC64LE-NEXT: .LBB369_1:
6310; PPC64LE-NEXT: lharx 5, 0, 3
6311; PPC64LE-NEXT: add 6, 4, 5
6312; PPC64LE-NEXT: sthcx. 6, 0, 3
6313; PPC64LE-NEXT: bne 0, .LBB369_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6314; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6315; PPC64LE-NEXT: mr 3, 5
6316; PPC64LE-NEXT: lwsync
6317; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6318 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6319 ret i16 %ret
6320}
6321
6322define i32 @test370(i32* %ptr, i32 %val) {
6323; PPC64LE-LABEL: test370:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6324; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6325; PPC64LE-NEXT: .LBB370_1:
6326; PPC64LE-NEXT: lwarx 5, 0, 3
6327; PPC64LE-NEXT: add 6, 4, 5
6328; PPC64LE-NEXT: stwcx. 6, 0, 3
6329; PPC64LE-NEXT: bne 0, .LBB370_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6330; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6331; PPC64LE-NEXT: mr 3, 5
6332; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6333 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6334 ret i32 %ret
6335}
6336
6337define i32 @test371(i32* %ptr, i32 %val) {
6338; PPC64LE-LABEL: test371:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6339; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6340; PPC64LE-NEXT: mr 5, 3
6341; PPC64LE-NEXT: .LBB371_1:
6342; PPC64LE-NEXT: lwarx 3, 0, 5
6343; PPC64LE-NEXT: add 6, 4, 3
6344; PPC64LE-NEXT: stwcx. 6, 0, 5
6345; PPC64LE-NEXT: bne 0, .LBB371_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6346; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6347; PPC64LE-NEXT: lwsync
6348; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6349 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6350 ret i32 %ret
6351}
6352
6353define i32 @test372(i32* %ptr, i32 %val) {
6354; PPC64LE-LABEL: test372:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6355; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6356; PPC64LE-NEXT: lwsync
6357; PPC64LE-NEXT: .LBB372_1:
6358; PPC64LE-NEXT: lwarx 5, 0, 3
6359; PPC64LE-NEXT: add 6, 4, 5
6360; PPC64LE-NEXT: stwcx. 6, 0, 3
6361; PPC64LE-NEXT: bne 0, .LBB372_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6362; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6363; PPC64LE-NEXT: mr 3, 5
6364; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6365 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6366 ret i32 %ret
6367}
6368
6369define i32 @test373(i32* %ptr, i32 %val) {
6370; PPC64LE-LABEL: test373:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6371; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6372; PPC64LE-NEXT: lwsync
6373; PPC64LE-NEXT: .LBB373_1:
6374; PPC64LE-NEXT: lwarx 5, 0, 3
6375; PPC64LE-NEXT: add 6, 4, 5
6376; PPC64LE-NEXT: stwcx. 6, 0, 3
6377; PPC64LE-NEXT: bne 0, .LBB373_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6378; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6379; PPC64LE-NEXT: mr 3, 5
6380; PPC64LE-NEXT: lwsync
6381; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6382 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6383 ret i32 %ret
6384}
6385
6386define i32 @test374(i32* %ptr, i32 %val) {
6387; PPC64LE-LABEL: test374:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6388; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6389; PPC64LE-NEXT: sync
6390; PPC64LE-NEXT: .LBB374_1:
6391; PPC64LE-NEXT: lwarx 5, 0, 3
6392; PPC64LE-NEXT: add 6, 4, 5
6393; PPC64LE-NEXT: stwcx. 6, 0, 3
6394; PPC64LE-NEXT: bne 0, .LBB374_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6395; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6396; PPC64LE-NEXT: mr 3, 5
6397; PPC64LE-NEXT: lwsync
6398; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6399 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6400 ret i32 %ret
6401}
6402
6403define i64 @test375(i64* %ptr, i64 %val) {
6404; PPC64LE-LABEL: test375:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6405; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6406; PPC64LE-NEXT: .LBB375_1:
6407; PPC64LE-NEXT: ldarx 5, 0, 3
6408; PPC64LE-NEXT: add 6, 4, 5
6409; PPC64LE-NEXT: stdcx. 6, 0, 3
6410; PPC64LE-NEXT: bne 0, .LBB375_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6411; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6412; PPC64LE-NEXT: mr 3, 5
6413; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6414 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6415 ret i64 %ret
6416}
6417
6418define i64 @test376(i64* %ptr, i64 %val) {
6419; PPC64LE-LABEL: test376:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6420; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6421; PPC64LE-NEXT: mr 5, 3
6422; PPC64LE-NEXT: .LBB376_1:
6423; PPC64LE-NEXT: ldarx 3, 0, 5
6424; PPC64LE-NEXT: add 6, 4, 3
6425; PPC64LE-NEXT: stdcx. 6, 0, 5
6426; PPC64LE-NEXT: bne 0, .LBB376_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6427; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6428; PPC64LE-NEXT: lwsync
6429; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6430 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6431 ret i64 %ret
6432}
6433
6434define i64 @test377(i64* %ptr, i64 %val) {
6435; PPC64LE-LABEL: test377:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6436; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6437; PPC64LE-NEXT: lwsync
6438; PPC64LE-NEXT: .LBB377_1:
6439; PPC64LE-NEXT: ldarx 5, 0, 3
6440; PPC64LE-NEXT: add 6, 4, 5
6441; PPC64LE-NEXT: stdcx. 6, 0, 3
6442; PPC64LE-NEXT: bne 0, .LBB377_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6443; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6444; PPC64LE-NEXT: mr 3, 5
6445; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6446 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6447 ret i64 %ret
6448}
6449
6450define i64 @test378(i64* %ptr, i64 %val) {
6451; PPC64LE-LABEL: test378:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6452; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6453; PPC64LE-NEXT: lwsync
6454; PPC64LE-NEXT: .LBB378_1:
6455; PPC64LE-NEXT: ldarx 5, 0, 3
6456; PPC64LE-NEXT: add 6, 4, 5
6457; PPC64LE-NEXT: stdcx. 6, 0, 3
6458; PPC64LE-NEXT: bne 0, .LBB378_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6459; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6460; PPC64LE-NEXT: mr 3, 5
6461; PPC64LE-NEXT: lwsync
6462; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6463 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6464 ret i64 %ret
6465}
6466
6467define i64 @test379(i64* %ptr, i64 %val) {
6468; PPC64LE-LABEL: test379:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6469; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6470; PPC64LE-NEXT: sync
6471; PPC64LE-NEXT: .LBB379_1:
6472; PPC64LE-NEXT: ldarx 5, 0, 3
6473; PPC64LE-NEXT: add 6, 4, 5
6474; PPC64LE-NEXT: stdcx. 6, 0, 3
6475; PPC64LE-NEXT: bne 0, .LBB379_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6476; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6477; PPC64LE-NEXT: mr 3, 5
6478; PPC64LE-NEXT: lwsync
6479; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6480 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6481 ret i64 %ret
6482}
6483
6484define i8 @test380(i8* %ptr, i8 %val) {
6485; PPC64LE-LABEL: test380:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6486; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6487; PPC64LE-NEXT: .LBB380_1:
6488; PPC64LE-NEXT: lbarx 5, 0, 3
6489; PPC64LE-NEXT: subf 6, 4, 5
6490; PPC64LE-NEXT: stbcx. 6, 0, 3
6491; PPC64LE-NEXT: bne 0, .LBB380_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6492; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6493; PPC64LE-NEXT: mr 3, 5
6494; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6495 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6496 ret i8 %ret
6497}
6498
6499define i8 @test381(i8* %ptr, i8 %val) {
6500; PPC64LE-LABEL: test381:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6501; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6502; PPC64LE-NEXT: mr 5, 3
6503; PPC64LE-NEXT: .LBB381_1:
6504; PPC64LE-NEXT: lbarx 3, 0, 5
6505; PPC64LE-NEXT: subf 6, 4, 3
6506; PPC64LE-NEXT: stbcx. 6, 0, 5
6507; PPC64LE-NEXT: bne 0, .LBB381_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6508; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6509; PPC64LE-NEXT: lwsync
6510; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6511 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6512 ret i8 %ret
6513}
6514
6515define i8 @test382(i8* %ptr, i8 %val) {
6516; PPC64LE-LABEL: test382:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6517; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6518; PPC64LE-NEXT: lwsync
6519; PPC64LE-NEXT: .LBB382_1:
6520; PPC64LE-NEXT: lbarx 5, 0, 3
6521; PPC64LE-NEXT: subf 6, 4, 5
6522; PPC64LE-NEXT: stbcx. 6, 0, 3
6523; PPC64LE-NEXT: bne 0, .LBB382_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6524; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6525; PPC64LE-NEXT: mr 3, 5
6526; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6527 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6528 ret i8 %ret
6529}
6530
6531define i8 @test383(i8* %ptr, i8 %val) {
6532; PPC64LE-LABEL: test383:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6533; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6534; PPC64LE-NEXT: lwsync
6535; PPC64LE-NEXT: .LBB383_1:
6536; PPC64LE-NEXT: lbarx 5, 0, 3
6537; PPC64LE-NEXT: subf 6, 4, 5
6538; PPC64LE-NEXT: stbcx. 6, 0, 3
6539; PPC64LE-NEXT: bne 0, .LBB383_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6540; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6541; PPC64LE-NEXT: mr 3, 5
6542; PPC64LE-NEXT: lwsync
6543; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6544 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6545 ret i8 %ret
6546}
6547
6548define i8 @test384(i8* %ptr, i8 %val) {
6549; PPC64LE-LABEL: test384:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6550; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6551; PPC64LE-NEXT: sync
6552; PPC64LE-NEXT: .LBB384_1:
6553; PPC64LE-NEXT: lbarx 5, 0, 3
6554; PPC64LE-NEXT: subf 6, 4, 5
6555; PPC64LE-NEXT: stbcx. 6, 0, 3
6556; PPC64LE-NEXT: bne 0, .LBB384_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6557; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6558; PPC64LE-NEXT: mr 3, 5
6559; PPC64LE-NEXT: lwsync
6560; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6561 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6562 ret i8 %ret
6563}
6564
6565define i16 @test385(i16* %ptr, i16 %val) {
6566; PPC64LE-LABEL: test385:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6567; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6568; PPC64LE-NEXT: .LBB385_1:
6569; PPC64LE-NEXT: lharx 5, 0, 3
6570; PPC64LE-NEXT: subf 6, 4, 5
6571; PPC64LE-NEXT: sthcx. 6, 0, 3
6572; PPC64LE-NEXT: bne 0, .LBB385_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6573; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6574; PPC64LE-NEXT: mr 3, 5
6575; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6576 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6577 ret i16 %ret
6578}
6579
6580define i16 @test386(i16* %ptr, i16 %val) {
6581; PPC64LE-LABEL: test386:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6582; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6583; PPC64LE-NEXT: mr 5, 3
6584; PPC64LE-NEXT: .LBB386_1:
6585; PPC64LE-NEXT: lharx 3, 0, 5
6586; PPC64LE-NEXT: subf 6, 4, 3
6587; PPC64LE-NEXT: sthcx. 6, 0, 5
6588; PPC64LE-NEXT: bne 0, .LBB386_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6589; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6590; PPC64LE-NEXT: lwsync
6591; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6592 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6593 ret i16 %ret
6594}
6595
6596define i16 @test387(i16* %ptr, i16 %val) {
6597; PPC64LE-LABEL: test387:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6598; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6599; PPC64LE-NEXT: lwsync
6600; PPC64LE-NEXT: .LBB387_1:
6601; PPC64LE-NEXT: lharx 5, 0, 3
6602; PPC64LE-NEXT: subf 6, 4, 5
6603; PPC64LE-NEXT: sthcx. 6, 0, 3
6604; PPC64LE-NEXT: bne 0, .LBB387_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6605; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6606; PPC64LE-NEXT: mr 3, 5
6607; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6608 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6609 ret i16 %ret
6610}
6611
6612define i16 @test388(i16* %ptr, i16 %val) {
6613; PPC64LE-LABEL: test388:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6614; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6615; PPC64LE-NEXT: lwsync
6616; PPC64LE-NEXT: .LBB388_1:
6617; PPC64LE-NEXT: lharx 5, 0, 3
6618; PPC64LE-NEXT: subf 6, 4, 5
6619; PPC64LE-NEXT: sthcx. 6, 0, 3
6620; PPC64LE-NEXT: bne 0, .LBB388_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6621; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6622; PPC64LE-NEXT: mr 3, 5
6623; PPC64LE-NEXT: lwsync
6624; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6625 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6626 ret i16 %ret
6627}
6628
6629define i16 @test389(i16* %ptr, i16 %val) {
6630; PPC64LE-LABEL: test389:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6631; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6632; PPC64LE-NEXT: sync
6633; PPC64LE-NEXT: .LBB389_1:
6634; PPC64LE-NEXT: lharx 5, 0, 3
6635; PPC64LE-NEXT: subf 6, 4, 5
6636; PPC64LE-NEXT: sthcx. 6, 0, 3
6637; PPC64LE-NEXT: bne 0, .LBB389_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6638; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6639; PPC64LE-NEXT: mr 3, 5
6640; PPC64LE-NEXT: lwsync
6641; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6642 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6643 ret i16 %ret
6644}
6645
6646define i32 @test390(i32* %ptr, i32 %val) {
6647; PPC64LE-LABEL: test390:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6648; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6649; PPC64LE-NEXT: .LBB390_1:
6650; PPC64LE-NEXT: lwarx 5, 0, 3
6651; PPC64LE-NEXT: subf 6, 4, 5
6652; PPC64LE-NEXT: stwcx. 6, 0, 3
6653; PPC64LE-NEXT: bne 0, .LBB390_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6654; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6655; PPC64LE-NEXT: mr 3, 5
6656; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6657 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6658 ret i32 %ret
6659}
6660
6661define i32 @test391(i32* %ptr, i32 %val) {
6662; PPC64LE-LABEL: test391:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6663; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6664; PPC64LE-NEXT: mr 5, 3
6665; PPC64LE-NEXT: .LBB391_1:
6666; PPC64LE-NEXT: lwarx 3, 0, 5
6667; PPC64LE-NEXT: subf 6, 4, 3
6668; PPC64LE-NEXT: stwcx. 6, 0, 5
6669; PPC64LE-NEXT: bne 0, .LBB391_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6670; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6671; PPC64LE-NEXT: lwsync
6672; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6673 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6674 ret i32 %ret
6675}
6676
6677define i32 @test392(i32* %ptr, i32 %val) {
6678; PPC64LE-LABEL: test392:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6679; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6680; PPC64LE-NEXT: lwsync
6681; PPC64LE-NEXT: .LBB392_1:
6682; PPC64LE-NEXT: lwarx 5, 0, 3
6683; PPC64LE-NEXT: subf 6, 4, 5
6684; PPC64LE-NEXT: stwcx. 6, 0, 3
6685; PPC64LE-NEXT: bne 0, .LBB392_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6686; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6687; PPC64LE-NEXT: mr 3, 5
6688; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6689 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6690 ret i32 %ret
6691}
6692
6693define i32 @test393(i32* %ptr, i32 %val) {
6694; PPC64LE-LABEL: test393:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6695; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6696; PPC64LE-NEXT: lwsync
6697; PPC64LE-NEXT: .LBB393_1:
6698; PPC64LE-NEXT: lwarx 5, 0, 3
6699; PPC64LE-NEXT: subf 6, 4, 5
6700; PPC64LE-NEXT: stwcx. 6, 0, 3
6701; PPC64LE-NEXT: bne 0, .LBB393_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6702; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6703; PPC64LE-NEXT: mr 3, 5
6704; PPC64LE-NEXT: lwsync
6705; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6706 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6707 ret i32 %ret
6708}
6709
6710define i32 @test394(i32* %ptr, i32 %val) {
6711; PPC64LE-LABEL: test394:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6712; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6713; PPC64LE-NEXT: sync
6714; PPC64LE-NEXT: .LBB394_1:
6715; PPC64LE-NEXT: lwarx 5, 0, 3
6716; PPC64LE-NEXT: subf 6, 4, 5
6717; PPC64LE-NEXT: stwcx. 6, 0, 3
6718; PPC64LE-NEXT: bne 0, .LBB394_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6719; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6720; PPC64LE-NEXT: mr 3, 5
6721; PPC64LE-NEXT: lwsync
6722; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6723 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6724 ret i32 %ret
6725}
6726
6727define i64 @test395(i64* %ptr, i64 %val) {
6728; PPC64LE-LABEL: test395:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6729; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6730; PPC64LE-NEXT: .LBB395_1:
6731; PPC64LE-NEXT: ldarx 5, 0, 3
6732; PPC64LE-NEXT: sub 6, 5, 4
6733; PPC64LE-NEXT: stdcx. 6, 0, 3
6734; PPC64LE-NEXT: bne 0, .LBB395_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6735; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6736; PPC64LE-NEXT: mr 3, 5
6737; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6738 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6739 ret i64 %ret
6740}
6741
6742define i64 @test396(i64* %ptr, i64 %val) {
6743; PPC64LE-LABEL: test396:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6744; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6745; PPC64LE-NEXT: mr 5, 3
6746; PPC64LE-NEXT: .LBB396_1:
6747; PPC64LE-NEXT: ldarx 3, 0, 5
6748; PPC64LE-NEXT: sub 6, 3, 4
6749; PPC64LE-NEXT: stdcx. 6, 0, 5
6750; PPC64LE-NEXT: bne 0, .LBB396_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6751; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6752; PPC64LE-NEXT: lwsync
6753; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6754 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6755 ret i64 %ret
6756}
6757
6758define i64 @test397(i64* %ptr, i64 %val) {
6759; PPC64LE-LABEL: test397:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6760; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6761; PPC64LE-NEXT: lwsync
6762; PPC64LE-NEXT: .LBB397_1:
6763; PPC64LE-NEXT: ldarx 5, 0, 3
6764; PPC64LE-NEXT: sub 6, 5, 4
6765; PPC64LE-NEXT: stdcx. 6, 0, 3
6766; PPC64LE-NEXT: bne 0, .LBB397_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6767; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6768; PPC64LE-NEXT: mr 3, 5
6769; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6770 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6771 ret i64 %ret
6772}
6773
6774define i64 @test398(i64* %ptr, i64 %val) {
6775; PPC64LE-LABEL: test398:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6776; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6777; PPC64LE-NEXT: lwsync
6778; PPC64LE-NEXT: .LBB398_1:
6779; PPC64LE-NEXT: ldarx 5, 0, 3
6780; PPC64LE-NEXT: sub 6, 5, 4
6781; PPC64LE-NEXT: stdcx. 6, 0, 3
6782; PPC64LE-NEXT: bne 0, .LBB398_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6783; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6784; PPC64LE-NEXT: mr 3, 5
6785; PPC64LE-NEXT: lwsync
6786; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6787 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6788 ret i64 %ret
6789}
6790
6791define i64 @test399(i64* %ptr, i64 %val) {
6792; PPC64LE-LABEL: test399:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6793; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6794; PPC64LE-NEXT: sync
6795; PPC64LE-NEXT: .LBB399_1:
6796; PPC64LE-NEXT: ldarx 5, 0, 3
6797; PPC64LE-NEXT: sub 6, 5, 4
6798; PPC64LE-NEXT: stdcx. 6, 0, 3
6799; PPC64LE-NEXT: bne 0, .LBB399_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6800; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6801; PPC64LE-NEXT: mr 3, 5
6802; PPC64LE-NEXT: lwsync
6803; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6804 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6805 ret i64 %ret
6806}
6807
6808define i8 @test400(i8* %ptr, i8 %val) {
6809; PPC64LE-LABEL: test400:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6810; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6811; PPC64LE-NEXT: .LBB400_1:
6812; PPC64LE-NEXT: lbarx 5, 0, 3
6813; PPC64LE-NEXT: and 6, 4, 5
6814; PPC64LE-NEXT: stbcx. 6, 0, 3
6815; PPC64LE-NEXT: bne 0, .LBB400_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6816; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6817; PPC64LE-NEXT: mr 3, 5
6818; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6819 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6820 ret i8 %ret
6821}
6822
6823define i8 @test401(i8* %ptr, i8 %val) {
6824; PPC64LE-LABEL: test401:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6825; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6826; PPC64LE-NEXT: mr 5, 3
6827; PPC64LE-NEXT: .LBB401_1:
6828; PPC64LE-NEXT: lbarx 3, 0, 5
6829; PPC64LE-NEXT: and 6, 4, 3
6830; PPC64LE-NEXT: stbcx. 6, 0, 5
6831; PPC64LE-NEXT: bne 0, .LBB401_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6832; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6833; PPC64LE-NEXT: lwsync
6834; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6835 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6836 ret i8 %ret
6837}
6838
6839define i8 @test402(i8* %ptr, i8 %val) {
6840; PPC64LE-LABEL: test402:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6841; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6842; PPC64LE-NEXT: lwsync
6843; PPC64LE-NEXT: .LBB402_1:
6844; PPC64LE-NEXT: lbarx 5, 0, 3
6845; PPC64LE-NEXT: and 6, 4, 5
6846; PPC64LE-NEXT: stbcx. 6, 0, 3
6847; PPC64LE-NEXT: bne 0, .LBB402_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6848; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6849; PPC64LE-NEXT: mr 3, 5
6850; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6851 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6852 ret i8 %ret
6853}
6854
6855define i8 @test403(i8* %ptr, i8 %val) {
6856; PPC64LE-LABEL: test403:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6857; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6858; PPC64LE-NEXT: lwsync
6859; PPC64LE-NEXT: .LBB403_1:
6860; PPC64LE-NEXT: lbarx 5, 0, 3
6861; PPC64LE-NEXT: and 6, 4, 5
6862; PPC64LE-NEXT: stbcx. 6, 0, 3
6863; PPC64LE-NEXT: bne 0, .LBB403_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6864; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6865; PPC64LE-NEXT: mr 3, 5
6866; PPC64LE-NEXT: lwsync
6867; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6868 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6869 ret i8 %ret
6870}
6871
6872define i8 @test404(i8* %ptr, i8 %val) {
6873; PPC64LE-LABEL: test404:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6874; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6875; PPC64LE-NEXT: sync
6876; PPC64LE-NEXT: .LBB404_1:
6877; PPC64LE-NEXT: lbarx 5, 0, 3
6878; PPC64LE-NEXT: and 6, 4, 5
6879; PPC64LE-NEXT: stbcx. 6, 0, 3
6880; PPC64LE-NEXT: bne 0, .LBB404_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6881; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6882; PPC64LE-NEXT: mr 3, 5
6883; PPC64LE-NEXT: lwsync
6884; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6885 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6886 ret i8 %ret
6887}
6888
6889define i16 @test405(i16* %ptr, i16 %val) {
6890; PPC64LE-LABEL: test405:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6891; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6892; PPC64LE-NEXT: .LBB405_1:
6893; PPC64LE-NEXT: lharx 5, 0, 3
6894; PPC64LE-NEXT: and 6, 4, 5
6895; PPC64LE-NEXT: sthcx. 6, 0, 3
6896; PPC64LE-NEXT: bne 0, .LBB405_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6897; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6898; PPC64LE-NEXT: mr 3, 5
6899; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6900 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6901 ret i16 %ret
6902}
6903
6904define i16 @test406(i16* %ptr, i16 %val) {
6905; PPC64LE-LABEL: test406:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6906; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6907; PPC64LE-NEXT: mr 5, 3
6908; PPC64LE-NEXT: .LBB406_1:
6909; PPC64LE-NEXT: lharx 3, 0, 5
6910; PPC64LE-NEXT: and 6, 4, 3
6911; PPC64LE-NEXT: sthcx. 6, 0, 5
6912; PPC64LE-NEXT: bne 0, .LBB406_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6913; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6914; PPC64LE-NEXT: lwsync
6915; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6916 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6917 ret i16 %ret
6918}
6919
6920define i16 @test407(i16* %ptr, i16 %val) {
6921; PPC64LE-LABEL: test407:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6922; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6923; PPC64LE-NEXT: lwsync
6924; PPC64LE-NEXT: .LBB407_1:
6925; PPC64LE-NEXT: lharx 5, 0, 3
6926; PPC64LE-NEXT: and 6, 4, 5
6927; PPC64LE-NEXT: sthcx. 6, 0, 3
6928; PPC64LE-NEXT: bne 0, .LBB407_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6929; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6930; PPC64LE-NEXT: mr 3, 5
6931; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6932 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6933 ret i16 %ret
6934}
6935
6936define i16 @test408(i16* %ptr, i16 %val) {
6937; PPC64LE-LABEL: test408:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6938; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6939; PPC64LE-NEXT: lwsync
6940; PPC64LE-NEXT: .LBB408_1:
6941; PPC64LE-NEXT: lharx 5, 0, 3
6942; PPC64LE-NEXT: and 6, 4, 5
6943; PPC64LE-NEXT: sthcx. 6, 0, 3
6944; PPC64LE-NEXT: bne 0, .LBB408_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6945; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6946; PPC64LE-NEXT: mr 3, 5
6947; PPC64LE-NEXT: lwsync
6948; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6949 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6950 ret i16 %ret
6951}
6952
6953define i16 @test409(i16* %ptr, i16 %val) {
6954; PPC64LE-LABEL: test409:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6955; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6956; PPC64LE-NEXT: sync
6957; PPC64LE-NEXT: .LBB409_1:
6958; PPC64LE-NEXT: lharx 5, 0, 3
6959; PPC64LE-NEXT: and 6, 4, 5
6960; PPC64LE-NEXT: sthcx. 6, 0, 3
6961; PPC64LE-NEXT: bne 0, .LBB409_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6962; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6963; PPC64LE-NEXT: mr 3, 5
6964; PPC64LE-NEXT: lwsync
6965; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6966 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6967 ret i16 %ret
6968}
6969
6970define i32 @test410(i32* %ptr, i32 %val) {
6971; PPC64LE-LABEL: test410:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6972; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6973; PPC64LE-NEXT: .LBB410_1:
6974; PPC64LE-NEXT: lwarx 5, 0, 3
6975; PPC64LE-NEXT: and 6, 4, 5
6976; PPC64LE-NEXT: stwcx. 6, 0, 3
6977; PPC64LE-NEXT: bne 0, .LBB410_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6978; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6979; PPC64LE-NEXT: mr 3, 5
6980; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6981 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6982 ret i32 %ret
6983}
6984
6985define i32 @test411(i32* %ptr, i32 %val) {
6986; PPC64LE-LABEL: test411:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6987; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6988; PPC64LE-NEXT: mr 5, 3
6989; PPC64LE-NEXT: .LBB411_1:
6990; PPC64LE-NEXT: lwarx 3, 0, 5
6991; PPC64LE-NEXT: and 6, 4, 3
6992; PPC64LE-NEXT: stwcx. 6, 0, 5
6993; PPC64LE-NEXT: bne 0, .LBB411_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6994; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6995; PPC64LE-NEXT: lwsync
6996; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6997 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6998 ret i32 %ret
6999}
7000
7001define i32 @test412(i32* %ptr, i32 %val) {
7002; PPC64LE-LABEL: test412:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7003; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7004; PPC64LE-NEXT: lwsync
7005; PPC64LE-NEXT: .LBB412_1:
7006; PPC64LE-NEXT: lwarx 5, 0, 3
7007; PPC64LE-NEXT: and 6, 4, 5
7008; PPC64LE-NEXT: stwcx. 6, 0, 3
7009; PPC64LE-NEXT: bne 0, .LBB412_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7010; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7011; PPC64LE-NEXT: mr 3, 5
7012; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7013 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7014 ret i32 %ret
7015}
7016
7017define i32 @test413(i32* %ptr, i32 %val) {
7018; PPC64LE-LABEL: test413:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7019; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7020; PPC64LE-NEXT: lwsync
7021; PPC64LE-NEXT: .LBB413_1:
7022; PPC64LE-NEXT: lwarx 5, 0, 3
7023; PPC64LE-NEXT: and 6, 4, 5
7024; PPC64LE-NEXT: stwcx. 6, 0, 3
7025; PPC64LE-NEXT: bne 0, .LBB413_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7026; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7027; PPC64LE-NEXT: mr 3, 5
7028; PPC64LE-NEXT: lwsync
7029; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7030 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7031 ret i32 %ret
7032}
7033
7034define i32 @test414(i32* %ptr, i32 %val) {
7035; PPC64LE-LABEL: test414:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7036; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7037; PPC64LE-NEXT: sync
7038; PPC64LE-NEXT: .LBB414_1:
7039; PPC64LE-NEXT: lwarx 5, 0, 3
7040; PPC64LE-NEXT: and 6, 4, 5
7041; PPC64LE-NEXT: stwcx. 6, 0, 3
7042; PPC64LE-NEXT: bne 0, .LBB414_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7043; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7044; PPC64LE-NEXT: mr 3, 5
7045; PPC64LE-NEXT: lwsync
7046; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7047 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7048 ret i32 %ret
7049}
7050
7051define i64 @test415(i64* %ptr, i64 %val) {
7052; PPC64LE-LABEL: test415:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7053; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7054; PPC64LE-NEXT: .LBB415_1:
7055; PPC64LE-NEXT: ldarx 5, 0, 3
7056; PPC64LE-NEXT: and 6, 4, 5
7057; PPC64LE-NEXT: stdcx. 6, 0, 3
7058; PPC64LE-NEXT: bne 0, .LBB415_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7059; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7060; PPC64LE-NEXT: mr 3, 5
7061; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7062 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7063 ret i64 %ret
7064}
7065
7066define i64 @test416(i64* %ptr, i64 %val) {
7067; PPC64LE-LABEL: test416:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7068; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7069; PPC64LE-NEXT: mr 5, 3
7070; PPC64LE-NEXT: .LBB416_1:
7071; PPC64LE-NEXT: ldarx 3, 0, 5
7072; PPC64LE-NEXT: and 6, 4, 3
7073; PPC64LE-NEXT: stdcx. 6, 0, 5
7074; PPC64LE-NEXT: bne 0, .LBB416_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7075; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7076; PPC64LE-NEXT: lwsync
7077; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7078 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7079 ret i64 %ret
7080}
7081
7082define i64 @test417(i64* %ptr, i64 %val) {
7083; PPC64LE-LABEL: test417:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7084; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7085; PPC64LE-NEXT: lwsync
7086; PPC64LE-NEXT: .LBB417_1:
7087; PPC64LE-NEXT: ldarx 5, 0, 3
7088; PPC64LE-NEXT: and 6, 4, 5
7089; PPC64LE-NEXT: stdcx. 6, 0, 3
7090; PPC64LE-NEXT: bne 0, .LBB417_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7091; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7092; PPC64LE-NEXT: mr 3, 5
7093; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7094 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7095 ret i64 %ret
7096}
7097
7098define i64 @test418(i64* %ptr, i64 %val) {
7099; PPC64LE-LABEL: test418:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7100; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7101; PPC64LE-NEXT: lwsync
7102; PPC64LE-NEXT: .LBB418_1:
7103; PPC64LE-NEXT: ldarx 5, 0, 3
7104; PPC64LE-NEXT: and 6, 4, 5
7105; PPC64LE-NEXT: stdcx. 6, 0, 3
7106; PPC64LE-NEXT: bne 0, .LBB418_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7107; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7108; PPC64LE-NEXT: mr 3, 5
7109; PPC64LE-NEXT: lwsync
7110; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7111 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7112 ret i64 %ret
7113}
7114
7115define i64 @test419(i64* %ptr, i64 %val) {
7116; PPC64LE-LABEL: test419:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7117; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7118; PPC64LE-NEXT: sync
7119; PPC64LE-NEXT: .LBB419_1:
7120; PPC64LE-NEXT: ldarx 5, 0, 3
7121; PPC64LE-NEXT: and 6, 4, 5
7122; PPC64LE-NEXT: stdcx. 6, 0, 3
7123; PPC64LE-NEXT: bne 0, .LBB419_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7124; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7125; PPC64LE-NEXT: mr 3, 5
7126; PPC64LE-NEXT: lwsync
7127; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7128 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7129 ret i64 %ret
7130}
7131
7132define i8 @test420(i8* %ptr, i8 %val) {
7133; PPC64LE-LABEL: test420:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7134; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7135; PPC64LE-NEXT: .LBB420_1:
7136; PPC64LE-NEXT: lbarx 5, 0, 3
7137; PPC64LE-NEXT: nand 6, 4, 5
7138; PPC64LE-NEXT: stbcx. 6, 0, 3
7139; PPC64LE-NEXT: bne 0, .LBB420_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7140; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7141; PPC64LE-NEXT: mr 3, 5
7142; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7143 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7144 ret i8 %ret
7145}
7146
7147define i8 @test421(i8* %ptr, i8 %val) {
7148; PPC64LE-LABEL: test421:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7149; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7150; PPC64LE-NEXT: mr 5, 3
7151; PPC64LE-NEXT: .LBB421_1:
7152; PPC64LE-NEXT: lbarx 3, 0, 5
7153; PPC64LE-NEXT: nand 6, 4, 3
7154; PPC64LE-NEXT: stbcx. 6, 0, 5
7155; PPC64LE-NEXT: bne 0, .LBB421_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7156; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7157; PPC64LE-NEXT: lwsync
7158; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7159 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7160 ret i8 %ret
7161}
7162
7163define i8 @test422(i8* %ptr, i8 %val) {
7164; PPC64LE-LABEL: test422:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7165; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7166; PPC64LE-NEXT: lwsync
7167; PPC64LE-NEXT: .LBB422_1:
7168; PPC64LE-NEXT: lbarx 5, 0, 3
7169; PPC64LE-NEXT: nand 6, 4, 5
7170; PPC64LE-NEXT: stbcx. 6, 0, 3
7171; PPC64LE-NEXT: bne 0, .LBB422_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7172; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7173; PPC64LE-NEXT: mr 3, 5
7174; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7175 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7176 ret i8 %ret
7177}
7178
7179define i8 @test423(i8* %ptr, i8 %val) {
7180; PPC64LE-LABEL: test423:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7181; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7182; PPC64LE-NEXT: lwsync
7183; PPC64LE-NEXT: .LBB423_1:
7184; PPC64LE-NEXT: lbarx 5, 0, 3
7185; PPC64LE-NEXT: nand 6, 4, 5
7186; PPC64LE-NEXT: stbcx. 6, 0, 3
7187; PPC64LE-NEXT: bne 0, .LBB423_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7188; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7189; PPC64LE-NEXT: mr 3, 5
7190; PPC64LE-NEXT: lwsync
7191; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7192 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7193 ret i8 %ret
7194}
7195
7196define i8 @test424(i8* %ptr, i8 %val) {
7197; PPC64LE-LABEL: test424:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7198; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7199; PPC64LE-NEXT: sync
7200; PPC64LE-NEXT: .LBB424_1:
7201; PPC64LE-NEXT: lbarx 5, 0, 3
7202; PPC64LE-NEXT: nand 6, 4, 5
7203; PPC64LE-NEXT: stbcx. 6, 0, 3
7204; PPC64LE-NEXT: bne 0, .LBB424_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7205; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7206; PPC64LE-NEXT: mr 3, 5
7207; PPC64LE-NEXT: lwsync
7208; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7209 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7210 ret i8 %ret
7211}
7212
7213define i16 @test425(i16* %ptr, i16 %val) {
7214; PPC64LE-LABEL: test425:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7215; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7216; PPC64LE-NEXT: .LBB425_1:
7217; PPC64LE-NEXT: lharx 5, 0, 3
7218; PPC64LE-NEXT: nand 6, 4, 5
7219; PPC64LE-NEXT: sthcx. 6, 0, 3
7220; PPC64LE-NEXT: bne 0, .LBB425_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7221; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7222; PPC64LE-NEXT: mr 3, 5
7223; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7224 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7225 ret i16 %ret
7226}
7227
7228define i16 @test426(i16* %ptr, i16 %val) {
7229; PPC64LE-LABEL: test426:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7230; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7231; PPC64LE-NEXT: mr 5, 3
7232; PPC64LE-NEXT: .LBB426_1:
7233; PPC64LE-NEXT: lharx 3, 0, 5
7234; PPC64LE-NEXT: nand 6, 4, 3
7235; PPC64LE-NEXT: sthcx. 6, 0, 5
7236; PPC64LE-NEXT: bne 0, .LBB426_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7237; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7238; PPC64LE-NEXT: lwsync
7239; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7240 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7241 ret i16 %ret
7242}
7243
7244define i16 @test427(i16* %ptr, i16 %val) {
7245; PPC64LE-LABEL: test427:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7246; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7247; PPC64LE-NEXT: lwsync
7248; PPC64LE-NEXT: .LBB427_1:
7249; PPC64LE-NEXT: lharx 5, 0, 3
7250; PPC64LE-NEXT: nand 6, 4, 5
7251; PPC64LE-NEXT: sthcx. 6, 0, 3
7252; PPC64LE-NEXT: bne 0, .LBB427_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7253; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7254; PPC64LE-NEXT: mr 3, 5
7255; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7256 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7257 ret i16 %ret
7258}
7259
7260define i16 @test428(i16* %ptr, i16 %val) {
7261; PPC64LE-LABEL: test428:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7262; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7263; PPC64LE-NEXT: lwsync
7264; PPC64LE-NEXT: .LBB428_1:
7265; PPC64LE-NEXT: lharx 5, 0, 3
7266; PPC64LE-NEXT: nand 6, 4, 5
7267; PPC64LE-NEXT: sthcx. 6, 0, 3
7268; PPC64LE-NEXT: bne 0, .LBB428_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7269; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7270; PPC64LE-NEXT: mr 3, 5
7271; PPC64LE-NEXT: lwsync
7272; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7273 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7274 ret i16 %ret
7275}
7276
7277define i16 @test429(i16* %ptr, i16 %val) {
7278; PPC64LE-LABEL: test429:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7279; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7280; PPC64LE-NEXT: sync
7281; PPC64LE-NEXT: .LBB429_1:
7282; PPC64LE-NEXT: lharx 5, 0, 3
7283; PPC64LE-NEXT: nand 6, 4, 5
7284; PPC64LE-NEXT: sthcx. 6, 0, 3
7285; PPC64LE-NEXT: bne 0, .LBB429_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7286; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7287; PPC64LE-NEXT: mr 3, 5
7288; PPC64LE-NEXT: lwsync
7289; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7290 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7291 ret i16 %ret
7292}
7293
7294define i32 @test430(i32* %ptr, i32 %val) {
7295; PPC64LE-LABEL: test430:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7296; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7297; PPC64LE-NEXT: .LBB430_1:
7298; PPC64LE-NEXT: lwarx 5, 0, 3
7299; PPC64LE-NEXT: nand 6, 4, 5
7300; PPC64LE-NEXT: stwcx. 6, 0, 3
7301; PPC64LE-NEXT: bne 0, .LBB430_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7302; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7303; PPC64LE-NEXT: mr 3, 5
7304; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7305 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7306 ret i32 %ret
7307}
7308
7309define i32 @test431(i32* %ptr, i32 %val) {
7310; PPC64LE-LABEL: test431:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7311; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7312; PPC64LE-NEXT: mr 5, 3
7313; PPC64LE-NEXT: .LBB431_1:
7314; PPC64LE-NEXT: lwarx 3, 0, 5
7315; PPC64LE-NEXT: nand 6, 4, 3
7316; PPC64LE-NEXT: stwcx. 6, 0, 5
7317; PPC64LE-NEXT: bne 0, .LBB431_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7318; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7319; PPC64LE-NEXT: lwsync
7320; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7321 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7322 ret i32 %ret
7323}
7324
7325define i32 @test432(i32* %ptr, i32 %val) {
7326; PPC64LE-LABEL: test432:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7327; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7328; PPC64LE-NEXT: lwsync
7329; PPC64LE-NEXT: .LBB432_1:
7330; PPC64LE-NEXT: lwarx 5, 0, 3
7331; PPC64LE-NEXT: nand 6, 4, 5
7332; PPC64LE-NEXT: stwcx. 6, 0, 3
7333; PPC64LE-NEXT: bne 0, .LBB432_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7334; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7335; PPC64LE-NEXT: mr 3, 5
7336; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7337 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7338 ret i32 %ret
7339}
7340
7341define i32 @test433(i32* %ptr, i32 %val) {
7342; PPC64LE-LABEL: test433:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7343; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7344; PPC64LE-NEXT: lwsync
7345; PPC64LE-NEXT: .LBB433_1:
7346; PPC64LE-NEXT: lwarx 5, 0, 3
7347; PPC64LE-NEXT: nand 6, 4, 5
7348; PPC64LE-NEXT: stwcx. 6, 0, 3
7349; PPC64LE-NEXT: bne 0, .LBB433_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7350; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7351; PPC64LE-NEXT: mr 3, 5
7352; PPC64LE-NEXT: lwsync
7353; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7354 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7355 ret i32 %ret
7356}
7357
7358define i32 @test434(i32* %ptr, i32 %val) {
7359; PPC64LE-LABEL: test434:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7360; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7361; PPC64LE-NEXT: sync
7362; PPC64LE-NEXT: .LBB434_1:
7363; PPC64LE-NEXT: lwarx 5, 0, 3
7364; PPC64LE-NEXT: nand 6, 4, 5
7365; PPC64LE-NEXT: stwcx. 6, 0, 3
7366; PPC64LE-NEXT: bne 0, .LBB434_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7367; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7368; PPC64LE-NEXT: mr 3, 5
7369; PPC64LE-NEXT: lwsync
7370; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7371 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7372 ret i32 %ret
7373}
7374
7375define i64 @test435(i64* %ptr, i64 %val) {
7376; PPC64LE-LABEL: test435:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7377; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7378; PPC64LE-NEXT: .LBB435_1:
7379; PPC64LE-NEXT: ldarx 5, 0, 3
7380; PPC64LE-NEXT: nand 6, 4, 5
7381; PPC64LE-NEXT: stdcx. 6, 0, 3
7382; PPC64LE-NEXT: bne 0, .LBB435_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7383; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7384; PPC64LE-NEXT: mr 3, 5
7385; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7386 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7387 ret i64 %ret
7388}
7389
7390define i64 @test436(i64* %ptr, i64 %val) {
7391; PPC64LE-LABEL: test436:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7392; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7393; PPC64LE-NEXT: mr 5, 3
7394; PPC64LE-NEXT: .LBB436_1:
7395; PPC64LE-NEXT: ldarx 3, 0, 5
7396; PPC64LE-NEXT: nand 6, 4, 3
7397; PPC64LE-NEXT: stdcx. 6, 0, 5
7398; PPC64LE-NEXT: bne 0, .LBB436_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7399; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7400; PPC64LE-NEXT: lwsync
7401; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7402 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7403 ret i64 %ret
7404}
7405
7406define i64 @test437(i64* %ptr, i64 %val) {
7407; PPC64LE-LABEL: test437:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7408; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7409; PPC64LE-NEXT: lwsync
7410; PPC64LE-NEXT: .LBB437_1:
7411; PPC64LE-NEXT: ldarx 5, 0, 3
7412; PPC64LE-NEXT: nand 6, 4, 5
7413; PPC64LE-NEXT: stdcx. 6, 0, 3
7414; PPC64LE-NEXT: bne 0, .LBB437_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7415; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7416; PPC64LE-NEXT: mr 3, 5
7417; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7418 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7419 ret i64 %ret
7420}
7421
7422define i64 @test438(i64* %ptr, i64 %val) {
7423; PPC64LE-LABEL: test438:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7424; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7425; PPC64LE-NEXT: lwsync
7426; PPC64LE-NEXT: .LBB438_1:
7427; PPC64LE-NEXT: ldarx 5, 0, 3
7428; PPC64LE-NEXT: nand 6, 4, 5
7429; PPC64LE-NEXT: stdcx. 6, 0, 3
7430; PPC64LE-NEXT: bne 0, .LBB438_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7431; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7432; PPC64LE-NEXT: mr 3, 5
7433; PPC64LE-NEXT: lwsync
7434; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7435 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7436 ret i64 %ret
7437}
7438
7439define i64 @test439(i64* %ptr, i64 %val) {
7440; PPC64LE-LABEL: test439:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7441; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7442; PPC64LE-NEXT: sync
7443; PPC64LE-NEXT: .LBB439_1:
7444; PPC64LE-NEXT: ldarx 5, 0, 3
7445; PPC64LE-NEXT: nand 6, 4, 5
7446; PPC64LE-NEXT: stdcx. 6, 0, 3
7447; PPC64LE-NEXT: bne 0, .LBB439_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7448; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7449; PPC64LE-NEXT: mr 3, 5
7450; PPC64LE-NEXT: lwsync
7451; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7452 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7453 ret i64 %ret
7454}
7455
7456define i8 @test440(i8* %ptr, i8 %val) {
7457; PPC64LE-LABEL: test440:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7458; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7459; PPC64LE-NEXT: .LBB440_1:
7460; PPC64LE-NEXT: lbarx 5, 0, 3
7461; PPC64LE-NEXT: or 6, 4, 5
7462; PPC64LE-NEXT: stbcx. 6, 0, 3
7463; PPC64LE-NEXT: bne 0, .LBB440_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7464; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7465; PPC64LE-NEXT: mr 3, 5
7466; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7467 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7468 ret i8 %ret
7469}
7470
7471define i8 @test441(i8* %ptr, i8 %val) {
7472; PPC64LE-LABEL: test441:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7473; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7474; PPC64LE-NEXT: mr 5, 3
7475; PPC64LE-NEXT: .LBB441_1:
7476; PPC64LE-NEXT: lbarx 3, 0, 5
7477; PPC64LE-NEXT: or 6, 4, 3
7478; PPC64LE-NEXT: stbcx. 6, 0, 5
7479; PPC64LE-NEXT: bne 0, .LBB441_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7480; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7481; PPC64LE-NEXT: lwsync
7482; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7483 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7484 ret i8 %ret
7485}
7486
7487define i8 @test442(i8* %ptr, i8 %val) {
7488; PPC64LE-LABEL: test442:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7489; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7490; PPC64LE-NEXT: lwsync
7491; PPC64LE-NEXT: .LBB442_1:
7492; PPC64LE-NEXT: lbarx 5, 0, 3
7493; PPC64LE-NEXT: or 6, 4, 5
7494; PPC64LE-NEXT: stbcx. 6, 0, 3
7495; PPC64LE-NEXT: bne 0, .LBB442_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7496; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7497; PPC64LE-NEXT: mr 3, 5
7498; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7499 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7500 ret i8 %ret
7501}
7502
7503define i8 @test443(i8* %ptr, i8 %val) {
7504; PPC64LE-LABEL: test443:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7505; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7506; PPC64LE-NEXT: lwsync
7507; PPC64LE-NEXT: .LBB443_1:
7508; PPC64LE-NEXT: lbarx 5, 0, 3
7509; PPC64LE-NEXT: or 6, 4, 5
7510; PPC64LE-NEXT: stbcx. 6, 0, 3
7511; PPC64LE-NEXT: bne 0, .LBB443_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7512; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7513; PPC64LE-NEXT: mr 3, 5
7514; PPC64LE-NEXT: lwsync
7515; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7516 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7517 ret i8 %ret
7518}
7519
7520define i8 @test444(i8* %ptr, i8 %val) {
7521; PPC64LE-LABEL: test444:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7522; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7523; PPC64LE-NEXT: sync
7524; PPC64LE-NEXT: .LBB444_1:
7525; PPC64LE-NEXT: lbarx 5, 0, 3
7526; PPC64LE-NEXT: or 6, 4, 5
7527; PPC64LE-NEXT: stbcx. 6, 0, 3
7528; PPC64LE-NEXT: bne 0, .LBB444_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7529; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7530; PPC64LE-NEXT: mr 3, 5
7531; PPC64LE-NEXT: lwsync
7532; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7533 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7534 ret i8 %ret
7535}
7536
7537define i16 @test445(i16* %ptr, i16 %val) {
7538; PPC64LE-LABEL: test445:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7539; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7540; PPC64LE-NEXT: .LBB445_1:
7541; PPC64LE-NEXT: lharx 5, 0, 3
7542; PPC64LE-NEXT: or 6, 4, 5
7543; PPC64LE-NEXT: sthcx. 6, 0, 3
7544; PPC64LE-NEXT: bne 0, .LBB445_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7545; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7546; PPC64LE-NEXT: mr 3, 5
7547; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7548 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7549 ret i16 %ret
7550}
7551
7552define i16 @test446(i16* %ptr, i16 %val) {
7553; PPC64LE-LABEL: test446:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7554; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7555; PPC64LE-NEXT: mr 5, 3
7556; PPC64LE-NEXT: .LBB446_1:
7557; PPC64LE-NEXT: lharx 3, 0, 5
7558; PPC64LE-NEXT: or 6, 4, 3
7559; PPC64LE-NEXT: sthcx. 6, 0, 5
7560; PPC64LE-NEXT: bne 0, .LBB446_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7561; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7562; PPC64LE-NEXT: lwsync
7563; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7564 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7565 ret i16 %ret
7566}
7567
7568define i16 @test447(i16* %ptr, i16 %val) {
7569; PPC64LE-LABEL: test447:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7570; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7571; PPC64LE-NEXT: lwsync
7572; PPC64LE-NEXT: .LBB447_1:
7573; PPC64LE-NEXT: lharx 5, 0, 3
7574; PPC64LE-NEXT: or 6, 4, 5
7575; PPC64LE-NEXT: sthcx. 6, 0, 3
7576; PPC64LE-NEXT: bne 0, .LBB447_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7577; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7578; PPC64LE-NEXT: mr 3, 5
7579; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7580 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7581 ret i16 %ret
7582}
7583
7584define i16 @test448(i16* %ptr, i16 %val) {
7585; PPC64LE-LABEL: test448:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7586; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7587; PPC64LE-NEXT: lwsync
7588; PPC64LE-NEXT: .LBB448_1:
7589; PPC64LE-NEXT: lharx 5, 0, 3
7590; PPC64LE-NEXT: or 6, 4, 5
7591; PPC64LE-NEXT: sthcx. 6, 0, 3
7592; PPC64LE-NEXT: bne 0, .LBB448_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7593; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7594; PPC64LE-NEXT: mr 3, 5
7595; PPC64LE-NEXT: lwsync
7596; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7597 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7598 ret i16 %ret
7599}
7600
7601define i16 @test449(i16* %ptr, i16 %val) {
7602; PPC64LE-LABEL: test449:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7603; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7604; PPC64LE-NEXT: sync
7605; PPC64LE-NEXT: .LBB449_1:
7606; PPC64LE-NEXT: lharx 5, 0, 3
7607; PPC64LE-NEXT: or 6, 4, 5
7608; PPC64LE-NEXT: sthcx. 6, 0, 3
7609; PPC64LE-NEXT: bne 0, .LBB449_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7610; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7611; PPC64LE-NEXT: mr 3, 5
7612; PPC64LE-NEXT: lwsync
7613; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7614 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7615 ret i16 %ret
7616}
7617
7618define i32 @test450(i32* %ptr, i32 %val) {
7619; PPC64LE-LABEL: test450:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7620; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7621; PPC64LE-NEXT: .LBB450_1:
7622; PPC64LE-NEXT: lwarx 5, 0, 3
7623; PPC64LE-NEXT: or 6, 4, 5
7624; PPC64LE-NEXT: stwcx. 6, 0, 3
7625; PPC64LE-NEXT: bne 0, .LBB450_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7626; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7627; PPC64LE-NEXT: mr 3, 5
7628; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7629 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7630 ret i32 %ret
7631}
7632
7633define i32 @test451(i32* %ptr, i32 %val) {
7634; PPC64LE-LABEL: test451:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7635; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7636; PPC64LE-NEXT: mr 5, 3
7637; PPC64LE-NEXT: .LBB451_1:
7638; PPC64LE-NEXT: lwarx 3, 0, 5
7639; PPC64LE-NEXT: or 6, 4, 3
7640; PPC64LE-NEXT: stwcx. 6, 0, 5
7641; PPC64LE-NEXT: bne 0, .LBB451_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7642; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7643; PPC64LE-NEXT: lwsync
7644; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7645 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7646 ret i32 %ret
7647}
7648
7649define i32 @test452(i32* %ptr, i32 %val) {
7650; PPC64LE-LABEL: test452:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7651; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7652; PPC64LE-NEXT: lwsync
7653; PPC64LE-NEXT: .LBB452_1:
7654; PPC64LE-NEXT: lwarx 5, 0, 3
7655; PPC64LE-NEXT: or 6, 4, 5
7656; PPC64LE-NEXT: stwcx. 6, 0, 3
7657; PPC64LE-NEXT: bne 0, .LBB452_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7658; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7659; PPC64LE-NEXT: mr 3, 5
7660; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7661 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7662 ret i32 %ret
7663}
7664
7665define i32 @test453(i32* %ptr, i32 %val) {
7666; PPC64LE-LABEL: test453:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7667; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7668; PPC64LE-NEXT: lwsync
7669; PPC64LE-NEXT: .LBB453_1:
7670; PPC64LE-NEXT: lwarx 5, 0, 3
7671; PPC64LE-NEXT: or 6, 4, 5
7672; PPC64LE-NEXT: stwcx. 6, 0, 3
7673; PPC64LE-NEXT: bne 0, .LBB453_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7674; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7675; PPC64LE-NEXT: mr 3, 5
7676; PPC64LE-NEXT: lwsync
7677; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7678 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7679 ret i32 %ret
7680}
7681
7682define i32 @test454(i32* %ptr, i32 %val) {
7683; PPC64LE-LABEL: test454:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7684; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7685; PPC64LE-NEXT: sync
7686; PPC64LE-NEXT: .LBB454_1:
7687; PPC64LE-NEXT: lwarx 5, 0, 3
7688; PPC64LE-NEXT: or 6, 4, 5
7689; PPC64LE-NEXT: stwcx. 6, 0, 3
7690; PPC64LE-NEXT: bne 0, .LBB454_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7691; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7692; PPC64LE-NEXT: mr 3, 5
7693; PPC64LE-NEXT: lwsync
7694; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7695 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7696 ret i32 %ret
7697}
7698
7699define i64 @test455(i64* %ptr, i64 %val) {
7700; PPC64LE-LABEL: test455:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7701; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7702; PPC64LE-NEXT: .LBB455_1:
7703; PPC64LE-NEXT: ldarx 5, 0, 3
7704; PPC64LE-NEXT: or 6, 4, 5
7705; PPC64LE-NEXT: stdcx. 6, 0, 3
7706; PPC64LE-NEXT: bne 0, .LBB455_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7707; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7708; PPC64LE-NEXT: mr 3, 5
7709; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7710 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7711 ret i64 %ret
7712}
7713
7714define i64 @test456(i64* %ptr, i64 %val) {
7715; PPC64LE-LABEL: test456:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7716; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7717; PPC64LE-NEXT: mr 5, 3
7718; PPC64LE-NEXT: .LBB456_1:
7719; PPC64LE-NEXT: ldarx 3, 0, 5
7720; PPC64LE-NEXT: or 6, 4, 3
7721; PPC64LE-NEXT: stdcx. 6, 0, 5
7722; PPC64LE-NEXT: bne 0, .LBB456_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7723; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7724; PPC64LE-NEXT: lwsync
7725; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7726 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7727 ret i64 %ret
7728}
7729
7730define i64 @test457(i64* %ptr, i64 %val) {
7731; PPC64LE-LABEL: test457:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7732; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7733; PPC64LE-NEXT: lwsync
7734; PPC64LE-NEXT: .LBB457_1:
7735; PPC64LE-NEXT: ldarx 5, 0, 3
7736; PPC64LE-NEXT: or 6, 4, 5
7737; PPC64LE-NEXT: stdcx. 6, 0, 3
7738; PPC64LE-NEXT: bne 0, .LBB457_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7739; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7740; PPC64LE-NEXT: mr 3, 5
7741; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7742 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7743 ret i64 %ret
7744}
7745
7746define i64 @test458(i64* %ptr, i64 %val) {
7747; PPC64LE-LABEL: test458:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7748; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7749; PPC64LE-NEXT: lwsync
7750; PPC64LE-NEXT: .LBB458_1:
7751; PPC64LE-NEXT: ldarx 5, 0, 3
7752; PPC64LE-NEXT: or 6, 4, 5
7753; PPC64LE-NEXT: stdcx. 6, 0, 3
7754; PPC64LE-NEXT: bne 0, .LBB458_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7755; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7756; PPC64LE-NEXT: mr 3, 5
7757; PPC64LE-NEXT: lwsync
7758; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7759 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7760 ret i64 %ret
7761}
7762
7763define i64 @test459(i64* %ptr, i64 %val) {
7764; PPC64LE-LABEL: test459:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7765; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7766; PPC64LE-NEXT: sync
7767; PPC64LE-NEXT: .LBB459_1:
7768; PPC64LE-NEXT: ldarx 5, 0, 3
7769; PPC64LE-NEXT: or 6, 4, 5
7770; PPC64LE-NEXT: stdcx. 6, 0, 3
7771; PPC64LE-NEXT: bne 0, .LBB459_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7772; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7773; PPC64LE-NEXT: mr 3, 5
7774; PPC64LE-NEXT: lwsync
7775; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7776 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7777 ret i64 %ret
7778}
7779
7780define i8 @test460(i8* %ptr, i8 %val) {
7781; PPC64LE-LABEL: test460:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7782; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7783; PPC64LE-NEXT: .LBB460_1:
7784; PPC64LE-NEXT: lbarx 5, 0, 3
7785; PPC64LE-NEXT: xor 6, 4, 5
7786; PPC64LE-NEXT: stbcx. 6, 0, 3
7787; PPC64LE-NEXT: bne 0, .LBB460_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7788; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7789; PPC64LE-NEXT: mr 3, 5
7790; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7791 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7792 ret i8 %ret
7793}
7794
7795define i8 @test461(i8* %ptr, i8 %val) {
7796; PPC64LE-LABEL: test461:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7797; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7798; PPC64LE-NEXT: mr 5, 3
7799; PPC64LE-NEXT: .LBB461_1:
7800; PPC64LE-NEXT: lbarx 3, 0, 5
7801; PPC64LE-NEXT: xor 6, 4, 3
7802; PPC64LE-NEXT: stbcx. 6, 0, 5
7803; PPC64LE-NEXT: bne 0, .LBB461_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7804; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7805; PPC64LE-NEXT: lwsync
7806; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7807 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7808 ret i8 %ret
7809}
7810
7811define i8 @test462(i8* %ptr, i8 %val) {
7812; PPC64LE-LABEL: test462:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7813; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7814; PPC64LE-NEXT: lwsync
7815; PPC64LE-NEXT: .LBB462_1:
7816; PPC64LE-NEXT: lbarx 5, 0, 3
7817; PPC64LE-NEXT: xor 6, 4, 5
7818; PPC64LE-NEXT: stbcx. 6, 0, 3
7819; PPC64LE-NEXT: bne 0, .LBB462_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7820; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7821; PPC64LE-NEXT: mr 3, 5
7822; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7823 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7824 ret i8 %ret
7825}
7826
7827define i8 @test463(i8* %ptr, i8 %val) {
7828; PPC64LE-LABEL: test463:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7829; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7830; PPC64LE-NEXT: lwsync
7831; PPC64LE-NEXT: .LBB463_1:
7832; PPC64LE-NEXT: lbarx 5, 0, 3
7833; PPC64LE-NEXT: xor 6, 4, 5
7834; PPC64LE-NEXT: stbcx. 6, 0, 3
7835; PPC64LE-NEXT: bne 0, .LBB463_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7836; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7837; PPC64LE-NEXT: mr 3, 5
7838; PPC64LE-NEXT: lwsync
7839; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7840 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7841 ret i8 %ret
7842}
7843
7844define i8 @test464(i8* %ptr, i8 %val) {
7845; PPC64LE-LABEL: test464:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7846; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7847; PPC64LE-NEXT: sync
7848; PPC64LE-NEXT: .LBB464_1:
7849; PPC64LE-NEXT: lbarx 5, 0, 3
7850; PPC64LE-NEXT: xor 6, 4, 5
7851; PPC64LE-NEXT: stbcx. 6, 0, 3
7852; PPC64LE-NEXT: bne 0, .LBB464_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7853; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7854; PPC64LE-NEXT: mr 3, 5
7855; PPC64LE-NEXT: lwsync
7856; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7857 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7858 ret i8 %ret
7859}
7860
7861define i16 @test465(i16* %ptr, i16 %val) {
7862; PPC64LE-LABEL: test465:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7863; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7864; PPC64LE-NEXT: .LBB465_1:
7865; PPC64LE-NEXT: lharx 5, 0, 3
7866; PPC64LE-NEXT: xor 6, 4, 5
7867; PPC64LE-NEXT: sthcx. 6, 0, 3
7868; PPC64LE-NEXT: bne 0, .LBB465_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7869; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7870; PPC64LE-NEXT: mr 3, 5
7871; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7872 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7873 ret i16 %ret
7874}
7875
7876define i16 @test466(i16* %ptr, i16 %val) {
7877; PPC64LE-LABEL: test466:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7878; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7879; PPC64LE-NEXT: mr 5, 3
7880; PPC64LE-NEXT: .LBB466_1:
7881; PPC64LE-NEXT: lharx 3, 0, 5
7882; PPC64LE-NEXT: xor 6, 4, 3
7883; PPC64LE-NEXT: sthcx. 6, 0, 5
7884; PPC64LE-NEXT: bne 0, .LBB466_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7885; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7886; PPC64LE-NEXT: lwsync
7887; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7888 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7889 ret i16 %ret
7890}
7891
7892define i16 @test467(i16* %ptr, i16 %val) {
7893; PPC64LE-LABEL: test467:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7894; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7895; PPC64LE-NEXT: lwsync
7896; PPC64LE-NEXT: .LBB467_1:
7897; PPC64LE-NEXT: lharx 5, 0, 3
7898; PPC64LE-NEXT: xor 6, 4, 5
7899; PPC64LE-NEXT: sthcx. 6, 0, 3
7900; PPC64LE-NEXT: bne 0, .LBB467_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7901; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7902; PPC64LE-NEXT: mr 3, 5
7903; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7904 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7905 ret i16 %ret
7906}
7907
7908define i16 @test468(i16* %ptr, i16 %val) {
7909; PPC64LE-LABEL: test468:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7910; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7911; PPC64LE-NEXT: lwsync
7912; PPC64LE-NEXT: .LBB468_1:
7913; PPC64LE-NEXT: lharx 5, 0, 3
7914; PPC64LE-NEXT: xor 6, 4, 5
7915; PPC64LE-NEXT: sthcx. 6, 0, 3
7916; PPC64LE-NEXT: bne 0, .LBB468_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7917; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7918; PPC64LE-NEXT: mr 3, 5
7919; PPC64LE-NEXT: lwsync
7920; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7921 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7922 ret i16 %ret
7923}
7924
7925define i16 @test469(i16* %ptr, i16 %val) {
7926; PPC64LE-LABEL: test469:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7927; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7928; PPC64LE-NEXT: sync
7929; PPC64LE-NEXT: .LBB469_1:
7930; PPC64LE-NEXT: lharx 5, 0, 3
7931; PPC64LE-NEXT: xor 6, 4, 5
7932; PPC64LE-NEXT: sthcx. 6, 0, 3
7933; PPC64LE-NEXT: bne 0, .LBB469_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7934; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7935; PPC64LE-NEXT: mr 3, 5
7936; PPC64LE-NEXT: lwsync
7937; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7938 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7939 ret i16 %ret
7940}
7941
7942define i32 @test470(i32* %ptr, i32 %val) {
7943; PPC64LE-LABEL: test470:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7944; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7945; PPC64LE-NEXT: .LBB470_1:
7946; PPC64LE-NEXT: lwarx 5, 0, 3
7947; PPC64LE-NEXT: xor 6, 4, 5
7948; PPC64LE-NEXT: stwcx. 6, 0, 3
7949; PPC64LE-NEXT: bne 0, .LBB470_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7950; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7951; PPC64LE-NEXT: mr 3, 5
7952; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7953 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7954 ret i32 %ret
7955}
7956
7957define i32 @test471(i32* %ptr, i32 %val) {
7958; PPC64LE-LABEL: test471:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7959; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7960; PPC64LE-NEXT: mr 5, 3
7961; PPC64LE-NEXT: .LBB471_1:
7962; PPC64LE-NEXT: lwarx 3, 0, 5
7963; PPC64LE-NEXT: xor 6, 4, 3
7964; PPC64LE-NEXT: stwcx. 6, 0, 5
7965; PPC64LE-NEXT: bne 0, .LBB471_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7966; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7967; PPC64LE-NEXT: lwsync
7968; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7969 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7970 ret i32 %ret
7971}
7972
7973define i32 @test472(i32* %ptr, i32 %val) {
7974; PPC64LE-LABEL: test472:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7975; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7976; PPC64LE-NEXT: lwsync
7977; PPC64LE-NEXT: .LBB472_1:
7978; PPC64LE-NEXT: lwarx 5, 0, 3
7979; PPC64LE-NEXT: xor 6, 4, 5
7980; PPC64LE-NEXT: stwcx. 6, 0, 3
7981; PPC64LE-NEXT: bne 0, .LBB472_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7982; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7983; PPC64LE-NEXT: mr 3, 5
7984; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7985 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7986 ret i32 %ret
7987}
7988
7989define i32 @test473(i32* %ptr, i32 %val) {
7990; PPC64LE-LABEL: test473:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7991; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7992; PPC64LE-NEXT: lwsync
7993; PPC64LE-NEXT: .LBB473_1:
7994; PPC64LE-NEXT: lwarx 5, 0, 3
7995; PPC64LE-NEXT: xor 6, 4, 5
7996; PPC64LE-NEXT: stwcx. 6, 0, 3
7997; PPC64LE-NEXT: bne 0, .LBB473_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7998; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7999; PPC64LE-NEXT: mr 3, 5
8000; PPC64LE-NEXT: lwsync
8001; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8002 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8003 ret i32 %ret
8004}
8005
8006define i32 @test474(i32* %ptr, i32 %val) {
8007; PPC64LE-LABEL: test474:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8008; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8009; PPC64LE-NEXT: sync
8010; PPC64LE-NEXT: .LBB474_1:
8011; PPC64LE-NEXT: lwarx 5, 0, 3
8012; PPC64LE-NEXT: xor 6, 4, 5
8013; PPC64LE-NEXT: stwcx. 6, 0, 3
8014; PPC64LE-NEXT: bne 0, .LBB474_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8015; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8016; PPC64LE-NEXT: mr 3, 5
8017; PPC64LE-NEXT: lwsync
8018; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8019 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8020 ret i32 %ret
8021}
8022
8023define i64 @test475(i64* %ptr, i64 %val) {
8024; PPC64LE-LABEL: test475:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8025; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8026; PPC64LE-NEXT: .LBB475_1:
8027; PPC64LE-NEXT: ldarx 5, 0, 3
8028; PPC64LE-NEXT: xor 6, 4, 5
8029; PPC64LE-NEXT: stdcx. 6, 0, 3
8030; PPC64LE-NEXT: bne 0, .LBB475_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8031; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8032; PPC64LE-NEXT: mr 3, 5
8033; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8034 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8035 ret i64 %ret
8036}
8037
8038define i64 @test476(i64* %ptr, i64 %val) {
8039; PPC64LE-LABEL: test476:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8040; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8041; PPC64LE-NEXT: mr 5, 3
8042; PPC64LE-NEXT: .LBB476_1:
8043; PPC64LE-NEXT: ldarx 3, 0, 5
8044; PPC64LE-NEXT: xor 6, 4, 3
8045; PPC64LE-NEXT: stdcx. 6, 0, 5
8046; PPC64LE-NEXT: bne 0, .LBB476_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8047; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8048; PPC64LE-NEXT: lwsync
8049; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8050 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8051 ret i64 %ret
8052}
8053
8054define i64 @test477(i64* %ptr, i64 %val) {
8055; PPC64LE-LABEL: test477:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8056; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8057; PPC64LE-NEXT: lwsync
8058; PPC64LE-NEXT: .LBB477_1:
8059; PPC64LE-NEXT: ldarx 5, 0, 3
8060; PPC64LE-NEXT: xor 6, 4, 5
8061; PPC64LE-NEXT: stdcx. 6, 0, 3
8062; PPC64LE-NEXT: bne 0, .LBB477_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8063; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8064; PPC64LE-NEXT: mr 3, 5
8065; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8066 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8067 ret i64 %ret
8068}
8069
8070define i64 @test478(i64* %ptr, i64 %val) {
8071; PPC64LE-LABEL: test478:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8072; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8073; PPC64LE-NEXT: lwsync
8074; PPC64LE-NEXT: .LBB478_1:
8075; PPC64LE-NEXT: ldarx 5, 0, 3
8076; PPC64LE-NEXT: xor 6, 4, 5
8077; PPC64LE-NEXT: stdcx. 6, 0, 3
8078; PPC64LE-NEXT: bne 0, .LBB478_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8079; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8080; PPC64LE-NEXT: mr 3, 5
8081; PPC64LE-NEXT: lwsync
8082; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8083 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8084 ret i64 %ret
8085}
8086
8087define i64 @test479(i64* %ptr, i64 %val) {
8088; PPC64LE-LABEL: test479:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8089; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8090; PPC64LE-NEXT: sync
8091; PPC64LE-NEXT: .LBB479_1:
8092; PPC64LE-NEXT: ldarx 5, 0, 3
8093; PPC64LE-NEXT: xor 6, 4, 5
8094; PPC64LE-NEXT: stdcx. 6, 0, 3
8095; PPC64LE-NEXT: bne 0, .LBB479_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8096; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8097; PPC64LE-NEXT: mr 3, 5
8098; PPC64LE-NEXT: lwsync
8099; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8100 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8101 ret i64 %ret
8102}
8103
8104define i8 @test480(i8* %ptr, i8 %val) {
8105; PPC64LE-LABEL: test480:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8106; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8107; PPC64LE-NEXT: .LBB480_1:
8108; PPC64LE-NEXT: lbarx 5, 0, 3
8109; PPC64LE-NEXT: extsb 6, 5
8110; PPC64LE-NEXT: cmpw 4, 6
8111; PPC64LE-NEXT: ble 0, .LBB480_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8112; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8113; PPC64LE-NEXT: stbcx. 4, 0, 3
8114; PPC64LE-NEXT: bne 0, .LBB480_1
8115; PPC64LE-NEXT: .LBB480_3:
8116; PPC64LE-NEXT: mr 3, 5
8117; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8118 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8119 ret i8 %ret
8120}
8121
8122define i8 @test481(i8* %ptr, i8 %val) {
8123; PPC64LE-LABEL: test481:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8124; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8125; PPC64LE-NEXT: mr 5, 3
8126; PPC64LE-NEXT: .LBB481_1:
8127; PPC64LE-NEXT: lbarx 3, 0, 5
8128; PPC64LE-NEXT: extsb 6, 3
8129; PPC64LE-NEXT: cmpw 4, 6
8130; PPC64LE-NEXT: ble 0, .LBB481_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8131; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8132; PPC64LE-NEXT: stbcx. 4, 0, 5
8133; PPC64LE-NEXT: bne 0, .LBB481_1
8134; PPC64LE-NEXT: .LBB481_3:
8135; PPC64LE-NEXT: lwsync
8136; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8137 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8138 ret i8 %ret
8139}
8140
8141define i8 @test482(i8* %ptr, i8 %val) {
8142; PPC64LE-LABEL: test482:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8143; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8144; PPC64LE-NEXT: lwsync
8145; PPC64LE-NEXT: .LBB482_1:
8146; PPC64LE-NEXT: lbarx 5, 0, 3
8147; PPC64LE-NEXT: extsb 6, 5
8148; PPC64LE-NEXT: cmpw 4, 6
8149; PPC64LE-NEXT: ble 0, .LBB482_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8150; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8151; PPC64LE-NEXT: stbcx. 4, 0, 3
8152; PPC64LE-NEXT: bne 0, .LBB482_1
8153; PPC64LE-NEXT: .LBB482_3:
8154; PPC64LE-NEXT: mr 3, 5
8155; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8156 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8157 ret i8 %ret
8158}
8159
8160define i8 @test483(i8* %ptr, i8 %val) {
8161; PPC64LE-LABEL: test483:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8162; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8163; PPC64LE-NEXT: lwsync
8164; PPC64LE-NEXT: .LBB483_1:
8165; PPC64LE-NEXT: lbarx 5, 0, 3
8166; PPC64LE-NEXT: extsb 6, 5
8167; PPC64LE-NEXT: cmpw 4, 6
8168; PPC64LE-NEXT: ble 0, .LBB483_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8169; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8170; PPC64LE-NEXT: stbcx. 4, 0, 3
8171; PPC64LE-NEXT: bne 0, .LBB483_1
8172; PPC64LE-NEXT: .LBB483_3:
8173; PPC64LE-NEXT: mr 3, 5
8174; PPC64LE-NEXT: lwsync
8175; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8176 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8177 ret i8 %ret
8178}
8179
8180define i8 @test484(i8* %ptr, i8 %val) {
8181; PPC64LE-LABEL: test484:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8182; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8183; PPC64LE-NEXT: sync
8184; PPC64LE-NEXT: .LBB484_1:
8185; PPC64LE-NEXT: lbarx 5, 0, 3
8186; PPC64LE-NEXT: extsb 6, 5
8187; PPC64LE-NEXT: cmpw 4, 6
8188; PPC64LE-NEXT: ble 0, .LBB484_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8189; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8190; PPC64LE-NEXT: stbcx. 4, 0, 3
8191; PPC64LE-NEXT: bne 0, .LBB484_1
8192; PPC64LE-NEXT: .LBB484_3:
8193; PPC64LE-NEXT: mr 3, 5
8194; PPC64LE-NEXT: lwsync
8195; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8196 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8197 ret i8 %ret
8198}
8199
8200define i16 @test485(i16* %ptr, i16 %val) {
8201; PPC64LE-LABEL: test485:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8202; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8203; PPC64LE-NEXT: .LBB485_1:
8204; PPC64LE-NEXT: lharx 5, 0, 3
8205; PPC64LE-NEXT: extsh 6, 5
8206; PPC64LE-NEXT: cmpw 4, 6
8207; PPC64LE-NEXT: ble 0, .LBB485_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8208; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8209; PPC64LE-NEXT: sthcx. 4, 0, 3
8210; PPC64LE-NEXT: bne 0, .LBB485_1
8211; PPC64LE-NEXT: .LBB485_3:
8212; PPC64LE-NEXT: mr 3, 5
8213; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8214 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8215 ret i16 %ret
8216}
8217
8218define i16 @test486(i16* %ptr, i16 %val) {
8219; PPC64LE-LABEL: test486:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8220; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8221; PPC64LE-NEXT: mr 5, 3
8222; PPC64LE-NEXT: .LBB486_1:
8223; PPC64LE-NEXT: lharx 3, 0, 5
8224; PPC64LE-NEXT: extsh 6, 3
8225; PPC64LE-NEXT: cmpw 4, 6
8226; PPC64LE-NEXT: ble 0, .LBB486_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8227; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8228; PPC64LE-NEXT: sthcx. 4, 0, 5
8229; PPC64LE-NEXT: bne 0, .LBB486_1
8230; PPC64LE-NEXT: .LBB486_3:
8231; PPC64LE-NEXT: lwsync
8232; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8233 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8234 ret i16 %ret
8235}
8236
8237define i16 @test487(i16* %ptr, i16 %val) {
8238; PPC64LE-LABEL: test487:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8239; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8240; PPC64LE-NEXT: lwsync
8241; PPC64LE-NEXT: .LBB487_1:
8242; PPC64LE-NEXT: lharx 5, 0, 3
8243; PPC64LE-NEXT: extsh 6, 5
8244; PPC64LE-NEXT: cmpw 4, 6
8245; PPC64LE-NEXT: ble 0, .LBB487_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8246; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8247; PPC64LE-NEXT: sthcx. 4, 0, 3
8248; PPC64LE-NEXT: bne 0, .LBB487_1
8249; PPC64LE-NEXT: .LBB487_3:
8250; PPC64LE-NEXT: mr 3, 5
8251; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8252 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8253 ret i16 %ret
8254}
8255
8256define i16 @test488(i16* %ptr, i16 %val) {
8257; PPC64LE-LABEL: test488:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8258; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8259; PPC64LE-NEXT: lwsync
8260; PPC64LE-NEXT: .LBB488_1:
8261; PPC64LE-NEXT: lharx 5, 0, 3
8262; PPC64LE-NEXT: extsh 6, 5
8263; PPC64LE-NEXT: cmpw 4, 6
8264; PPC64LE-NEXT: ble 0, .LBB488_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8265; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8266; PPC64LE-NEXT: sthcx. 4, 0, 3
8267; PPC64LE-NEXT: bne 0, .LBB488_1
8268; PPC64LE-NEXT: .LBB488_3:
8269; PPC64LE-NEXT: mr 3, 5
8270; PPC64LE-NEXT: lwsync
8271; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8272 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8273 ret i16 %ret
8274}
8275
8276define i16 @test489(i16* %ptr, i16 %val) {
8277; PPC64LE-LABEL: test489:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8278; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8279; PPC64LE-NEXT: sync
8280; PPC64LE-NEXT: .LBB489_1:
8281; PPC64LE-NEXT: lharx 5, 0, 3
8282; PPC64LE-NEXT: extsh 6, 5
8283; PPC64LE-NEXT: cmpw 4, 6
8284; PPC64LE-NEXT: ble 0, .LBB489_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8285; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8286; PPC64LE-NEXT: sthcx. 4, 0, 3
8287; PPC64LE-NEXT: bne 0, .LBB489_1
8288; PPC64LE-NEXT: .LBB489_3:
8289; PPC64LE-NEXT: mr 3, 5
8290; PPC64LE-NEXT: lwsync
8291; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8292 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8293 ret i16 %ret
8294}
8295
8296define i32 @test490(i32* %ptr, i32 %val) {
8297; PPC64LE-LABEL: test490:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8298; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8299; PPC64LE-NEXT: .LBB490_1:
8300; PPC64LE-NEXT: lwarx 5, 0, 3
8301; PPC64LE-NEXT: cmpw 4, 5
8302; PPC64LE-NEXT: ble 0, .LBB490_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8303; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8304; PPC64LE-NEXT: stwcx. 4, 0, 3
8305; PPC64LE-NEXT: bne 0, .LBB490_1
8306; PPC64LE-NEXT: .LBB490_3:
8307; PPC64LE-NEXT: mr 3, 5
8308; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8309 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8310 ret i32 %ret
8311}
8312
8313define i32 @test491(i32* %ptr, i32 %val) {
8314; PPC64LE-LABEL: test491:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8315; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8316; PPC64LE-NEXT: mr 5, 3
8317; PPC64LE-NEXT: .LBB491_1:
8318; PPC64LE-NEXT: lwarx 3, 0, 5
8319; PPC64LE-NEXT: cmpw 4, 3
8320; PPC64LE-NEXT: ble 0, .LBB491_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8321; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8322; PPC64LE-NEXT: stwcx. 4, 0, 5
8323; PPC64LE-NEXT: bne 0, .LBB491_1
8324; PPC64LE-NEXT: .LBB491_3:
8325; PPC64LE-NEXT: lwsync
8326; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8327 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8328 ret i32 %ret
8329}
8330
8331define i32 @test492(i32* %ptr, i32 %val) {
8332; PPC64LE-LABEL: test492:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8333; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8334; PPC64LE-NEXT: lwsync
8335; PPC64LE-NEXT: .LBB492_1:
8336; PPC64LE-NEXT: lwarx 5, 0, 3
8337; PPC64LE-NEXT: cmpw 4, 5
8338; PPC64LE-NEXT: ble 0, .LBB492_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8339; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8340; PPC64LE-NEXT: stwcx. 4, 0, 3
8341; PPC64LE-NEXT: bne 0, .LBB492_1
8342; PPC64LE-NEXT: .LBB492_3:
8343; PPC64LE-NEXT: mr 3, 5
8344; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8345 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8346 ret i32 %ret
8347}
8348
8349define i32 @test493(i32* %ptr, i32 %val) {
8350; PPC64LE-LABEL: test493:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8351; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8352; PPC64LE-NEXT: lwsync
8353; PPC64LE-NEXT: .LBB493_1:
8354; PPC64LE-NEXT: lwarx 5, 0, 3
8355; PPC64LE-NEXT: cmpw 4, 5
8356; PPC64LE-NEXT: ble 0, .LBB493_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8357; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8358; PPC64LE-NEXT: stwcx. 4, 0, 3
8359; PPC64LE-NEXT: bne 0, .LBB493_1
8360; PPC64LE-NEXT: .LBB493_3:
8361; PPC64LE-NEXT: mr 3, 5
8362; PPC64LE-NEXT: lwsync
8363; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8364 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8365 ret i32 %ret
8366}
8367
8368define i32 @test494(i32* %ptr, i32 %val) {
8369; PPC64LE-LABEL: test494:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8370; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8371; PPC64LE-NEXT: sync
8372; PPC64LE-NEXT: .LBB494_1:
8373; PPC64LE-NEXT: lwarx 5, 0, 3
8374; PPC64LE-NEXT: cmpw 4, 5
8375; PPC64LE-NEXT: ble 0, .LBB494_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8376; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8377; PPC64LE-NEXT: stwcx. 4, 0, 3
8378; PPC64LE-NEXT: bne 0, .LBB494_1
8379; PPC64LE-NEXT: .LBB494_3:
8380; PPC64LE-NEXT: mr 3, 5
8381; PPC64LE-NEXT: lwsync
8382; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8383 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8384 ret i32 %ret
8385}
8386
8387define i64 @test495(i64* %ptr, i64 %val) {
8388; PPC64LE-LABEL: test495:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8389; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8390; PPC64LE-NEXT: .LBB495_1:
8391; PPC64LE-NEXT: ldarx 5, 0, 3
8392; PPC64LE-NEXT: cmpd 4, 5
8393; PPC64LE-NEXT: ble 0, .LBB495_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8394; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8395; PPC64LE-NEXT: stdcx. 4, 0, 3
8396; PPC64LE-NEXT: bne 0, .LBB495_1
8397; PPC64LE-NEXT: .LBB495_3:
8398; PPC64LE-NEXT: mr 3, 5
8399; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8400 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8401 ret i64 %ret
8402}
8403
8404define i64 @test496(i64* %ptr, i64 %val) {
8405; PPC64LE-LABEL: test496:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8406; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8407; PPC64LE-NEXT: mr 5, 3
8408; PPC64LE-NEXT: .LBB496_1:
8409; PPC64LE-NEXT: ldarx 3, 0, 5
8410; PPC64LE-NEXT: cmpd 4, 3
8411; PPC64LE-NEXT: ble 0, .LBB496_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8412; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8413; PPC64LE-NEXT: stdcx. 4, 0, 5
8414; PPC64LE-NEXT: bne 0, .LBB496_1
8415; PPC64LE-NEXT: .LBB496_3:
8416; PPC64LE-NEXT: lwsync
8417; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8418 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8419 ret i64 %ret
8420}
8421
8422define i64 @test497(i64* %ptr, i64 %val) {
8423; PPC64LE-LABEL: test497:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8424; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8425; PPC64LE-NEXT: lwsync
8426; PPC64LE-NEXT: .LBB497_1:
8427; PPC64LE-NEXT: ldarx 5, 0, 3
8428; PPC64LE-NEXT: cmpd 4, 5
8429; PPC64LE-NEXT: ble 0, .LBB497_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8430; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8431; PPC64LE-NEXT: stdcx. 4, 0, 3
8432; PPC64LE-NEXT: bne 0, .LBB497_1
8433; PPC64LE-NEXT: .LBB497_3:
8434; PPC64LE-NEXT: mr 3, 5
8435; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8436 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8437 ret i64 %ret
8438}
8439
8440define i64 @test498(i64* %ptr, i64 %val) {
8441; PPC64LE-LABEL: test498:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8442; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8443; PPC64LE-NEXT: lwsync
8444; PPC64LE-NEXT: .LBB498_1:
8445; PPC64LE-NEXT: ldarx 5, 0, 3
8446; PPC64LE-NEXT: cmpd 4, 5
8447; PPC64LE-NEXT: ble 0, .LBB498_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8448; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8449; PPC64LE-NEXT: stdcx. 4, 0, 3
8450; PPC64LE-NEXT: bne 0, .LBB498_1
8451; PPC64LE-NEXT: .LBB498_3:
8452; PPC64LE-NEXT: mr 3, 5
8453; PPC64LE-NEXT: lwsync
8454; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8455 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8456 ret i64 %ret
8457}
8458
8459define i64 @test499(i64* %ptr, i64 %val) {
8460; PPC64LE-LABEL: test499:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8461; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8462; PPC64LE-NEXT: sync
8463; PPC64LE-NEXT: .LBB499_1:
8464; PPC64LE-NEXT: ldarx 5, 0, 3
8465; PPC64LE-NEXT: cmpd 4, 5
8466; PPC64LE-NEXT: ble 0, .LBB499_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8467; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8468; PPC64LE-NEXT: stdcx. 4, 0, 3
8469; PPC64LE-NEXT: bne 0, .LBB499_1
8470; PPC64LE-NEXT: .LBB499_3:
8471; PPC64LE-NEXT: mr 3, 5
8472; PPC64LE-NEXT: lwsync
8473; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8474 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8475 ret i64 %ret
8476}
8477
8478define i8 @test500(i8* %ptr, i8 %val) {
8479; PPC64LE-LABEL: test500:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8480; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8481; PPC64LE-NEXT: .LBB500_1:
8482; PPC64LE-NEXT: lbarx 5, 0, 3
8483; PPC64LE-NEXT: extsb 6, 5
8484; PPC64LE-NEXT: cmpw 4, 6
8485; PPC64LE-NEXT: bge 0, .LBB500_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8486; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8487; PPC64LE-NEXT: stbcx. 4, 0, 3
8488; PPC64LE-NEXT: bne 0, .LBB500_1
8489; PPC64LE-NEXT: .LBB500_3:
8490; PPC64LE-NEXT: mr 3, 5
8491; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8492 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8493 ret i8 %ret
8494}
8495
8496define i8 @test501(i8* %ptr, i8 %val) {
8497; PPC64LE-LABEL: test501:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8498; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8499; PPC64LE-NEXT: mr 5, 3
8500; PPC64LE-NEXT: .LBB501_1:
8501; PPC64LE-NEXT: lbarx 3, 0, 5
8502; PPC64LE-NEXT: extsb 6, 3
8503; PPC64LE-NEXT: cmpw 4, 6
8504; PPC64LE-NEXT: bge 0, .LBB501_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8505; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8506; PPC64LE-NEXT: stbcx. 4, 0, 5
8507; PPC64LE-NEXT: bne 0, .LBB501_1
8508; PPC64LE-NEXT: .LBB501_3:
8509; PPC64LE-NEXT: lwsync
8510; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8511 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8512 ret i8 %ret
8513}
8514
8515define i8 @test502(i8* %ptr, i8 %val) {
8516; PPC64LE-LABEL: test502:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8517; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8518; PPC64LE-NEXT: lwsync
8519; PPC64LE-NEXT: .LBB502_1:
8520; PPC64LE-NEXT: lbarx 5, 0, 3
8521; PPC64LE-NEXT: extsb 6, 5
8522; PPC64LE-NEXT: cmpw 4, 6
8523; PPC64LE-NEXT: bge 0, .LBB502_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8524; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8525; PPC64LE-NEXT: stbcx. 4, 0, 3
8526; PPC64LE-NEXT: bne 0, .LBB502_1
8527; PPC64LE-NEXT: .LBB502_3:
8528; PPC64LE-NEXT: mr 3, 5
8529; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8530 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8531 ret i8 %ret
8532}
8533
8534define i8 @test503(i8* %ptr, i8 %val) {
8535; PPC64LE-LABEL: test503:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8536; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8537; PPC64LE-NEXT: lwsync
8538; PPC64LE-NEXT: .LBB503_1:
8539; PPC64LE-NEXT: lbarx 5, 0, 3
8540; PPC64LE-NEXT: extsb 6, 5
8541; PPC64LE-NEXT: cmpw 4, 6
8542; PPC64LE-NEXT: bge 0, .LBB503_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8543; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8544; PPC64LE-NEXT: stbcx. 4, 0, 3
8545; PPC64LE-NEXT: bne 0, .LBB503_1
8546; PPC64LE-NEXT: .LBB503_3:
8547; PPC64LE-NEXT: mr 3, 5
8548; PPC64LE-NEXT: lwsync
8549; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8550 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8551 ret i8 %ret
8552}
8553
8554define i8 @test504(i8* %ptr, i8 %val) {
8555; PPC64LE-LABEL: test504:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8556; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8557; PPC64LE-NEXT: sync
8558; PPC64LE-NEXT: .LBB504_1:
8559; PPC64LE-NEXT: lbarx 5, 0, 3
8560; PPC64LE-NEXT: extsb 6, 5
8561; PPC64LE-NEXT: cmpw 4, 6
8562; PPC64LE-NEXT: bge 0, .LBB504_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8563; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8564; PPC64LE-NEXT: stbcx. 4, 0, 3
8565; PPC64LE-NEXT: bne 0, .LBB504_1
8566; PPC64LE-NEXT: .LBB504_3:
8567; PPC64LE-NEXT: mr 3, 5
8568; PPC64LE-NEXT: lwsync
8569; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8570 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8571 ret i8 %ret
8572}
8573
8574define i16 @test505(i16* %ptr, i16 %val) {
8575; PPC64LE-LABEL: test505:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8576; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8577; PPC64LE-NEXT: .LBB505_1:
8578; PPC64LE-NEXT: lharx 5, 0, 3
8579; PPC64LE-NEXT: extsh 6, 5
8580; PPC64LE-NEXT: cmpw 4, 6
8581; PPC64LE-NEXT: bge 0, .LBB505_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8582; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8583; PPC64LE-NEXT: sthcx. 4, 0, 3
8584; PPC64LE-NEXT: bne 0, .LBB505_1
8585; PPC64LE-NEXT: .LBB505_3:
8586; PPC64LE-NEXT: mr 3, 5
8587; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8588 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8589 ret i16 %ret
8590}
8591
8592define i16 @test506(i16* %ptr, i16 %val) {
8593; PPC64LE-LABEL: test506:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8594; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8595; PPC64LE-NEXT: mr 5, 3
8596; PPC64LE-NEXT: .LBB506_1:
8597; PPC64LE-NEXT: lharx 3, 0, 5
8598; PPC64LE-NEXT: extsh 6, 3
8599; PPC64LE-NEXT: cmpw 4, 6
8600; PPC64LE-NEXT: bge 0, .LBB506_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8601; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8602; PPC64LE-NEXT: sthcx. 4, 0, 5
8603; PPC64LE-NEXT: bne 0, .LBB506_1
8604; PPC64LE-NEXT: .LBB506_3:
8605; PPC64LE-NEXT: lwsync
8606; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8607 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8608 ret i16 %ret
8609}
8610
8611define i16 @test507(i16* %ptr, i16 %val) {
8612; PPC64LE-LABEL: test507:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8613; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8614; PPC64LE-NEXT: lwsync
8615; PPC64LE-NEXT: .LBB507_1:
8616; PPC64LE-NEXT: lharx 5, 0, 3
8617; PPC64LE-NEXT: extsh 6, 5
8618; PPC64LE-NEXT: cmpw 4, 6
8619; PPC64LE-NEXT: bge 0, .LBB507_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8620; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8621; PPC64LE-NEXT: sthcx. 4, 0, 3
8622; PPC64LE-NEXT: bne 0, .LBB507_1
8623; PPC64LE-NEXT: .LBB507_3:
8624; PPC64LE-NEXT: mr 3, 5
8625; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8626 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8627 ret i16 %ret
8628}
8629
8630define i16 @test508(i16* %ptr, i16 %val) {
8631; PPC64LE-LABEL: test508:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8632; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8633; PPC64LE-NEXT: lwsync
8634; PPC64LE-NEXT: .LBB508_1:
8635; PPC64LE-NEXT: lharx 5, 0, 3
8636; PPC64LE-NEXT: extsh 6, 5
8637; PPC64LE-NEXT: cmpw 4, 6
8638; PPC64LE-NEXT: bge 0, .LBB508_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8639; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8640; PPC64LE-NEXT: sthcx. 4, 0, 3
8641; PPC64LE-NEXT: bne 0, .LBB508_1
8642; PPC64LE-NEXT: .LBB508_3:
8643; PPC64LE-NEXT: mr 3, 5
8644; PPC64LE-NEXT: lwsync
8645; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8646 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8647 ret i16 %ret
8648}
8649
8650define i16 @test509(i16* %ptr, i16 %val) {
8651; PPC64LE-LABEL: test509:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8652; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8653; PPC64LE-NEXT: sync
8654; PPC64LE-NEXT: .LBB509_1:
8655; PPC64LE-NEXT: lharx 5, 0, 3
8656; PPC64LE-NEXT: extsh 6, 5
8657; PPC64LE-NEXT: cmpw 4, 6
8658; PPC64LE-NEXT: bge 0, .LBB509_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8659; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8660; PPC64LE-NEXT: sthcx. 4, 0, 3
8661; PPC64LE-NEXT: bne 0, .LBB509_1
8662; PPC64LE-NEXT: .LBB509_3:
8663; PPC64LE-NEXT: mr 3, 5
8664; PPC64LE-NEXT: lwsync
8665; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8666 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8667 ret i16 %ret
8668}
8669
8670define i32 @test510(i32* %ptr, i32 %val) {
8671; PPC64LE-LABEL: test510:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8672; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8673; PPC64LE-NEXT: .LBB510_1:
8674; PPC64LE-NEXT: lwarx 5, 0, 3
8675; PPC64LE-NEXT: cmpw 4, 5
8676; PPC64LE-NEXT: bge 0, .LBB510_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8677; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8678; PPC64LE-NEXT: stwcx. 4, 0, 3
8679; PPC64LE-NEXT: bne 0, .LBB510_1
8680; PPC64LE-NEXT: .LBB510_3:
8681; PPC64LE-NEXT: mr 3, 5
8682; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8683 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8684 ret i32 %ret
8685}
8686
8687define i32 @test511(i32* %ptr, i32 %val) {
8688; PPC64LE-LABEL: test511:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8689; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8690; PPC64LE-NEXT: mr 5, 3
8691; PPC64LE-NEXT: .LBB511_1:
8692; PPC64LE-NEXT: lwarx 3, 0, 5
8693; PPC64LE-NEXT: cmpw 4, 3
8694; PPC64LE-NEXT: bge 0, .LBB511_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8695; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8696; PPC64LE-NEXT: stwcx. 4, 0, 5
8697; PPC64LE-NEXT: bne 0, .LBB511_1
8698; PPC64LE-NEXT: .LBB511_3:
8699; PPC64LE-NEXT: lwsync
8700; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8701 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8702 ret i32 %ret
8703}
8704
8705define i32 @test512(i32* %ptr, i32 %val) {
8706; PPC64LE-LABEL: test512:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8707; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8708; PPC64LE-NEXT: lwsync
8709; PPC64LE-NEXT: .LBB512_1:
8710; PPC64LE-NEXT: lwarx 5, 0, 3
8711; PPC64LE-NEXT: cmpw 4, 5
8712; PPC64LE-NEXT: bge 0, .LBB512_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8713; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8714; PPC64LE-NEXT: stwcx. 4, 0, 3
8715; PPC64LE-NEXT: bne 0, .LBB512_1
8716; PPC64LE-NEXT: .LBB512_3:
8717; PPC64LE-NEXT: mr 3, 5
8718; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8719 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8720 ret i32 %ret
8721}
8722
8723define i32 @test513(i32* %ptr, i32 %val) {
8724; PPC64LE-LABEL: test513:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8725; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8726; PPC64LE-NEXT: lwsync
8727; PPC64LE-NEXT: .LBB513_1:
8728; PPC64LE-NEXT: lwarx 5, 0, 3
8729; PPC64LE-NEXT: cmpw 4, 5
8730; PPC64LE-NEXT: bge 0, .LBB513_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8731; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8732; PPC64LE-NEXT: stwcx. 4, 0, 3
8733; PPC64LE-NEXT: bne 0, .LBB513_1
8734; PPC64LE-NEXT: .LBB513_3:
8735; PPC64LE-NEXT: mr 3, 5
8736; PPC64LE-NEXT: lwsync
8737; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8738 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8739 ret i32 %ret
8740}
8741
8742define i32 @test514(i32* %ptr, i32 %val) {
8743; PPC64LE-LABEL: test514:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8744; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8745; PPC64LE-NEXT: sync
8746; PPC64LE-NEXT: .LBB514_1:
8747; PPC64LE-NEXT: lwarx 5, 0, 3
8748; PPC64LE-NEXT: cmpw 4, 5
8749; PPC64LE-NEXT: bge 0, .LBB514_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8750; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8751; PPC64LE-NEXT: stwcx. 4, 0, 3
8752; PPC64LE-NEXT: bne 0, .LBB514_1
8753; PPC64LE-NEXT: .LBB514_3:
8754; PPC64LE-NEXT: mr 3, 5
8755; PPC64LE-NEXT: lwsync
8756; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8757 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8758 ret i32 %ret
8759}
8760
8761define i64 @test515(i64* %ptr, i64 %val) {
8762; PPC64LE-LABEL: test515:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8763; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8764; PPC64LE-NEXT: .LBB515_1:
8765; PPC64LE-NEXT: ldarx 5, 0, 3
8766; PPC64LE-NEXT: cmpd 4, 5
8767; PPC64LE-NEXT: bge 0, .LBB515_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8768; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8769; PPC64LE-NEXT: stdcx. 4, 0, 3
8770; PPC64LE-NEXT: bne 0, .LBB515_1
8771; PPC64LE-NEXT: .LBB515_3:
8772; PPC64LE-NEXT: mr 3, 5
8773; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8774 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8775 ret i64 %ret
8776}
8777
8778define i64 @test516(i64* %ptr, i64 %val) {
8779; PPC64LE-LABEL: test516:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8780; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8781; PPC64LE-NEXT: mr 5, 3
8782; PPC64LE-NEXT: .LBB516_1:
8783; PPC64LE-NEXT: ldarx 3, 0, 5
8784; PPC64LE-NEXT: cmpd 4, 3
8785; PPC64LE-NEXT: bge 0, .LBB516_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8786; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8787; PPC64LE-NEXT: stdcx. 4, 0, 5
8788; PPC64LE-NEXT: bne 0, .LBB516_1
8789; PPC64LE-NEXT: .LBB516_3:
8790; PPC64LE-NEXT: lwsync
8791; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8792 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8793 ret i64 %ret
8794}
8795
8796define i64 @test517(i64* %ptr, i64 %val) {
8797; PPC64LE-LABEL: test517:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8798; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8799; PPC64LE-NEXT: lwsync
8800; PPC64LE-NEXT: .LBB517_1:
8801; PPC64LE-NEXT: ldarx 5, 0, 3
8802; PPC64LE-NEXT: cmpd 4, 5
8803; PPC64LE-NEXT: bge 0, .LBB517_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8804; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8805; PPC64LE-NEXT: stdcx. 4, 0, 3
8806; PPC64LE-NEXT: bne 0, .LBB517_1
8807; PPC64LE-NEXT: .LBB517_3:
8808; PPC64LE-NEXT: mr 3, 5
8809; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8810 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8811 ret i64 %ret
8812}
8813
8814define i64 @test518(i64* %ptr, i64 %val) {
8815; PPC64LE-LABEL: test518:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8816; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8817; PPC64LE-NEXT: lwsync
8818; PPC64LE-NEXT: .LBB518_1:
8819; PPC64LE-NEXT: ldarx 5, 0, 3
8820; PPC64LE-NEXT: cmpd 4, 5
8821; PPC64LE-NEXT: bge 0, .LBB518_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8822; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8823; PPC64LE-NEXT: stdcx. 4, 0, 3
8824; PPC64LE-NEXT: bne 0, .LBB518_1
8825; PPC64LE-NEXT: .LBB518_3:
8826; PPC64LE-NEXT: mr 3, 5
8827; PPC64LE-NEXT: lwsync
8828; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8829 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8830 ret i64 %ret
8831}
8832
8833define i64 @test519(i64* %ptr, i64 %val) {
8834; PPC64LE-LABEL: test519:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8835; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8836; PPC64LE-NEXT: sync
8837; PPC64LE-NEXT: .LBB519_1:
8838; PPC64LE-NEXT: ldarx 5, 0, 3
8839; PPC64LE-NEXT: cmpd 4, 5
8840; PPC64LE-NEXT: bge 0, .LBB519_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8841; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8842; PPC64LE-NEXT: stdcx. 4, 0, 3
8843; PPC64LE-NEXT: bne 0, .LBB519_1
8844; PPC64LE-NEXT: .LBB519_3:
8845; PPC64LE-NEXT: mr 3, 5
8846; PPC64LE-NEXT: lwsync
8847; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8848 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8849 ret i64 %ret
8850}
8851
8852define i8 @test520(i8* %ptr, i8 %val) {
8853; PPC64LE-LABEL: test520:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8854; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8855; PPC64LE-NEXT: .LBB520_1:
8856; PPC64LE-NEXT: lbarx 5, 0, 3
8857; PPC64LE-NEXT: cmplw 4, 5
8858; PPC64LE-NEXT: ble 0, .LBB520_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8859; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8860; PPC64LE-NEXT: stbcx. 4, 0, 3
8861; PPC64LE-NEXT: bne 0, .LBB520_1
8862; PPC64LE-NEXT: .LBB520_3:
8863; PPC64LE-NEXT: mr 3, 5
8864; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8865 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8866 ret i8 %ret
8867}
8868
8869define i8 @test521(i8* %ptr, i8 %val) {
8870; PPC64LE-LABEL: test521:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8871; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8872; PPC64LE-NEXT: mr 5, 3
8873; PPC64LE-NEXT: .LBB521_1:
8874; PPC64LE-NEXT: lbarx 3, 0, 5
8875; PPC64LE-NEXT: cmplw 4, 3
8876; PPC64LE-NEXT: ble 0, .LBB521_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8877; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8878; PPC64LE-NEXT: stbcx. 4, 0, 5
8879; PPC64LE-NEXT: bne 0, .LBB521_1
8880; PPC64LE-NEXT: .LBB521_3:
8881; PPC64LE-NEXT: lwsync
8882; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8883 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8884 ret i8 %ret
8885}
8886
8887define i8 @test522(i8* %ptr, i8 %val) {
8888; PPC64LE-LABEL: test522:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8889; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8890; PPC64LE-NEXT: lwsync
8891; PPC64LE-NEXT: .LBB522_1:
8892; PPC64LE-NEXT: lbarx 5, 0, 3
8893; PPC64LE-NEXT: cmplw 4, 5
8894; PPC64LE-NEXT: ble 0, .LBB522_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8895; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8896; PPC64LE-NEXT: stbcx. 4, 0, 3
8897; PPC64LE-NEXT: bne 0, .LBB522_1
8898; PPC64LE-NEXT: .LBB522_3:
8899; PPC64LE-NEXT: mr 3, 5
8900; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8901 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8902 ret i8 %ret
8903}
8904
8905define i8 @test523(i8* %ptr, i8 %val) {
8906; PPC64LE-LABEL: test523:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8907; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8908; PPC64LE-NEXT: lwsync
8909; PPC64LE-NEXT: .LBB523_1:
8910; PPC64LE-NEXT: lbarx 5, 0, 3
8911; PPC64LE-NEXT: cmplw 4, 5
8912; PPC64LE-NEXT: ble 0, .LBB523_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8913; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8914; PPC64LE-NEXT: stbcx. 4, 0, 3
8915; PPC64LE-NEXT: bne 0, .LBB523_1
8916; PPC64LE-NEXT: .LBB523_3:
8917; PPC64LE-NEXT: mr 3, 5
8918; PPC64LE-NEXT: lwsync
8919; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8920 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8921 ret i8 %ret
8922}
8923
8924define i8 @test524(i8* %ptr, i8 %val) {
8925; PPC64LE-LABEL: test524:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8926; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8927; PPC64LE-NEXT: sync
8928; PPC64LE-NEXT: .LBB524_1:
8929; PPC64LE-NEXT: lbarx 5, 0, 3
8930; PPC64LE-NEXT: cmplw 4, 5
8931; PPC64LE-NEXT: ble 0, .LBB524_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8932; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8933; PPC64LE-NEXT: stbcx. 4, 0, 3
8934; PPC64LE-NEXT: bne 0, .LBB524_1
8935; PPC64LE-NEXT: .LBB524_3:
8936; PPC64LE-NEXT: mr 3, 5
8937; PPC64LE-NEXT: lwsync
8938; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8939 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8940 ret i8 %ret
8941}
8942
8943define i16 @test525(i16* %ptr, i16 %val) {
8944; PPC64LE-LABEL: test525:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8945; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8946; PPC64LE-NEXT: .LBB525_1:
8947; PPC64LE-NEXT: lharx 5, 0, 3
8948; PPC64LE-NEXT: cmplw 4, 5
8949; PPC64LE-NEXT: ble 0, .LBB525_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8950; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8951; PPC64LE-NEXT: sthcx. 4, 0, 3
8952; PPC64LE-NEXT: bne 0, .LBB525_1
8953; PPC64LE-NEXT: .LBB525_3:
8954; PPC64LE-NEXT: mr 3, 5
8955; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8956 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8957 ret i16 %ret
8958}
8959
8960define i16 @test526(i16* %ptr, i16 %val) {
8961; PPC64LE-LABEL: test526:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8962; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8963; PPC64LE-NEXT: mr 5, 3
8964; PPC64LE-NEXT: .LBB526_1:
8965; PPC64LE-NEXT: lharx 3, 0, 5
8966; PPC64LE-NEXT: cmplw 4, 3
8967; PPC64LE-NEXT: ble 0, .LBB526_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8968; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8969; PPC64LE-NEXT: sthcx. 4, 0, 5
8970; PPC64LE-NEXT: bne 0, .LBB526_1
8971; PPC64LE-NEXT: .LBB526_3:
8972; PPC64LE-NEXT: lwsync
8973; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8974 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8975 ret i16 %ret
8976}
8977
8978define i16 @test527(i16* %ptr, i16 %val) {
8979; PPC64LE-LABEL: test527:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8980; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8981; PPC64LE-NEXT: lwsync
8982; PPC64LE-NEXT: .LBB527_1:
8983; PPC64LE-NEXT: lharx 5, 0, 3
8984; PPC64LE-NEXT: cmplw 4, 5
8985; PPC64LE-NEXT: ble 0, .LBB527_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8986; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8987; PPC64LE-NEXT: sthcx. 4, 0, 3
8988; PPC64LE-NEXT: bne 0, .LBB527_1
8989; PPC64LE-NEXT: .LBB527_3:
8990; PPC64LE-NEXT: mr 3, 5
8991; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8992 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8993 ret i16 %ret
8994}
8995
8996define i16 @test528(i16* %ptr, i16 %val) {
8997; PPC64LE-LABEL: test528:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]8998; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8999; PPC64LE-NEXT: lwsync
9000; PPC64LE-NEXT: .LBB528_1:
9001; PPC64LE-NEXT: lharx 5, 0, 3
9002; PPC64LE-NEXT: cmplw 4, 5
9003; PPC64LE-NEXT: ble 0, .LBB528_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9004; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9005; PPC64LE-NEXT: sthcx. 4, 0, 3
9006; PPC64LE-NEXT: bne 0, .LBB528_1
9007; PPC64LE-NEXT: .LBB528_3:
9008; PPC64LE-NEXT: mr 3, 5
9009; PPC64LE-NEXT: lwsync
9010; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9011 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9012 ret i16 %ret
9013}
9014
9015define i16 @test529(i16* %ptr, i16 %val) {
9016; PPC64LE-LABEL: test529:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9017; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9018; PPC64LE-NEXT: sync
9019; PPC64LE-NEXT: .LBB529_1:
9020; PPC64LE-NEXT: lharx 5, 0, 3
9021; PPC64LE-NEXT: cmplw 4, 5
9022; PPC64LE-NEXT: ble 0, .LBB529_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9023; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9024; PPC64LE-NEXT: sthcx. 4, 0, 3
9025; PPC64LE-NEXT: bne 0, .LBB529_1
9026; PPC64LE-NEXT: .LBB529_3:
9027; PPC64LE-NEXT: mr 3, 5
9028; PPC64LE-NEXT: lwsync
9029; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9030 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9031 ret i16 %ret
9032}
9033
9034define i32 @test530(i32* %ptr, i32 %val) {
9035; PPC64LE-LABEL: test530:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9036; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9037; PPC64LE-NEXT: .LBB530_1:
9038; PPC64LE-NEXT: lwarx 5, 0, 3
9039; PPC64LE-NEXT: cmplw 4, 5
9040; PPC64LE-NEXT: ble 0, .LBB530_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9041; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9042; PPC64LE-NEXT: stwcx. 4, 0, 3
9043; PPC64LE-NEXT: bne 0, .LBB530_1
9044; PPC64LE-NEXT: .LBB530_3:
9045; PPC64LE-NEXT: mr 3, 5
9046; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9047 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9048 ret i32 %ret
9049}
9050
9051define i32 @test531(i32* %ptr, i32 %val) {
9052; PPC64LE-LABEL: test531:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9053; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9054; PPC64LE-NEXT: mr 5, 3
9055; PPC64LE-NEXT: .LBB531_1:
9056; PPC64LE-NEXT: lwarx 3, 0, 5
9057; PPC64LE-NEXT: cmplw 4, 3
9058; PPC64LE-NEXT: ble 0, .LBB531_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9059; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9060; PPC64LE-NEXT: stwcx. 4, 0, 5
9061; PPC64LE-NEXT: bne 0, .LBB531_1
9062; PPC64LE-NEXT: .LBB531_3:
9063; PPC64LE-NEXT: lwsync
9064; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9065 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9066 ret i32 %ret
9067}
9068
9069define i32 @test532(i32* %ptr, i32 %val) {
9070; PPC64LE-LABEL: test532:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9071; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9072; PPC64LE-NEXT: lwsync
9073; PPC64LE-NEXT: .LBB532_1:
9074; PPC64LE-NEXT: lwarx 5, 0, 3
9075; PPC64LE-NEXT: cmplw 4, 5
9076; PPC64LE-NEXT: ble 0, .LBB532_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9077; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9078; PPC64LE-NEXT: stwcx. 4, 0, 3
9079; PPC64LE-NEXT: bne 0, .LBB532_1
9080; PPC64LE-NEXT: .LBB532_3:
9081; PPC64LE-NEXT: mr 3, 5
9082; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9083 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9084 ret i32 %ret
9085}
9086
9087define i32 @test533(i32* %ptr, i32 %val) {
9088; PPC64LE-LABEL: test533:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9089; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9090; PPC64LE-NEXT: lwsync
9091; PPC64LE-NEXT: .LBB533_1:
9092; PPC64LE-NEXT: lwarx 5, 0, 3
9093; PPC64LE-NEXT: cmplw 4, 5
9094; PPC64LE-NEXT: ble 0, .LBB533_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9095; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9096; PPC64LE-NEXT: stwcx. 4, 0, 3
9097; PPC64LE-NEXT: bne 0, .LBB533_1
9098; PPC64LE-NEXT: .LBB533_3:
9099; PPC64LE-NEXT: mr 3, 5
9100; PPC64LE-NEXT: lwsync
9101; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9102 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9103 ret i32 %ret
9104}
9105
9106define i32 @test534(i32* %ptr, i32 %val) {
9107; PPC64LE-LABEL: test534:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9108; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9109; PPC64LE-NEXT: sync
9110; PPC64LE-NEXT: .LBB534_1:
9111; PPC64LE-NEXT: lwarx 5, 0, 3
9112; PPC64LE-NEXT: cmplw 4, 5
9113; PPC64LE-NEXT: ble 0, .LBB534_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9114; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9115; PPC64LE-NEXT: stwcx. 4, 0, 3
9116; PPC64LE-NEXT: bne 0, .LBB534_1
9117; PPC64LE-NEXT: .LBB534_3:
9118; PPC64LE-NEXT: mr 3, 5
9119; PPC64LE-NEXT: lwsync
9120; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9121 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9122 ret i32 %ret
9123}
9124
9125define i64 @test535(i64* %ptr, i64 %val) {
9126; PPC64LE-LABEL: test535:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9127; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9128; PPC64LE-NEXT: .LBB535_1:
9129; PPC64LE-NEXT: ldarx 5, 0, 3
9130; PPC64LE-NEXT: cmpld 4, 5
9131; PPC64LE-NEXT: ble 0, .LBB535_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9132; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9133; PPC64LE-NEXT: stdcx. 4, 0, 3
9134; PPC64LE-NEXT: bne 0, .LBB535_1
9135; PPC64LE-NEXT: .LBB535_3:
9136; PPC64LE-NEXT: mr 3, 5
9137; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9138 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9139 ret i64 %ret
9140}
9141
9142define i64 @test536(i64* %ptr, i64 %val) {
9143; PPC64LE-LABEL: test536:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9144; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9145; PPC64LE-NEXT: mr 5, 3
9146; PPC64LE-NEXT: .LBB536_1:
9147; PPC64LE-NEXT: ldarx 3, 0, 5
9148; PPC64LE-NEXT: cmpld 4, 3
9149; PPC64LE-NEXT: ble 0, .LBB536_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9150; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9151; PPC64LE-NEXT: stdcx. 4, 0, 5
9152; PPC64LE-NEXT: bne 0, .LBB536_1
9153; PPC64LE-NEXT: .LBB536_3:
9154; PPC64LE-NEXT: lwsync
9155; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9156 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9157 ret i64 %ret
9158}
9159
9160define i64 @test537(i64* %ptr, i64 %val) {
9161; PPC64LE-LABEL: test537:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9162; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9163; PPC64LE-NEXT: lwsync
9164; PPC64LE-NEXT: .LBB537_1:
9165; PPC64LE-NEXT: ldarx 5, 0, 3
9166; PPC64LE-NEXT: cmpld 4, 5
9167; PPC64LE-NEXT: ble 0, .LBB537_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9168; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9169; PPC64LE-NEXT: stdcx. 4, 0, 3
9170; PPC64LE-NEXT: bne 0, .LBB537_1
9171; PPC64LE-NEXT: .LBB537_3:
9172; PPC64LE-NEXT: mr 3, 5
9173; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9174 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9175 ret i64 %ret
9176}
9177
9178define i64 @test538(i64* %ptr, i64 %val) {
9179; PPC64LE-LABEL: test538:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9180; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9181; PPC64LE-NEXT: lwsync
9182; PPC64LE-NEXT: .LBB538_1:
9183; PPC64LE-NEXT: ldarx 5, 0, 3
9184; PPC64LE-NEXT: cmpld 4, 5
9185; PPC64LE-NEXT: ble 0, .LBB538_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9186; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9187; PPC64LE-NEXT: stdcx. 4, 0, 3
9188; PPC64LE-NEXT: bne 0, .LBB538_1
9189; PPC64LE-NEXT: .LBB538_3:
9190; PPC64LE-NEXT: mr 3, 5
9191; PPC64LE-NEXT: lwsync
9192; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9193 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9194 ret i64 %ret
9195}
9196
9197define i64 @test539(i64* %ptr, i64 %val) {
9198; PPC64LE-LABEL: test539:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9199; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9200; PPC64LE-NEXT: sync
9201; PPC64LE-NEXT: .LBB539_1:
9202; PPC64LE-NEXT: ldarx 5, 0, 3
9203; PPC64LE-NEXT: cmpld 4, 5
9204; PPC64LE-NEXT: ble 0, .LBB539_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9205; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9206; PPC64LE-NEXT: stdcx. 4, 0, 3
9207; PPC64LE-NEXT: bne 0, .LBB539_1
9208; PPC64LE-NEXT: .LBB539_3:
9209; PPC64LE-NEXT: mr 3, 5
9210; PPC64LE-NEXT: lwsync
9211; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9212 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9213 ret i64 %ret
9214}
9215
9216define i8 @test540(i8* %ptr, i8 %val) {
9217; PPC64LE-LABEL: test540:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9218; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9219; PPC64LE-NEXT: .LBB540_1:
9220; PPC64LE-NEXT: lbarx 5, 0, 3
9221; PPC64LE-NEXT: cmplw 4, 5
9222; PPC64LE-NEXT: bge 0, .LBB540_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9223; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9224; PPC64LE-NEXT: stbcx. 4, 0, 3
9225; PPC64LE-NEXT: bne 0, .LBB540_1
9226; PPC64LE-NEXT: .LBB540_3:
9227; PPC64LE-NEXT: mr 3, 5
9228; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9229 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9230 ret i8 %ret
9231}
9232
9233define i8 @test541(i8* %ptr, i8 %val) {
9234; PPC64LE-LABEL: test541:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9235; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9236; PPC64LE-NEXT: mr 5, 3
9237; PPC64LE-NEXT: .LBB541_1:
9238; PPC64LE-NEXT: lbarx 3, 0, 5
9239; PPC64LE-NEXT: cmplw 4, 3
9240; PPC64LE-NEXT: bge 0, .LBB541_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9241; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9242; PPC64LE-NEXT: stbcx. 4, 0, 5
9243; PPC64LE-NEXT: bne 0, .LBB541_1
9244; PPC64LE-NEXT: .LBB541_3:
9245; PPC64LE-NEXT: lwsync
9246; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9247 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9248 ret i8 %ret
9249}
9250
9251define i8 @test542(i8* %ptr, i8 %val) {
9252; PPC64LE-LABEL: test542:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9253; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9254; PPC64LE-NEXT: lwsync
9255; PPC64LE-NEXT: .LBB542_1:
9256; PPC64LE-NEXT: lbarx 5, 0, 3
9257; PPC64LE-NEXT: cmplw 4, 5
9258; PPC64LE-NEXT: bge 0, .LBB542_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9259; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9260; PPC64LE-NEXT: stbcx. 4, 0, 3
9261; PPC64LE-NEXT: bne 0, .LBB542_1
9262; PPC64LE-NEXT: .LBB542_3:
9263; PPC64LE-NEXT: mr 3, 5
9264; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9265 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9266 ret i8 %ret
9267}
9268
9269define i8 @test543(i8* %ptr, i8 %val) {
9270; PPC64LE-LABEL: test543:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9271; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9272; PPC64LE-NEXT: lwsync
9273; PPC64LE-NEXT: .LBB543_1:
9274; PPC64LE-NEXT: lbarx 5, 0, 3
9275; PPC64LE-NEXT: cmplw 4, 5
9276; PPC64LE-NEXT: bge 0, .LBB543_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9277; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9278; PPC64LE-NEXT: stbcx. 4, 0, 3
9279; PPC64LE-NEXT: bne 0, .LBB543_1
9280; PPC64LE-NEXT: .LBB543_3:
9281; PPC64LE-NEXT: mr 3, 5
9282; PPC64LE-NEXT: lwsync
9283; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9284 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9285 ret i8 %ret
9286}
9287
9288define i8 @test544(i8* %ptr, i8 %val) {
9289; PPC64LE-LABEL: test544:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9290; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9291; PPC64LE-NEXT: sync
9292; PPC64LE-NEXT: .LBB544_1:
9293; PPC64LE-NEXT: lbarx 5, 0, 3
9294; PPC64LE-NEXT: cmplw 4, 5
9295; PPC64LE-NEXT: bge 0, .LBB544_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9296; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9297; PPC64LE-NEXT: stbcx. 4, 0, 3
9298; PPC64LE-NEXT: bne 0, .LBB544_1
9299; PPC64LE-NEXT: .LBB544_3:
9300; PPC64LE-NEXT: mr 3, 5
9301; PPC64LE-NEXT: lwsync
9302; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9303 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9304 ret i8 %ret
9305}
9306
9307define i16 @test545(i16* %ptr, i16 %val) {
9308; PPC64LE-LABEL: test545:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9309; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9310; PPC64LE-NEXT: .LBB545_1:
9311; PPC64LE-NEXT: lharx 5, 0, 3
9312; PPC64LE-NEXT: cmplw 4, 5
9313; PPC64LE-NEXT: bge 0, .LBB545_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9314; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9315; PPC64LE-NEXT: sthcx. 4, 0, 3
9316; PPC64LE-NEXT: bne 0, .LBB545_1
9317; PPC64LE-NEXT: .LBB545_3:
9318; PPC64LE-NEXT: mr 3, 5
9319; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9320 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9321 ret i16 %ret
9322}
9323
9324define i16 @test546(i16* %ptr, i16 %val) {
9325; PPC64LE-LABEL: test546:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9326; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9327; PPC64LE-NEXT: mr 5, 3
9328; PPC64LE-NEXT: .LBB546_1:
9329; PPC64LE-NEXT: lharx 3, 0, 5
9330; PPC64LE-NEXT: cmplw 4, 3
9331; PPC64LE-NEXT: bge 0, .LBB546_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9332; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9333; PPC64LE-NEXT: sthcx. 4, 0, 5
9334; PPC64LE-NEXT: bne 0, .LBB546_1
9335; PPC64LE-NEXT: .LBB546_3:
9336; PPC64LE-NEXT: lwsync
9337; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9338 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9339 ret i16 %ret
9340}
9341
9342define i16 @test547(i16* %ptr, i16 %val) {
9343; PPC64LE-LABEL: test547:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9344; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9345; PPC64LE-NEXT: lwsync
9346; PPC64LE-NEXT: .LBB547_1:
9347; PPC64LE-NEXT: lharx 5, 0, 3
9348; PPC64LE-NEXT: cmplw 4, 5
9349; PPC64LE-NEXT: bge 0, .LBB547_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9350; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9351; PPC64LE-NEXT: sthcx. 4, 0, 3
9352; PPC64LE-NEXT: bne 0, .LBB547_1
9353; PPC64LE-NEXT: .LBB547_3:
9354; PPC64LE-NEXT: mr 3, 5
9355; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9356 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9357 ret i16 %ret
9358}
9359
9360define i16 @test548(i16* %ptr, i16 %val) {
9361; PPC64LE-LABEL: test548:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9362; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9363; PPC64LE-NEXT: lwsync
9364; PPC64LE-NEXT: .LBB548_1:
9365; PPC64LE-NEXT: lharx 5, 0, 3
9366; PPC64LE-NEXT: cmplw 4, 5
9367; PPC64LE-NEXT: bge 0, .LBB548_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9368; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9369; PPC64LE-NEXT: sthcx. 4, 0, 3
9370; PPC64LE-NEXT: bne 0, .LBB548_1
9371; PPC64LE-NEXT: .LBB548_3:
9372; PPC64LE-NEXT: mr 3, 5
9373; PPC64LE-NEXT: lwsync
9374; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9375 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9376 ret i16 %ret
9377}
9378
9379define i16 @test549(i16* %ptr, i16 %val) {
9380; PPC64LE-LABEL: test549:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9381; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9382; PPC64LE-NEXT: sync
9383; PPC64LE-NEXT: .LBB549_1:
9384; PPC64LE-NEXT: lharx 5, 0, 3
9385; PPC64LE-NEXT: cmplw 4, 5
9386; PPC64LE-NEXT: bge 0, .LBB549_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9387; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9388; PPC64LE-NEXT: sthcx. 4, 0, 3
9389; PPC64LE-NEXT: bne 0, .LBB549_1
9390; PPC64LE-NEXT: .LBB549_3:
9391; PPC64LE-NEXT: mr 3, 5
9392; PPC64LE-NEXT: lwsync
9393; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9394 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9395 ret i16 %ret
9396}
9397
9398define i32 @test550(i32* %ptr, i32 %val) {
9399; PPC64LE-LABEL: test550:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9400; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9401; PPC64LE-NEXT: .LBB550_1:
9402; PPC64LE-NEXT: lwarx 5, 0, 3
9403; PPC64LE-NEXT: cmplw 4, 5
9404; PPC64LE-NEXT: bge 0, .LBB550_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9405; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9406; PPC64LE-NEXT: stwcx. 4, 0, 3
9407; PPC64LE-NEXT: bne 0, .LBB550_1
9408; PPC64LE-NEXT: .LBB550_3:
9409; PPC64LE-NEXT: mr 3, 5
9410; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9411 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9412 ret i32 %ret
9413}
9414
9415define i32 @test551(i32* %ptr, i32 %val) {
9416; PPC64LE-LABEL: test551:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9417; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9418; PPC64LE-NEXT: mr 5, 3
9419; PPC64LE-NEXT: .LBB551_1:
9420; PPC64LE-NEXT: lwarx 3, 0, 5
9421; PPC64LE-NEXT: cmplw 4, 3
9422; PPC64LE-NEXT: bge 0, .LBB551_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9423; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9424; PPC64LE-NEXT: stwcx. 4, 0, 5
9425; PPC64LE-NEXT: bne 0, .LBB551_1
9426; PPC64LE-NEXT: .LBB551_3:
9427; PPC64LE-NEXT: lwsync
9428; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9429 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9430 ret i32 %ret
9431}
9432
9433define i32 @test552(i32* %ptr, i32 %val) {
9434; PPC64LE-LABEL: test552:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9435; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9436; PPC64LE-NEXT: lwsync
9437; PPC64LE-NEXT: .LBB552_1:
9438; PPC64LE-NEXT: lwarx 5, 0, 3
9439; PPC64LE-NEXT: cmplw 4, 5
9440; PPC64LE-NEXT: bge 0, .LBB552_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9441; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9442; PPC64LE-NEXT: stwcx. 4, 0, 3
9443; PPC64LE-NEXT: bne 0, .LBB552_1
9444; PPC64LE-NEXT: .LBB552_3:
9445; PPC64LE-NEXT: mr 3, 5
9446; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9447 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9448 ret i32 %ret
9449}
9450
9451define i32 @test553(i32* %ptr, i32 %val) {
9452; PPC64LE-LABEL: test553:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9453; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9454; PPC64LE-NEXT: lwsync
9455; PPC64LE-NEXT: .LBB553_1:
9456; PPC64LE-NEXT: lwarx 5, 0, 3
9457; PPC64LE-NEXT: cmplw 4, 5
9458; PPC64LE-NEXT: bge 0, .LBB553_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9459; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9460; PPC64LE-NEXT: stwcx. 4, 0, 3
9461; PPC64LE-NEXT: bne 0, .LBB553_1
9462; PPC64LE-NEXT: .LBB553_3:
9463; PPC64LE-NEXT: mr 3, 5
9464; PPC64LE-NEXT: lwsync
9465; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9466 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9467 ret i32 %ret
9468}
9469
9470define i32 @test554(i32* %ptr, i32 %val) {
9471; PPC64LE-LABEL: test554:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9472; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9473; PPC64LE-NEXT: sync
9474; PPC64LE-NEXT: .LBB554_1:
9475; PPC64LE-NEXT: lwarx 5, 0, 3
9476; PPC64LE-NEXT: cmplw 4, 5
9477; PPC64LE-NEXT: bge 0, .LBB554_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9478; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9479; PPC64LE-NEXT: stwcx. 4, 0, 3
9480; PPC64LE-NEXT: bne 0, .LBB554_1
9481; PPC64LE-NEXT: .LBB554_3:
9482; PPC64LE-NEXT: mr 3, 5
9483; PPC64LE-NEXT: lwsync
9484; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9485 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9486 ret i32 %ret
9487}
9488
9489define i64 @test555(i64* %ptr, i64 %val) {
9490; PPC64LE-LABEL: test555:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9491; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9492; PPC64LE-NEXT: .LBB555_1:
9493; PPC64LE-NEXT: ldarx 5, 0, 3
9494; PPC64LE-NEXT: cmpld 4, 5
9495; PPC64LE-NEXT: bge 0, .LBB555_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9496; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9497; PPC64LE-NEXT: stdcx. 4, 0, 3
9498; PPC64LE-NEXT: bne 0, .LBB555_1
9499; PPC64LE-NEXT: .LBB555_3:
9500; PPC64LE-NEXT: mr 3, 5
9501; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9502 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9503 ret i64 %ret
9504}
9505
9506define i64 @test556(i64* %ptr, i64 %val) {
9507; PPC64LE-LABEL: test556:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9508; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9509; PPC64LE-NEXT: mr 5, 3
9510; PPC64LE-NEXT: .LBB556_1:
9511; PPC64LE-NEXT: ldarx 3, 0, 5
9512; PPC64LE-NEXT: cmpld 4, 3
9513; PPC64LE-NEXT: bge 0, .LBB556_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9514; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9515; PPC64LE-NEXT: stdcx. 4, 0, 5
9516; PPC64LE-NEXT: bne 0, .LBB556_1
9517; PPC64LE-NEXT: .LBB556_3:
9518; PPC64LE-NEXT: lwsync
9519; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9520 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9521 ret i64 %ret
9522}
9523
9524define i64 @test557(i64* %ptr, i64 %val) {
9525; PPC64LE-LABEL: test557:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9526; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9527; PPC64LE-NEXT: lwsync
9528; PPC64LE-NEXT: .LBB557_1:
9529; PPC64LE-NEXT: ldarx 5, 0, 3
9530; PPC64LE-NEXT: cmpld 4, 5
9531; PPC64LE-NEXT: bge 0, .LBB557_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9532; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9533; PPC64LE-NEXT: stdcx. 4, 0, 3
9534; PPC64LE-NEXT: bne 0, .LBB557_1
9535; PPC64LE-NEXT: .LBB557_3:
9536; PPC64LE-NEXT: mr 3, 5
9537; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9538 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9539 ret i64 %ret
9540}
9541
9542define i64 @test558(i64* %ptr, i64 %val) {
9543; PPC64LE-LABEL: test558:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9544; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9545; PPC64LE-NEXT: lwsync
9546; PPC64LE-NEXT: .LBB558_1:
9547; PPC64LE-NEXT: ldarx 5, 0, 3
9548; PPC64LE-NEXT: cmpld 4, 5
9549; PPC64LE-NEXT: bge 0, .LBB558_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9550; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9551; PPC64LE-NEXT: stdcx. 4, 0, 3
9552; PPC64LE-NEXT: bne 0, .LBB558_1
9553; PPC64LE-NEXT: .LBB558_3:
9554; PPC64LE-NEXT: mr 3, 5
9555; PPC64LE-NEXT: lwsync
9556; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9557 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9558 ret i64 %ret
9559}
9560
9561define i64 @test559(i64* %ptr, i64 %val) {
9562; PPC64LE-LABEL: test559:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9563; PPC64LE: # %bb.0:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9564; PPC64LE-NEXT: sync
9565; PPC64LE-NEXT: .LBB559_1:
9566; PPC64LE-NEXT: ldarx 5, 0, 3
9567; PPC64LE-NEXT: cmpld 4, 5
9568; PPC64LE-NEXT: bge 0, .LBB559_3
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9569; PPC64LE-NEXT: # %bb.2:
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9570; PPC64LE-NEXT: stdcx. 4, 0, 3
9571; PPC64LE-NEXT: bne 0, .LBB559_1
9572; PPC64LE-NEXT: .LBB559_3:
9573; PPC64LE-NEXT: mr 3, 5
9574; PPC64LE-NEXT: lwsync
9575; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9576 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9577 ret i64 %ret
9578}
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]9579
9580; The second load should never be scheduled before isync.
9581define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) {
9582; PPC64LE-LABEL: test_ordering0:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9583; PPC64LE: # %bb.0:
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]9584; PPC64LE-NEXT: lwz 4, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]9585; PPC64LE-NEXT: cmpd 7, 4, 4
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]9586; PPC64LE-NEXT: bne- 7, .+4
9587; PPC64LE-NEXT: isync
9588; PPC64LE-NEXT: lwz 3, 0(3)
9589; PPC64LE-NEXT: add 3, 4, 3
9590; PPC64LE-NEXT: blr
9591 %val1 = load atomic i32, i32* %ptr1 acquire, align 4
9592 %val2 = load i32, i32* %ptr1
9593 %add = add i32 %val1, %val2
9594 ret i32 %add
9595}
9596
9597; The second store should never be scheduled before isync.
9598define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) {
9599; PPC64LE-LABEL: test_ordering1:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9600; PPC64LE: # %bb.0:
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]9601; PPC64LE-NEXT: lwz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]9602; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]9603; PPC64LE-NEXT: bne- 7, .+4
9604; PPC64LE-NEXT: isync
9605; PPC64LE-NEXT: stw 4, 0(5)
9606; PPC64LE-NEXT: blr
9607 %val2 = load atomic i32, i32* %ptr1 acquire, align 4
9608 store i32 %val1, i32* %ptr2
9609 ret i32 %val2
9610}