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gerrit-public.fairphone.software / toolchain / llvm-project / c066a92657a78f13b5e490e1b51c11d740671de0 / . / llvm / test / CodeGen / RISCV / vararg.ll
blob: 5d00a0e7f2a9f19cb0497623edcdad9413c65c66 [file] [log] [blame]
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]3; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
5; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]6
7declare void @llvm.va_start(i8*)
8declare void @llvm.va_end(i8*)
9
10declare void @notdead(i8*)
11
12; Although frontends are recommended to not generate va_arg due to the lack of
13; support for aggregate types, we test simple cases here to ensure they are
14; lowered correctly
15
16define i32 @va1(i8* %fmt, ...) nounwind {
17; RV32I-LABEL: va1:
18; RV32I: # %bb.0:
19; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]20; RV32I-NEXT: sw a1, 20(sp)
21; RV32I-NEXT: sw a7, 44(sp)
22; RV32I-NEXT: sw a6, 40(sp)
23; RV32I-NEXT: sw a5, 36(sp)
24; RV32I-NEXT: sw a4, 32(sp)
25; RV32I-NEXT: sw a3, 28(sp)
26; RV32I-NEXT: sw a2, 24(sp)
27; RV32I-NEXT: addi a0, sp, 24
28; RV32I-NEXT: sw a0, 12(sp)
29; RV32I-NEXT: lw a0, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]30; RV32I-NEXT: addi sp, sp, 48
31; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]32; RV32I-FPELIM-LABEL: va1:
33; RV32I-FPELIM: # %bb.0:
34; RV32I-FPELIM-NEXT: addi sp, sp, -48
35; RV32I-FPELIM-NEXT: sw a1, 20(sp)
36; RV32I-FPELIM-NEXT: sw a7, 44(sp)
37; RV32I-FPELIM-NEXT: sw a6, 40(sp)
38; RV32I-FPELIM-NEXT: sw a5, 36(sp)
39; RV32I-FPELIM-NEXT: sw a4, 32(sp)
40; RV32I-FPELIM-NEXT: sw a3, 28(sp)
41; RV32I-FPELIM-NEXT: sw a2, 24(sp)
42; RV32I-FPELIM-NEXT: addi a0, sp, 24
43; RV32I-FPELIM-NEXT: sw a0, 12(sp)
44; RV32I-FPELIM-NEXT: lw a0, 20(sp)
45; RV32I-FPELIM-NEXT: addi sp, sp, 48
46; RV32I-FPELIM-NEXT: ret
47;
48; RV32I-WITHFP-LABEL: va1:
49; RV32I-WITHFP: # %bb.0:
50; RV32I-WITHFP-NEXT: addi sp, sp, -48
51; RV32I-WITHFP-NEXT: sw ra, 12(sp)
52; RV32I-WITHFP-NEXT: sw s0, 8(sp)
53; RV32I-WITHFP-NEXT: addi s0, sp, 16
54; RV32I-WITHFP-NEXT: sw a1, 4(s0)
55; RV32I-WITHFP-NEXT: sw a7, 28(s0)
56; RV32I-WITHFP-NEXT: sw a6, 24(s0)
57; RV32I-WITHFP-NEXT: sw a5, 20(s0)
58; RV32I-WITHFP-NEXT: sw a4, 16(s0)
59; RV32I-WITHFP-NEXT: sw a3, 12(s0)
60; RV32I-WITHFP-NEXT: sw a2, 8(s0)
61; RV32I-WITHFP-NEXT: addi a0, s0, 8
62; RV32I-WITHFP-NEXT: sw a0, -12(s0)
63; RV32I-WITHFP-NEXT: lw a0, 4(s0)
64; RV32I-WITHFP-NEXT: lw s0, 8(sp)
65; RV32I-WITHFP-NEXT: lw ra, 12(sp)
66; RV32I-WITHFP-NEXT: addi sp, sp, 48
67; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]68 %va = alloca i8*, align 4
69 %1 = bitcast i8** %va to i8*
70 call void @llvm.va_start(i8* %1)
71 %argp.cur = load i8*, i8** %va, align 4
72 %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
73 store i8* %argp.next, i8** %va, align 4
74 %2 = bitcast i8* %argp.cur to i32*
75 %3 = load i32, i32* %2, align 4
76 call void @llvm.va_end(i8* %1)
77 ret i32 %3
78}
79
80define i32 @va1_va_arg(i8* %fmt, ...) nounwind {
81; RV32I-LABEL: va1_va_arg:
82; RV32I: # %bb.0:
83; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]84; RV32I-NEXT: sw a1, 20(sp)
85; RV32I-NEXT: sw a7, 44(sp)
86; RV32I-NEXT: sw a6, 40(sp)
87; RV32I-NEXT: sw a5, 36(sp)
88; RV32I-NEXT: sw a4, 32(sp)
89; RV32I-NEXT: sw a3, 28(sp)
90; RV32I-NEXT: sw a2, 24(sp)
91; RV32I-NEXT: addi a0, sp, 24
92; RV32I-NEXT: sw a0, 12(sp)
93; RV32I-NEXT: lw a0, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]94; RV32I-NEXT: addi sp, sp, 48
95; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]96; RV32I-FPELIM-LABEL: va1_va_arg:
97; RV32I-FPELIM: # %bb.0:
98; RV32I-FPELIM-NEXT: addi sp, sp, -48
99; RV32I-FPELIM-NEXT: sw a1, 20(sp)
100; RV32I-FPELIM-NEXT: sw a7, 44(sp)
101; RV32I-FPELIM-NEXT: sw a6, 40(sp)
102; RV32I-FPELIM-NEXT: sw a5, 36(sp)
103; RV32I-FPELIM-NEXT: sw a4, 32(sp)
104; RV32I-FPELIM-NEXT: sw a3, 28(sp)
105; RV32I-FPELIM-NEXT: sw a2, 24(sp)
106; RV32I-FPELIM-NEXT: addi a0, sp, 24
107; RV32I-FPELIM-NEXT: sw a0, 12(sp)
108; RV32I-FPELIM-NEXT: lw a0, 20(sp)
109; RV32I-FPELIM-NEXT: addi sp, sp, 48
110; RV32I-FPELIM-NEXT: ret
111;
112; RV32I-WITHFP-LABEL: va1_va_arg:
113; RV32I-WITHFP: # %bb.0:
114; RV32I-WITHFP-NEXT: addi sp, sp, -48
115; RV32I-WITHFP-NEXT: sw ra, 12(sp)
116; RV32I-WITHFP-NEXT: sw s0, 8(sp)
117; RV32I-WITHFP-NEXT: addi s0, sp, 16
118; RV32I-WITHFP-NEXT: sw a1, 4(s0)
119; RV32I-WITHFP-NEXT: sw a7, 28(s0)
120; RV32I-WITHFP-NEXT: sw a6, 24(s0)
121; RV32I-WITHFP-NEXT: sw a5, 20(s0)
122; RV32I-WITHFP-NEXT: sw a4, 16(s0)
123; RV32I-WITHFP-NEXT: sw a3, 12(s0)
124; RV32I-WITHFP-NEXT: sw a2, 8(s0)
125; RV32I-WITHFP-NEXT: addi a0, s0, 8
126; RV32I-WITHFP-NEXT: sw a0, -12(s0)
127; RV32I-WITHFP-NEXT: lw a0, 4(s0)
128; RV32I-WITHFP-NEXT: lw s0, 8(sp)
129; RV32I-WITHFP-NEXT: lw ra, 12(sp)
130; RV32I-WITHFP-NEXT: addi sp, sp, 48
131; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]132 %va = alloca i8*, align 4
133 %1 = bitcast i8** %va to i8*
134 call void @llvm.va_start(i8* %1)
135 %2 = va_arg i8** %va, i32
136 call void @llvm.va_end(i8* %1)
137 ret i32 %2
138}
139
140; Ensure the adjustment when restoring the stack pointer using the frame
141; pointer is correct
142define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind {
143; RV32I-LABEL: va1_va_arg_alloca:
144; RV32I: # %bb.0:
145; RV32I-NEXT: addi sp, sp, -48
146; RV32I-NEXT: sw ra, 12(sp)
147; RV32I-NEXT: sw s0, 8(sp)
148; RV32I-NEXT: sw s1, 4(sp)
149; RV32I-NEXT: addi s0, sp, 16
150; RV32I-NEXT: sw a1, 4(s0)
151; RV32I-NEXT: sw a7, 28(s0)
152; RV32I-NEXT: sw a6, 24(s0)
153; RV32I-NEXT: sw a5, 20(s0)
154; RV32I-NEXT: sw a4, 16(s0)
155; RV32I-NEXT: sw a3, 12(s0)
156; RV32I-NEXT: sw a2, 8(s0)
157; RV32I-NEXT: addi a0, s0, 8
158; RV32I-NEXT: sw a0, -16(s0)
159; RV32I-NEXT: lw s1, 4(s0)
160; RV32I-NEXT: addi a0, s1, 15
161; RV32I-NEXT: andi a0, a0, -16
162; RV32I-NEXT: sub a0, sp, a0
163; RV32I-NEXT: mv sp, a0
164; RV32I-NEXT: lui a1, %hi(notdead)
165; RV32I-NEXT: addi a1, a1, %lo(notdead)
166; RV32I-NEXT: jalr a1
167; RV32I-NEXT: mv a0, s1
168; RV32I-NEXT: addi sp, s0, -16
169; RV32I-NEXT: lw s1, 4(sp)
170; RV32I-NEXT: lw s0, 8(sp)
171; RV32I-NEXT: lw ra, 12(sp)
172; RV32I-NEXT: addi sp, sp, 48
173; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]174; RV32I-FPELIM-LABEL: va1_va_arg_alloca:
175; RV32I-FPELIM: # %bb.0:
176; RV32I-FPELIM-NEXT: addi sp, sp, -48
177; RV32I-FPELIM-NEXT: sw ra, 12(sp)
178; RV32I-FPELIM-NEXT: sw s0, 8(sp)
179; RV32I-FPELIM-NEXT: sw s1, 4(sp)
180; RV32I-FPELIM-NEXT: addi s0, sp, 16
181; RV32I-FPELIM-NEXT: sw a1, 4(s0)
182; RV32I-FPELIM-NEXT: sw a7, 28(s0)
183; RV32I-FPELIM-NEXT: sw a6, 24(s0)
184; RV32I-FPELIM-NEXT: sw a5, 20(s0)
185; RV32I-FPELIM-NEXT: sw a4, 16(s0)
186; RV32I-FPELIM-NEXT: sw a3, 12(s0)
187; RV32I-FPELIM-NEXT: sw a2, 8(s0)
188; RV32I-FPELIM-NEXT: addi a0, s0, 8
189; RV32I-FPELIM-NEXT: sw a0, -16(s0)
190; RV32I-FPELIM-NEXT: lw s1, 4(s0)
191; RV32I-FPELIM-NEXT: addi a0, s1, 15
192; RV32I-FPELIM-NEXT: andi a0, a0, -16
193; RV32I-FPELIM-NEXT: sub a0, sp, a0
194; RV32I-FPELIM-NEXT: mv sp, a0
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]195; RV32I-FPELIM-NEXT: call notdead
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]196; RV32I-FPELIM-NEXT: mv a0, s1
197; RV32I-FPELIM-NEXT: addi sp, s0, -16
198; RV32I-FPELIM-NEXT: lw s1, 4(sp)
199; RV32I-FPELIM-NEXT: lw s0, 8(sp)
200; RV32I-FPELIM-NEXT: lw ra, 12(sp)
201; RV32I-FPELIM-NEXT: addi sp, sp, 48
202; RV32I-FPELIM-NEXT: ret
203;
204; RV32I-WITHFP-LABEL: va1_va_arg_alloca:
205; RV32I-WITHFP: # %bb.0:
206; RV32I-WITHFP-NEXT: addi sp, sp, -48
207; RV32I-WITHFP-NEXT: sw ra, 12(sp)
208; RV32I-WITHFP-NEXT: sw s0, 8(sp)
209; RV32I-WITHFP-NEXT: sw s1, 4(sp)
210; RV32I-WITHFP-NEXT: addi s0, sp, 16
211; RV32I-WITHFP-NEXT: sw a1, 4(s0)
212; RV32I-WITHFP-NEXT: sw a7, 28(s0)
213; RV32I-WITHFP-NEXT: sw a6, 24(s0)
214; RV32I-WITHFP-NEXT: sw a5, 20(s0)
215; RV32I-WITHFP-NEXT: sw a4, 16(s0)
216; RV32I-WITHFP-NEXT: sw a3, 12(s0)
217; RV32I-WITHFP-NEXT: sw a2, 8(s0)
218; RV32I-WITHFP-NEXT: addi a0, s0, 8
219; RV32I-WITHFP-NEXT: sw a0, -16(s0)
220; RV32I-WITHFP-NEXT: lw s1, 4(s0)
221; RV32I-WITHFP-NEXT: addi a0, s1, 15
222; RV32I-WITHFP-NEXT: andi a0, a0, -16
223; RV32I-WITHFP-NEXT: sub a0, sp, a0
224; RV32I-WITHFP-NEXT: mv sp, a0
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]225; RV32I-WITHFP-NEXT: call notdead
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]226; RV32I-WITHFP-NEXT: mv a0, s1
227; RV32I-WITHFP-NEXT: addi sp, s0, -16
228; RV32I-WITHFP-NEXT: lw s1, 4(sp)
229; RV32I-WITHFP-NEXT: lw s0, 8(sp)
230; RV32I-WITHFP-NEXT: lw ra, 12(sp)
231; RV32I-WITHFP-NEXT: addi sp, sp, 48
232; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]233 %va = alloca i8*, align 4
234 %1 = bitcast i8** %va to i8*
235 call void @llvm.va_start(i8* %1)
236 %2 = va_arg i8** %va, i32
237 %3 = alloca i8, i32 %2
238 call void @notdead(i8* %3)
239 call void @llvm.va_end(i8* %1)
240 ret i32 %2
241}
242
243define void @va1_caller() nounwind {
244; RV32I-LABEL: va1_caller:
245; RV32I: # %bb.0:
246; RV32I-NEXT: addi sp, sp, -16
247; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]248; RV32I-NEXT: lui a0, 261888
249; RV32I-NEXT: mv a3, a0
250; RV32I-NEXT: lui a0, %hi(va1)
251; RV32I-NEXT: addi a0, a0, %lo(va1)
252; RV32I-NEXT: addi a4, zero, 2
253; RV32I-NEXT: mv a2, zero
254; RV32I-NEXT: jalr a0
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]255; RV32I-NEXT: lw ra, 12(sp)
256; RV32I-NEXT: addi sp, sp, 16
257; RV32I-NEXT: ret
258; Pass a double, as a float would be promoted by a C/C++ frontend
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]259; RV32I-FPELIM-LABEL: va1_caller:
260; RV32I-FPELIM: # %bb.0:
261; RV32I-FPELIM-NEXT: addi sp, sp, -16
262; RV32I-FPELIM-NEXT: sw ra, 12(sp)
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]263; RV32I-FPELIM-NEXT: lui a3, 261888
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]264; RV32I-FPELIM-NEXT: addi a4, zero, 2
265; RV32I-FPELIM-NEXT: mv a2, zero
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]266; RV32I-FPELIM-NEXT: call va1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]267; RV32I-FPELIM-NEXT: lw ra, 12(sp)
268; RV32I-FPELIM-NEXT: addi sp, sp, 16
269; RV32I-FPELIM-NEXT: ret
270;
271; RV32I-WITHFP-LABEL: va1_caller:
272; RV32I-WITHFP: # %bb.0:
273; RV32I-WITHFP-NEXT: addi sp, sp, -16
274; RV32I-WITHFP-NEXT: sw ra, 12(sp)
275; RV32I-WITHFP-NEXT: sw s0, 8(sp)
276; RV32I-WITHFP-NEXT: addi s0, sp, 16
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]277; RV32I-WITHFP-NEXT: lui a3, 261888
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]278; RV32I-WITHFP-NEXT: addi a4, zero, 2
279; RV32I-WITHFP-NEXT: mv a2, zero
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]280; RV32I-WITHFP-NEXT: call va1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]281; RV32I-WITHFP-NEXT: lw s0, 8(sp)
282; RV32I-WITHFP-NEXT: lw ra, 12(sp)
283; RV32I-WITHFP-NEXT: addi sp, sp, 16
284; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]285 %1 = call i32 (i8*, ...) @va1(i8* undef, double 1.0, i32 2)
286 ret void
287}
288
289; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
290; register pair (where the first register is even-numbered).
291
292define double @va2(i8 *%fmt, ...) nounwind {
293; RV32I-LABEL: va2:
294; RV32I: # %bb.0:
295; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]296; RV32I-NEXT: sw a7, 44(sp)
297; RV32I-NEXT: sw a6, 40(sp)
298; RV32I-NEXT: sw a5, 36(sp)
299; RV32I-NEXT: sw a4, 32(sp)
300; RV32I-NEXT: sw a3, 28(sp)
301; RV32I-NEXT: sw a2, 24(sp)
302; RV32I-NEXT: sw a1, 20(sp)
303; RV32I-NEXT: addi a0, sp, 35
304; RV32I-NEXT: sw a0, 12(sp)
305; RV32I-NEXT: addi a0, sp, 27
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]306; RV32I-NEXT: andi a1, a0, -8
307; RV32I-NEXT: lw a0, 0(a1)
308; RV32I-NEXT: ori a1, a1, 4
309; RV32I-NEXT: lw a1, 0(a1)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]310; RV32I-NEXT: addi sp, sp, 48
311; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]312; RV32I-FPELIM-LABEL: va2:
313; RV32I-FPELIM: # %bb.0:
314; RV32I-FPELIM-NEXT: addi sp, sp, -48
315; RV32I-FPELIM-NEXT: sw a7, 44(sp)
316; RV32I-FPELIM-NEXT: sw a6, 40(sp)
317; RV32I-FPELIM-NEXT: sw a5, 36(sp)
318; RV32I-FPELIM-NEXT: sw a4, 32(sp)
319; RV32I-FPELIM-NEXT: sw a3, 28(sp)
320; RV32I-FPELIM-NEXT: sw a2, 24(sp)
321; RV32I-FPELIM-NEXT: sw a1, 20(sp)
322; RV32I-FPELIM-NEXT: addi a0, sp, 35
323; RV32I-FPELIM-NEXT: sw a0, 12(sp)
324; RV32I-FPELIM-NEXT: addi a0, sp, 27
325; RV32I-FPELIM-NEXT: andi a1, a0, -8
326; RV32I-FPELIM-NEXT: lw a0, 0(a1)
327; RV32I-FPELIM-NEXT: ori a1, a1, 4
328; RV32I-FPELIM-NEXT: lw a1, 0(a1)
329; RV32I-FPELIM-NEXT: addi sp, sp, 48
330; RV32I-FPELIM-NEXT: ret
331;
332; RV32I-WITHFP-LABEL: va2:
333; RV32I-WITHFP: # %bb.0:
334; RV32I-WITHFP-NEXT: addi sp, sp, -48
335; RV32I-WITHFP-NEXT: sw ra, 12(sp)
336; RV32I-WITHFP-NEXT: sw s0, 8(sp)
337; RV32I-WITHFP-NEXT: addi s0, sp, 16
338; RV32I-WITHFP-NEXT: sw a7, 28(s0)
339; RV32I-WITHFP-NEXT: sw a6, 24(s0)
340; RV32I-WITHFP-NEXT: sw a5, 20(s0)
341; RV32I-WITHFP-NEXT: sw a4, 16(s0)
342; RV32I-WITHFP-NEXT: sw a3, 12(s0)
343; RV32I-WITHFP-NEXT: sw a2, 8(s0)
344; RV32I-WITHFP-NEXT: sw a1, 4(s0)
345; RV32I-WITHFP-NEXT: addi a0, s0, 19
346; RV32I-WITHFP-NEXT: sw a0, -12(s0)
347; RV32I-WITHFP-NEXT: addi a0, s0, 11
348; RV32I-WITHFP-NEXT: andi a1, a0, -8
349; RV32I-WITHFP-NEXT: lw a0, 0(a1)
350; RV32I-WITHFP-NEXT: ori a1, a1, 4
351; RV32I-WITHFP-NEXT: lw a1, 0(a1)
352; RV32I-WITHFP-NEXT: lw s0, 8(sp)
353; RV32I-WITHFP-NEXT: lw ra, 12(sp)
354; RV32I-WITHFP-NEXT: addi sp, sp, 48
355; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]356 %va = alloca i8*, align 4
357 %1 = bitcast i8** %va to i8*
358 call void @llvm.va_start(i8* %1)
359 %2 = bitcast i8** %va to i32*
360 %argp.cur = load i32, i32* %2, align 4
361 %3 = add i32 %argp.cur, 7
362 %4 = and i32 %3, -8
363 %argp.cur.aligned = inttoptr i32 %3 to i8*
364 %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 8
365 store i8* %argp.next, i8** %va, align 4
366 %5 = inttoptr i32 %4 to double*
367 %6 = load double, double* %5, align 8
368 call void @llvm.va_end(i8* %1)
369 ret double %6
370}
371
372define double @va2_va_arg(i8 *%fmt, ...) nounwind {
373; RV32I-LABEL: va2_va_arg:
374; RV32I: # %bb.0:
375; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]376; RV32I-NEXT: sw a7, 44(sp)
377; RV32I-NEXT: sw a6, 40(sp)
378; RV32I-NEXT: sw a5, 36(sp)
379; RV32I-NEXT: sw a4, 32(sp)
380; RV32I-NEXT: sw a3, 28(sp)
381; RV32I-NEXT: sw a2, 24(sp)
382; RV32I-NEXT: sw a1, 20(sp)
383; RV32I-NEXT: addi a0, sp, 27
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]384; RV32I-NEXT: andi a0, a0, -8
385; RV32I-NEXT: ori a1, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]386; RV32I-NEXT: sw a1, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]387; RV32I-NEXT: lw a0, 0(a0)
388; RV32I-NEXT: addi a2, a1, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]389; RV32I-NEXT: sw a2, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]390; RV32I-NEXT: lw a1, 0(a1)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]391; RV32I-NEXT: addi sp, sp, 48
392; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]393; RV32I-FPELIM-LABEL: va2_va_arg:
394; RV32I-FPELIM: # %bb.0:
395; RV32I-FPELIM-NEXT: addi sp, sp, -48
396; RV32I-FPELIM-NEXT: sw a7, 44(sp)
397; RV32I-FPELIM-NEXT: sw a6, 40(sp)
398; RV32I-FPELIM-NEXT: sw a5, 36(sp)
399; RV32I-FPELIM-NEXT: sw a4, 32(sp)
400; RV32I-FPELIM-NEXT: sw a3, 28(sp)
401; RV32I-FPELIM-NEXT: sw a2, 24(sp)
402; RV32I-FPELIM-NEXT: sw a1, 20(sp)
403; RV32I-FPELIM-NEXT: addi a0, sp, 27
404; RV32I-FPELIM-NEXT: andi a0, a0, -8
405; RV32I-FPELIM-NEXT: ori a1, a0, 4
406; RV32I-FPELIM-NEXT: sw a1, 12(sp)
407; RV32I-FPELIM-NEXT: lw a0, 0(a0)
408; RV32I-FPELIM-NEXT: addi a2, a1, 4
409; RV32I-FPELIM-NEXT: sw a2, 12(sp)
410; RV32I-FPELIM-NEXT: lw a1, 0(a1)
411; RV32I-FPELIM-NEXT: addi sp, sp, 48
412; RV32I-FPELIM-NEXT: ret
413;
414; RV32I-WITHFP-LABEL: va2_va_arg:
415; RV32I-WITHFP: # %bb.0:
416; RV32I-WITHFP-NEXT: addi sp, sp, -48
417; RV32I-WITHFP-NEXT: sw ra, 12(sp)
418; RV32I-WITHFP-NEXT: sw s0, 8(sp)
419; RV32I-WITHFP-NEXT: addi s0, sp, 16
420; RV32I-WITHFP-NEXT: sw a7, 28(s0)
421; RV32I-WITHFP-NEXT: sw a6, 24(s0)
422; RV32I-WITHFP-NEXT: sw a5, 20(s0)
423; RV32I-WITHFP-NEXT: sw a4, 16(s0)
424; RV32I-WITHFP-NEXT: sw a3, 12(s0)
425; RV32I-WITHFP-NEXT: sw a2, 8(s0)
426; RV32I-WITHFP-NEXT: sw a1, 4(s0)
427; RV32I-WITHFP-NEXT: addi a0, s0, 11
428; RV32I-WITHFP-NEXT: andi a0, a0, -8
429; RV32I-WITHFP-NEXT: ori a1, a0, 4
430; RV32I-WITHFP-NEXT: sw a1, -12(s0)
431; RV32I-WITHFP-NEXT: lw a0, 0(a0)
432; RV32I-WITHFP-NEXT: addi a2, a1, 4
433; RV32I-WITHFP-NEXT: sw a2, -12(s0)
434; RV32I-WITHFP-NEXT: lw a1, 0(a1)
435; RV32I-WITHFP-NEXT: lw s0, 8(sp)
436; RV32I-WITHFP-NEXT: lw ra, 12(sp)
437; RV32I-WITHFP-NEXT: addi sp, sp, 48
438; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]439 %va = alloca i8*, align 4
440 %1 = bitcast i8** %va to i8*
441 call void @llvm.va_start(i8* %1)
442 %2 = va_arg i8** %va, double
443 call void @llvm.va_end(i8* %1)
444 ret double %2
445}
446
447define void @va2_caller() nounwind {
448; RV32I-LABEL: va2_caller:
449; RV32I: # %bb.0:
450; RV32I-NEXT: addi sp, sp, -16
451; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]452; RV32I-NEXT: lui a0, 261888
453; RV32I-NEXT: mv a3, a0
454; RV32I-NEXT: lui a0, %hi(va2)
455; RV32I-NEXT: addi a0, a0, %lo(va2)
456; RV32I-NEXT: mv a2, zero
457; RV32I-NEXT: jalr a0
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]458; RV32I-NEXT: lw ra, 12(sp)
459; RV32I-NEXT: addi sp, sp, 16
460; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]461; RV32I-FPELIM-LABEL: va2_caller:
462; RV32I-FPELIM: # %bb.0:
463; RV32I-FPELIM-NEXT: addi sp, sp, -16
464; RV32I-FPELIM-NEXT: sw ra, 12(sp)
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]465; RV32I-FPELIM-NEXT: lui a3, 261888
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]466; RV32I-FPELIM-NEXT: mv a2, zero
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]467; RV32I-FPELIM-NEXT: call va2
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]468; RV32I-FPELIM-NEXT: lw ra, 12(sp)
469; RV32I-FPELIM-NEXT: addi sp, sp, 16
470; RV32I-FPELIM-NEXT: ret
471;
472; RV32I-WITHFP-LABEL: va2_caller:
473; RV32I-WITHFP: # %bb.0:
474; RV32I-WITHFP-NEXT: addi sp, sp, -16
475; RV32I-WITHFP-NEXT: sw ra, 12(sp)
476; RV32I-WITHFP-NEXT: sw s0, 8(sp)
477; RV32I-WITHFP-NEXT: addi s0, sp, 16
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]478; RV32I-WITHFP-NEXT: lui a3, 261888
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]479; RV32I-WITHFP-NEXT: mv a2, zero
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]480; RV32I-WITHFP-NEXT: call va2
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]481; RV32I-WITHFP-NEXT: lw s0, 8(sp)
482; RV32I-WITHFP-NEXT: lw ra, 12(sp)
483; RV32I-WITHFP-NEXT: addi sp, sp, 16
484; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]485 %1 = call double (i8*, ...) @va2(i8* undef, double 1.000000e+00)
486 ret void
487}
488
489; Ensure a named double argument is passed in a1 and a2, while the vararg
490; double is passed in a4 and a5 (rather than a3 and a4)
491
492define double @va3(i32 %a, double %b, ...) nounwind {
493; RV32I-LABEL: va3:
494; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]495; RV32I-NEXT: addi sp, sp, -32
496; RV32I-NEXT: sw ra, 4(sp)
497; RV32I-NEXT: sw a7, 28(sp)
498; RV32I-NEXT: sw a6, 24(sp)
499; RV32I-NEXT: sw a5, 20(sp)
500; RV32I-NEXT: sw a4, 16(sp)
501; RV32I-NEXT: sw a3, 12(sp)
502; RV32I-NEXT: addi a0, sp, 27
503; RV32I-NEXT: sw a0, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]504; RV32I-NEXT: lui a0, %hi(__adddf3)
505; RV32I-NEXT: addi a5, a0, %lo(__adddf3)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]506; RV32I-NEXT: addi a0, sp, 19
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]507; RV32I-NEXT: andi a0, a0, -8
508; RV32I-NEXT: lw a4, 0(a0)
509; RV32I-NEXT: ori a0, a0, 4
510; RV32I-NEXT: lw a3, 0(a0)
511; RV32I-NEXT: mv a0, a1
512; RV32I-NEXT: mv a1, a2
513; RV32I-NEXT: mv a2, a4
514; RV32I-NEXT: jalr a5
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]515; RV32I-NEXT: lw ra, 4(sp)
516; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]517; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]518; RV32I-FPELIM-LABEL: va3:
519; RV32I-FPELIM: # %bb.0:
520; RV32I-FPELIM-NEXT: addi sp, sp, -32
521; RV32I-FPELIM-NEXT: sw ra, 4(sp)
522; RV32I-FPELIM-NEXT: sw a7, 28(sp)
523; RV32I-FPELIM-NEXT: sw a6, 24(sp)
524; RV32I-FPELIM-NEXT: sw a5, 20(sp)
525; RV32I-FPELIM-NEXT: sw a4, 16(sp)
526; RV32I-FPELIM-NEXT: sw a3, 12(sp)
527; RV32I-FPELIM-NEXT: addi a0, sp, 27
528; RV32I-FPELIM-NEXT: sw a0, 0(sp)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]529; RV32I-FPELIM-NEXT: addi a0, sp, 19
530; RV32I-FPELIM-NEXT: andi a0, a0, -8
531; RV32I-FPELIM-NEXT: lw a4, 0(a0)
532; RV32I-FPELIM-NEXT: ori a0, a0, 4
533; RV32I-FPELIM-NEXT: lw a3, 0(a0)
534; RV32I-FPELIM-NEXT: mv a0, a1
535; RV32I-FPELIM-NEXT: mv a1, a2
536; RV32I-FPELIM-NEXT: mv a2, a4
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]537; RV32I-FPELIM-NEXT: call __adddf3
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]538; RV32I-FPELIM-NEXT: lw ra, 4(sp)
539; RV32I-FPELIM-NEXT: addi sp, sp, 32
540; RV32I-FPELIM-NEXT: ret
541;
542; RV32I-WITHFP-LABEL: va3:
543; RV32I-WITHFP: # %bb.0:
544; RV32I-WITHFP-NEXT: addi sp, sp, -48
545; RV32I-WITHFP-NEXT: sw ra, 20(sp)
546; RV32I-WITHFP-NEXT: sw s0, 16(sp)
547; RV32I-WITHFP-NEXT: addi s0, sp, 24
548; RV32I-WITHFP-NEXT: sw a7, 20(s0)
549; RV32I-WITHFP-NEXT: sw a6, 16(s0)
550; RV32I-WITHFP-NEXT: sw a5, 12(s0)
551; RV32I-WITHFP-NEXT: sw a4, 8(s0)
552; RV32I-WITHFP-NEXT: sw a3, 4(s0)
553; RV32I-WITHFP-NEXT: addi a0, s0, 19
554; RV32I-WITHFP-NEXT: sw a0, -12(s0)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]555; RV32I-WITHFP-NEXT: addi a0, s0, 11
556; RV32I-WITHFP-NEXT: andi a0, a0, -8
557; RV32I-WITHFP-NEXT: lw a4, 0(a0)
558; RV32I-WITHFP-NEXT: ori a0, a0, 4
559; RV32I-WITHFP-NEXT: lw a3, 0(a0)
560; RV32I-WITHFP-NEXT: mv a0, a1
561; RV32I-WITHFP-NEXT: mv a1, a2
562; RV32I-WITHFP-NEXT: mv a2, a4
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]563; RV32I-WITHFP-NEXT: call __adddf3
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]564; RV32I-WITHFP-NEXT: lw s0, 16(sp)
565; RV32I-WITHFP-NEXT: lw ra, 20(sp)
566; RV32I-WITHFP-NEXT: addi sp, sp, 48
567; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]568 %va = alloca i8*, align 4
569 %1 = bitcast i8** %va to i8*
570 call void @llvm.va_start(i8* %1)
571 %2 = bitcast i8** %va to i32*
572 %argp.cur = load i32, i32* %2, align 4
573 %3 = add i32 %argp.cur, 7
574 %4 = and i32 %3, -8
575 %argp.cur.aligned = inttoptr i32 %3 to i8*
576 %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 8
577 store i8* %argp.next, i8** %va, align 4
578 %5 = inttoptr i32 %4 to double*
579 %6 = load double, double* %5, align 8
580 call void @llvm.va_end(i8* %1)
581 %7 = fadd double %b, %6
582 ret double %7
583}
584
585define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
586; RV32I-LABEL: va3_va_arg:
587; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]588; RV32I-NEXT: addi sp, sp, -32
589; RV32I-NEXT: sw ra, 4(sp)
590; RV32I-NEXT: sw a7, 28(sp)
591; RV32I-NEXT: sw a6, 24(sp)
592; RV32I-NEXT: sw a5, 20(sp)
593; RV32I-NEXT: sw a4, 16(sp)
594; RV32I-NEXT: sw a3, 12(sp)
595; RV32I-NEXT: addi a0, sp, 19
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]596; RV32I-NEXT: andi a0, a0, -8
597; RV32I-NEXT: ori a3, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]598; RV32I-NEXT: sw a3, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]599; RV32I-NEXT: lw a4, 0(a0)
600; RV32I-NEXT: addi a0, a3, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]601; RV32I-NEXT: sw a0, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]602; RV32I-NEXT: lui a0, %hi(__adddf3)
603; RV32I-NEXT: addi a5, a0, %lo(__adddf3)
604; RV32I-NEXT: lw a3, 0(a3)
605; RV32I-NEXT: mv a0, a1
606; RV32I-NEXT: mv a1, a2
607; RV32I-NEXT: mv a2, a4
608; RV32I-NEXT: jalr a5
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]609; RV32I-NEXT: lw ra, 4(sp)
610; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]611; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]612; RV32I-FPELIM-LABEL: va3_va_arg:
613; RV32I-FPELIM: # %bb.0:
614; RV32I-FPELIM-NEXT: addi sp, sp, -32
615; RV32I-FPELIM-NEXT: sw ra, 4(sp)
616; RV32I-FPELIM-NEXT: sw a7, 28(sp)
617; RV32I-FPELIM-NEXT: sw a6, 24(sp)
618; RV32I-FPELIM-NEXT: sw a5, 20(sp)
619; RV32I-FPELIM-NEXT: sw a4, 16(sp)
620; RV32I-FPELIM-NEXT: sw a3, 12(sp)
621; RV32I-FPELIM-NEXT: addi a0, sp, 19
622; RV32I-FPELIM-NEXT: andi a0, a0, -8
623; RV32I-FPELIM-NEXT: ori a3, a0, 4
624; RV32I-FPELIM-NEXT: sw a3, 0(sp)
625; RV32I-FPELIM-NEXT: lw a4, 0(a0)
626; RV32I-FPELIM-NEXT: addi a0, a3, 4
627; RV32I-FPELIM-NEXT: sw a0, 0(sp)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]628; RV32I-FPELIM-NEXT: lw a3, 0(a3)
629; RV32I-FPELIM-NEXT: mv a0, a1
630; RV32I-FPELIM-NEXT: mv a1, a2
631; RV32I-FPELIM-NEXT: mv a2, a4
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]632; RV32I-FPELIM-NEXT: call __adddf3
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]633; RV32I-FPELIM-NEXT: lw ra, 4(sp)
634; RV32I-FPELIM-NEXT: addi sp, sp, 32
635; RV32I-FPELIM-NEXT: ret
636;
637; RV32I-WITHFP-LABEL: va3_va_arg:
638; RV32I-WITHFP: # %bb.0:
639; RV32I-WITHFP-NEXT: addi sp, sp, -48
640; RV32I-WITHFP-NEXT: sw ra, 20(sp)
641; RV32I-WITHFP-NEXT: sw s0, 16(sp)
642; RV32I-WITHFP-NEXT: addi s0, sp, 24
643; RV32I-WITHFP-NEXT: sw a7, 20(s0)
644; RV32I-WITHFP-NEXT: sw a6, 16(s0)
645; RV32I-WITHFP-NEXT: sw a5, 12(s0)
646; RV32I-WITHFP-NEXT: sw a4, 8(s0)
647; RV32I-WITHFP-NEXT: sw a3, 4(s0)
648; RV32I-WITHFP-NEXT: addi a0, s0, 11
649; RV32I-WITHFP-NEXT: andi a0, a0, -8
650; RV32I-WITHFP-NEXT: ori a3, a0, 4
651; RV32I-WITHFP-NEXT: sw a3, -12(s0)
652; RV32I-WITHFP-NEXT: lw a4, 0(a0)
653; RV32I-WITHFP-NEXT: addi a0, a3, 4
654; RV32I-WITHFP-NEXT: sw a0, -12(s0)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]655; RV32I-WITHFP-NEXT: lw a3, 0(a3)
656; RV32I-WITHFP-NEXT: mv a0, a1
657; RV32I-WITHFP-NEXT: mv a1, a2
658; RV32I-WITHFP-NEXT: mv a2, a4
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]659; RV32I-WITHFP-NEXT: call __adddf3
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]660; RV32I-WITHFP-NEXT: lw s0, 16(sp)
661; RV32I-WITHFP-NEXT: lw ra, 20(sp)
662; RV32I-WITHFP-NEXT: addi sp, sp, 48
663; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]664 %va = alloca i8*, align 4
665 %1 = bitcast i8** %va to i8*
666 call void @llvm.va_start(i8* %1)
667 %2 = va_arg i8** %va, double
668 call void @llvm.va_end(i8* %1)
669 %3 = fadd double %b, %2
670 ret double %3
671}
672
673define void @va3_caller() nounwind {
674; RV32I-LABEL: va3_caller:
675; RV32I: # %bb.0:
676; RV32I-NEXT: addi sp, sp, -16
677; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]678; RV32I-NEXT: lui a0, 261888
679; RV32I-NEXT: mv a2, a0
680; RV32I-NEXT: lui a0, 262144
681; RV32I-NEXT: mv a5, a0
682; RV32I-NEXT: lui a0, %hi(va3)
683; RV32I-NEXT: addi a3, a0, %lo(va3)
684; RV32I-NEXT: addi a0, zero, 2
685; RV32I-NEXT: mv a1, zero
686; RV32I-NEXT: mv a4, zero
687; RV32I-NEXT: jalr a3
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]688; RV32I-NEXT: lw ra, 12(sp)
689; RV32I-NEXT: addi sp, sp, 16
690; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]691; RV32I-FPELIM-LABEL: va3_caller:
692; RV32I-FPELIM: # %bb.0:
693; RV32I-FPELIM-NEXT: addi sp, sp, -16
694; RV32I-FPELIM-NEXT: sw ra, 12(sp)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]695; RV32I-FPELIM-NEXT: addi a0, zero, 2
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]696; RV32I-FPELIM-NEXT: lui a2, 261888
697; RV32I-FPELIM-NEXT: lui a5, 262144
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]698; RV32I-FPELIM-NEXT: mv a1, zero
699; RV32I-FPELIM-NEXT: mv a4, zero
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]700; RV32I-FPELIM-NEXT: call va3
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]701; RV32I-FPELIM-NEXT: lw ra, 12(sp)
702; RV32I-FPELIM-NEXT: addi sp, sp, 16
703; RV32I-FPELIM-NEXT: ret
704;
705; RV32I-WITHFP-LABEL: va3_caller:
706; RV32I-WITHFP: # %bb.0:
707; RV32I-WITHFP-NEXT: addi sp, sp, -16
708; RV32I-WITHFP-NEXT: sw ra, 12(sp)
709; RV32I-WITHFP-NEXT: sw s0, 8(sp)
710; RV32I-WITHFP-NEXT: addi s0, sp, 16
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]711; RV32I-WITHFP-NEXT: addi a0, zero, 2
Alex Bradbury3ff20222018-04-18 20:34:23 +0000[diff] [blame]712; RV32I-WITHFP-NEXT: lui a2, 261888
713; RV32I-WITHFP-NEXT: lui a5, 262144
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]714; RV32I-WITHFP-NEXT: mv a1, zero
715; RV32I-WITHFP-NEXT: mv a4, zero
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]716; RV32I-WITHFP-NEXT: call va3
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]717; RV32I-WITHFP-NEXT: lw s0, 8(sp)
718; RV32I-WITHFP-NEXT: lw ra, 12(sp)
719; RV32I-WITHFP-NEXT: addi sp, sp, 16
720; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]721 %1 = call double (i32, double, ...) @va3(i32 2, double 1.000000e+00, double 2.000000e+00)
722 ret void
723}
724
725declare void @llvm.va_copy(i8*, i8*)
726
727define i32 @va4_va_copy(i32 %argno, ...) nounwind {
728; RV32I-LABEL: va4_va_copy:
729; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]730; RV32I-NEXT: addi sp, sp, -48
731; RV32I-NEXT: sw ra, 12(sp)
732; RV32I-NEXT: sw s1, 8(sp)
733; RV32I-NEXT: sw a1, 20(sp)
734; RV32I-NEXT: sw a7, 44(sp)
735; RV32I-NEXT: sw a6, 40(sp)
736; RV32I-NEXT: sw a5, 36(sp)
737; RV32I-NEXT: sw a4, 32(sp)
738; RV32I-NEXT: sw a3, 28(sp)
739; RV32I-NEXT: sw a2, 24(sp)
740; RV32I-NEXT: addi a0, sp, 24
741; RV32I-NEXT: sw a0, 4(sp)
742; RV32I-NEXT: sw a0, 0(sp)
743; RV32I-NEXT: lw s1, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]744; RV32I-NEXT: lui a1, %hi(notdead)
745; RV32I-NEXT: addi a1, a1, %lo(notdead)
746; RV32I-NEXT: jalr a1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]747; RV32I-NEXT: lw a0, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]748; RV32I-NEXT: addi a0, a0, 3
749; RV32I-NEXT: andi a0, a0, -4
750; RV32I-NEXT: addi a1, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]751; RV32I-NEXT: sw a1, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]752; RV32I-NEXT: lw a1, 0(a0)
753; RV32I-NEXT: addi a0, a0, 7
754; RV32I-NEXT: andi a0, a0, -4
755; RV32I-NEXT: addi a2, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]756; RV32I-NEXT: sw a2, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]757; RV32I-NEXT: lw a2, 0(a0)
758; RV32I-NEXT: addi a0, a0, 7
759; RV32I-NEXT: andi a0, a0, -4
760; RV32I-NEXT: addi a3, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]761; RV32I-NEXT: sw a3, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]762; RV32I-NEXT: add a1, a1, s1
763; RV32I-NEXT: add a1, a1, a2
764; RV32I-NEXT: lw a0, 0(a0)
765; RV32I-NEXT: add a0, a1, a0
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]766; RV32I-NEXT: lw s1, 8(sp)
767; RV32I-NEXT: lw ra, 12(sp)
768; RV32I-NEXT: addi sp, sp, 48
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]769; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]770; RV32I-FPELIM-LABEL: va4_va_copy:
771; RV32I-FPELIM: # %bb.0:
772; RV32I-FPELIM-NEXT: addi sp, sp, -48
773; RV32I-FPELIM-NEXT: sw ra, 12(sp)
774; RV32I-FPELIM-NEXT: sw s1, 8(sp)
775; RV32I-FPELIM-NEXT: sw a1, 20(sp)
776; RV32I-FPELIM-NEXT: sw a7, 44(sp)
777; RV32I-FPELIM-NEXT: sw a6, 40(sp)
778; RV32I-FPELIM-NEXT: sw a5, 36(sp)
779; RV32I-FPELIM-NEXT: sw a4, 32(sp)
780; RV32I-FPELIM-NEXT: sw a3, 28(sp)
781; RV32I-FPELIM-NEXT: sw a2, 24(sp)
782; RV32I-FPELIM-NEXT: addi a0, sp, 24
783; RV32I-FPELIM-NEXT: sw a0, 4(sp)
784; RV32I-FPELIM-NEXT: sw a0, 0(sp)
785; RV32I-FPELIM-NEXT: lw s1, 20(sp)
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]786; RV32I-FPELIM-NEXT: call notdead
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]787; RV32I-FPELIM-NEXT: lw a0, 4(sp)
788; RV32I-FPELIM-NEXT: addi a0, a0, 3
789; RV32I-FPELIM-NEXT: andi a0, a0, -4
790; RV32I-FPELIM-NEXT: addi a1, a0, 4
791; RV32I-FPELIM-NEXT: sw a1, 4(sp)
792; RV32I-FPELIM-NEXT: lw a1, 0(a0)
793; RV32I-FPELIM-NEXT: addi a0, a0, 7
794; RV32I-FPELIM-NEXT: andi a0, a0, -4
795; RV32I-FPELIM-NEXT: addi a2, a0, 4
796; RV32I-FPELIM-NEXT: sw a2, 4(sp)
797; RV32I-FPELIM-NEXT: lw a2, 0(a0)
798; RV32I-FPELIM-NEXT: addi a0, a0, 7
799; RV32I-FPELIM-NEXT: andi a0, a0, -4
800; RV32I-FPELIM-NEXT: addi a3, a0, 4
801; RV32I-FPELIM-NEXT: sw a3, 4(sp)
802; RV32I-FPELIM-NEXT: add a1, a1, s1
803; RV32I-FPELIM-NEXT: add a1, a1, a2
804; RV32I-FPELIM-NEXT: lw a0, 0(a0)
805; RV32I-FPELIM-NEXT: add a0, a1, a0
806; RV32I-FPELIM-NEXT: lw s1, 8(sp)
807; RV32I-FPELIM-NEXT: lw ra, 12(sp)
808; RV32I-FPELIM-NEXT: addi sp, sp, 48
809; RV32I-FPELIM-NEXT: ret
810;
811; RV32I-WITHFP-LABEL: va4_va_copy:
812; RV32I-WITHFP: # %bb.0:
813; RV32I-WITHFP-NEXT: addi sp, sp, -64
814; RV32I-WITHFP-NEXT: sw ra, 28(sp)
815; RV32I-WITHFP-NEXT: sw s0, 24(sp)
816; RV32I-WITHFP-NEXT: sw s1, 20(sp)
817; RV32I-WITHFP-NEXT: addi s0, sp, 32
818; RV32I-WITHFP-NEXT: sw a1, 4(s0)
819; RV32I-WITHFP-NEXT: sw a7, 28(s0)
820; RV32I-WITHFP-NEXT: sw a6, 24(s0)
821; RV32I-WITHFP-NEXT: sw a5, 20(s0)
822; RV32I-WITHFP-NEXT: sw a4, 16(s0)
823; RV32I-WITHFP-NEXT: sw a3, 12(s0)
824; RV32I-WITHFP-NEXT: sw a2, 8(s0)
825; RV32I-WITHFP-NEXT: addi a0, s0, 8
826; RV32I-WITHFP-NEXT: sw a0, -16(s0)
827; RV32I-WITHFP-NEXT: sw a0, -20(s0)
828; RV32I-WITHFP-NEXT: lw s1, 4(s0)
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]829; RV32I-WITHFP-NEXT: call notdead
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]830; RV32I-WITHFP-NEXT: lw a0, -16(s0)
831; RV32I-WITHFP-NEXT: addi a0, a0, 3
832; RV32I-WITHFP-NEXT: andi a0, a0, -4
833; RV32I-WITHFP-NEXT: addi a1, a0, 4
834; RV32I-WITHFP-NEXT: sw a1, -16(s0)
835; RV32I-WITHFP-NEXT: lw a1, 0(a0)
836; RV32I-WITHFP-NEXT: addi a0, a0, 7
837; RV32I-WITHFP-NEXT: andi a0, a0, -4
838; RV32I-WITHFP-NEXT: addi a2, a0, 4
839; RV32I-WITHFP-NEXT: sw a2, -16(s0)
840; RV32I-WITHFP-NEXT: lw a2, 0(a0)
841; RV32I-WITHFP-NEXT: addi a0, a0, 7
842; RV32I-WITHFP-NEXT: andi a0, a0, -4
843; RV32I-WITHFP-NEXT: addi a3, a0, 4
844; RV32I-WITHFP-NEXT: sw a3, -16(s0)
845; RV32I-WITHFP-NEXT: add a1, a1, s1
846; RV32I-WITHFP-NEXT: add a1, a1, a2
847; RV32I-WITHFP-NEXT: lw a0, 0(a0)
848; RV32I-WITHFP-NEXT: add a0, a1, a0
849; RV32I-WITHFP-NEXT: lw s1, 20(sp)
850; RV32I-WITHFP-NEXT: lw s0, 24(sp)
851; RV32I-WITHFP-NEXT: lw ra, 28(sp)
852; RV32I-WITHFP-NEXT: addi sp, sp, 64
853; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]854 %vargs = alloca i8*, align 4
855 %wargs = alloca i8*, align 4
856 %1 = bitcast i8** %vargs to i8*
857 %2 = bitcast i8** %wargs to i8*
858 call void @llvm.va_start(i8* %1)
859 %3 = va_arg i8** %vargs, i32
860 call void @llvm.va_copy(i8* %2, i8* %1)
861 %4 = load i8*, i8** %wargs, align 4
862 call void @notdead(i8* %4)
863 %5 = va_arg i8** %vargs, i32
864 %6 = va_arg i8** %vargs, i32
865 %7 = va_arg i8** %vargs, i32
866 call void @llvm.va_end(i8* %1)
867 call void @llvm.va_end(i8* %2)
868 %add1 = add i32 %5, %3
869 %add2 = add i32 %add1, %6
870 %add3 = add i32 %add2, %7
871 ret i32 %add3
872}
873
874; Check 2x*xlen values are aligned appropriately when passed on the stack in a vararg call
875
876define i32 @va5_aligned_stack_callee(i32 %a, ...) nounwind {
877; RV32I-LABEL: va5_aligned_stack_callee:
878; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]879; RV32I-NEXT: addi sp, sp, -32
880; RV32I-NEXT: sw a7, 28(sp)
881; RV32I-NEXT: sw a6, 24(sp)
882; RV32I-NEXT: sw a5, 20(sp)
883; RV32I-NEXT: sw a4, 16(sp)
884; RV32I-NEXT: sw a3, 12(sp)
885; RV32I-NEXT: sw a2, 8(sp)
886; RV32I-NEXT: sw a1, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]887; RV32I-NEXT: addi a0, zero, 1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]888; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]889; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]890; RV32I-FPELIM-LABEL: va5_aligned_stack_callee:
891; RV32I-FPELIM: # %bb.0:
892; RV32I-FPELIM-NEXT: addi sp, sp, -32
893; RV32I-FPELIM-NEXT: sw a7, 28(sp)
894; RV32I-FPELIM-NEXT: sw a6, 24(sp)
895; RV32I-FPELIM-NEXT: sw a5, 20(sp)
896; RV32I-FPELIM-NEXT: sw a4, 16(sp)
897; RV32I-FPELIM-NEXT: sw a3, 12(sp)
898; RV32I-FPELIM-NEXT: sw a2, 8(sp)
899; RV32I-FPELIM-NEXT: sw a1, 4(sp)
900; RV32I-FPELIM-NEXT: addi a0, zero, 1
901; RV32I-FPELIM-NEXT: addi sp, sp, 32
902; RV32I-FPELIM-NEXT: ret
903;
904; RV32I-WITHFP-LABEL: va5_aligned_stack_callee:
905; RV32I-WITHFP: # %bb.0:
906; RV32I-WITHFP-NEXT: addi sp, sp, -48
907; RV32I-WITHFP-NEXT: sw ra, 12(sp)
908; RV32I-WITHFP-NEXT: sw s0, 8(sp)
909; RV32I-WITHFP-NEXT: addi s0, sp, 16
910; RV32I-WITHFP-NEXT: sw a7, 28(s0)
911; RV32I-WITHFP-NEXT: sw a6, 24(s0)
912; RV32I-WITHFP-NEXT: sw a5, 20(s0)
913; RV32I-WITHFP-NEXT: sw a4, 16(s0)
914; RV32I-WITHFP-NEXT: sw a3, 12(s0)
915; RV32I-WITHFP-NEXT: sw a2, 8(s0)
916; RV32I-WITHFP-NEXT: sw a1, 4(s0)
917; RV32I-WITHFP-NEXT: addi a0, zero, 1
918; RV32I-WITHFP-NEXT: lw s0, 8(sp)
919; RV32I-WITHFP-NEXT: lw ra, 12(sp)
920; RV32I-WITHFP-NEXT: addi sp, sp, 48
921; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]922 ret i32 1
923}
924
925define void @va5_aligned_stack_caller() nounwind {
926; The double should be 8-byte aligned on the stack, but the two-element array
927; should only be 4-byte aligned
928; RV32I-LABEL: va5_aligned_stack_caller:
929; RV32I: # %bb.0:
930; RV32I-NEXT: addi sp, sp, -64
931; RV32I-NEXT: sw ra, 60(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]932; RV32I-NEXT: addi a0, zero, 17
933; RV32I-NEXT: sw a0, 24(sp)
934; RV32I-NEXT: addi a0, zero, 16
935; RV32I-NEXT: sw a0, 20(sp)
936; RV32I-NEXT: addi a0, zero, 15
937; RV32I-NEXT: sw a0, 16(sp)
938; RV32I-NEXT: lui a0, 262236
939; RV32I-NEXT: addi a0, a0, 655
940; RV32I-NEXT: sw a0, 12(sp)
941; RV32I-NEXT: lui a0, 377487
942; RV32I-NEXT: addi a0, a0, 1475
943; RV32I-NEXT: sw a0, 8(sp)
944; RV32I-NEXT: addi a0, zero, 14
945; RV32I-NEXT: sw a0, 0(sp)
946; RV32I-NEXT: lui a0, 262153
947; RV32I-NEXT: addi a0, a0, 491
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]948; RV32I-NEXT: sw a0, 44(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]949; RV32I-NEXT: lui a0, 545260
950; RV32I-NEXT: addi a0, a0, -1967
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]951; RV32I-NEXT: sw a0, 40(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]952; RV32I-NEXT: lui a0, 964690
953; RV32I-NEXT: addi a0, a0, -328
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]954; RV32I-NEXT: sw a0, 36(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]955; RV32I-NEXT: lui a0, 335544
956; RV32I-NEXT: addi a0, a0, 1311
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]957; RV32I-NEXT: sw a0, 32(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]958; RV32I-NEXT: lui a0, 688509
959; RV32I-NEXT: addi a6, a0, -2048
960; RV32I-NEXT: lui a0, %hi(va5_aligned_stack_callee)
961; RV32I-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
962; RV32I-NEXT: addi a0, zero, 1
963; RV32I-NEXT: addi a1, zero, 11
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]964; RV32I-NEXT: addi a2, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]965; RV32I-NEXT: addi a3, zero, 12
966; RV32I-NEXT: addi a4, zero, 13
967; RV32I-NEXT: addi a7, zero, 4
968; RV32I-NEXT: jalr a5
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]969; RV32I-NEXT: lw ra, 60(sp)
970; RV32I-NEXT: addi sp, sp, 64
971; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]972; RV32I-FPELIM-LABEL: va5_aligned_stack_caller:
973; RV32I-FPELIM: # %bb.0:
974; RV32I-FPELIM-NEXT: addi sp, sp, -64
975; RV32I-FPELIM-NEXT: sw ra, 60(sp)
976; RV32I-FPELIM-NEXT: addi a0, zero, 17
977; RV32I-FPELIM-NEXT: sw a0, 24(sp)
978; RV32I-FPELIM-NEXT: addi a0, zero, 16
979; RV32I-FPELIM-NEXT: sw a0, 20(sp)
980; RV32I-FPELIM-NEXT: addi a0, zero, 15
981; RV32I-FPELIM-NEXT: sw a0, 16(sp)
982; RV32I-FPELIM-NEXT: lui a0, 262236
983; RV32I-FPELIM-NEXT: addi a0, a0, 655
984; RV32I-FPELIM-NEXT: sw a0, 12(sp)
985; RV32I-FPELIM-NEXT: lui a0, 377487
986; RV32I-FPELIM-NEXT: addi a0, a0, 1475
987; RV32I-FPELIM-NEXT: sw a0, 8(sp)
988; RV32I-FPELIM-NEXT: addi a0, zero, 14
989; RV32I-FPELIM-NEXT: sw a0, 0(sp)
990; RV32I-FPELIM-NEXT: lui a0, 262153
991; RV32I-FPELIM-NEXT: addi a0, a0, 491
992; RV32I-FPELIM-NEXT: sw a0, 44(sp)
993; RV32I-FPELIM-NEXT: lui a0, 545260
994; RV32I-FPELIM-NEXT: addi a0, a0, -1967
995; RV32I-FPELIM-NEXT: sw a0, 40(sp)
996; RV32I-FPELIM-NEXT: lui a0, 964690
997; RV32I-FPELIM-NEXT: addi a0, a0, -328
998; RV32I-FPELIM-NEXT: sw a0, 36(sp)
999; RV32I-FPELIM-NEXT: lui a0, 335544
1000; RV32I-FPELIM-NEXT: addi a0, a0, 1311
1001; RV32I-FPELIM-NEXT: sw a0, 32(sp)
Alex Bradbury099c7202018-04-18 19:02:31 +0000[diff] [blame]1002; RV32I-FPELIM-NEXT: lui a0, 688509
1003; RV32I-FPELIM-NEXT: addi a6, a0, -2048
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1004; RV32I-FPELIM-NEXT: addi a0, zero, 1
1005; RV32I-FPELIM-NEXT: addi a1, zero, 11
1006; RV32I-FPELIM-NEXT: addi a2, sp, 32
1007; RV32I-FPELIM-NEXT: addi a3, zero, 12
1008; RV32I-FPELIM-NEXT: addi a4, zero, 13
1009; RV32I-FPELIM-NEXT: addi a7, zero, 4
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]1010; RV32I-FPELIM-NEXT: call va5_aligned_stack_callee
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1011; RV32I-FPELIM-NEXT: lw ra, 60(sp)
1012; RV32I-FPELIM-NEXT: addi sp, sp, 64
1013; RV32I-FPELIM-NEXT: ret
1014;
1015; RV32I-WITHFP-LABEL: va5_aligned_stack_caller:
1016; RV32I-WITHFP: # %bb.0:
1017; RV32I-WITHFP-NEXT: addi sp, sp, -64
1018; RV32I-WITHFP-NEXT: sw ra, 60(sp)
1019; RV32I-WITHFP-NEXT: sw s0, 56(sp)
1020; RV32I-WITHFP-NEXT: addi s0, sp, 64
1021; RV32I-WITHFP-NEXT: addi a0, zero, 17
1022; RV32I-WITHFP-NEXT: sw a0, 24(sp)
1023; RV32I-WITHFP-NEXT: addi a0, zero, 16
1024; RV32I-WITHFP-NEXT: sw a0, 20(sp)
1025; RV32I-WITHFP-NEXT: addi a0, zero, 15
1026; RV32I-WITHFP-NEXT: sw a0, 16(sp)
1027; RV32I-WITHFP-NEXT: lui a0, 262236
1028; RV32I-WITHFP-NEXT: addi a0, a0, 655
1029; RV32I-WITHFP-NEXT: sw a0, 12(sp)
1030; RV32I-WITHFP-NEXT: lui a0, 377487
1031; RV32I-WITHFP-NEXT: addi a0, a0, 1475
1032; RV32I-WITHFP-NEXT: sw a0, 8(sp)
1033; RV32I-WITHFP-NEXT: addi a0, zero, 14
1034; RV32I-WITHFP-NEXT: sw a0, 0(sp)
1035; RV32I-WITHFP-NEXT: lui a0, 262153
1036; RV32I-WITHFP-NEXT: addi a0, a0, 491
1037; RV32I-WITHFP-NEXT: sw a0, -20(s0)
1038; RV32I-WITHFP-NEXT: lui a0, 545260
1039; RV32I-WITHFP-NEXT: addi a0, a0, -1967
1040; RV32I-WITHFP-NEXT: sw a0, -24(s0)
1041; RV32I-WITHFP-NEXT: lui a0, 964690
1042; RV32I-WITHFP-NEXT: addi a0, a0, -328
1043; RV32I-WITHFP-NEXT: sw a0, -28(s0)
1044; RV32I-WITHFP-NEXT: lui a0, 335544
1045; RV32I-WITHFP-NEXT: addi a0, a0, 1311
1046; RV32I-WITHFP-NEXT: sw a0, -32(s0)
Alex Bradbury099c7202018-04-18 19:02:31 +0000[diff] [blame]1047; RV32I-WITHFP-NEXT: lui a0, 688509
1048; RV32I-WITHFP-NEXT: addi a6, a0, -2048
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1049; RV32I-WITHFP-NEXT: addi a0, zero, 1
1050; RV32I-WITHFP-NEXT: addi a1, zero, 11
1051; RV32I-WITHFP-NEXT: addi a2, s0, -32
1052; RV32I-WITHFP-NEXT: addi a3, zero, 12
1053; RV32I-WITHFP-NEXT: addi a4, zero, 13
1054; RV32I-WITHFP-NEXT: addi a7, zero, 4
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]1055; RV32I-WITHFP-NEXT: call va5_aligned_stack_callee
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1056; RV32I-WITHFP-NEXT: lw s0, 56(sp)
1057; RV32I-WITHFP-NEXT: lw ra, 60(sp)
1058; RV32I-WITHFP-NEXT: addi sp, sp, 64
1059; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1060 %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
1061 fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
1062 i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
1063 ret void
1064}
1065
1066; A function with no fixed arguments is not valid C, but can be
1067; specified in LLVM IR. We must ensure the vararg save area is
1068; still set up correctly.
1069
1070define i32 @va6_no_fixed_args(...) nounwind {
1071; RV32I-LABEL: va6_no_fixed_args:
1072; RV32I: # %bb.0:
1073; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1074; RV32I-NEXT: sw a0, 16(sp)
1075; RV32I-NEXT: sw a7, 44(sp)
1076; RV32I-NEXT: sw a6, 40(sp)
1077; RV32I-NEXT: sw a5, 36(sp)
1078; RV32I-NEXT: sw a4, 32(sp)
1079; RV32I-NEXT: sw a3, 28(sp)
1080; RV32I-NEXT: sw a2, 24(sp)
1081; RV32I-NEXT: sw a1, 20(sp)
1082; RV32I-NEXT: addi a0, sp, 20
1083; RV32I-NEXT: sw a0, 12(sp)
1084; RV32I-NEXT: lw a0, 16(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1085; RV32I-NEXT: addi sp, sp, 48
1086; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1087; RV32I-FPELIM-LABEL: va6_no_fixed_args:
1088; RV32I-FPELIM: # %bb.0:
1089; RV32I-FPELIM-NEXT: addi sp, sp, -48
1090; RV32I-FPELIM-NEXT: sw a0, 16(sp)
1091; RV32I-FPELIM-NEXT: sw a7, 44(sp)
1092; RV32I-FPELIM-NEXT: sw a6, 40(sp)
1093; RV32I-FPELIM-NEXT: sw a5, 36(sp)
1094; RV32I-FPELIM-NEXT: sw a4, 32(sp)
1095; RV32I-FPELIM-NEXT: sw a3, 28(sp)
1096; RV32I-FPELIM-NEXT: sw a2, 24(sp)
1097; RV32I-FPELIM-NEXT: sw a1, 20(sp)
1098; RV32I-FPELIM-NEXT: addi a0, sp, 20
1099; RV32I-FPELIM-NEXT: sw a0, 12(sp)
1100; RV32I-FPELIM-NEXT: lw a0, 16(sp)
1101; RV32I-FPELIM-NEXT: addi sp, sp, 48
1102; RV32I-FPELIM-NEXT: ret
1103;
1104; RV32I-WITHFP-LABEL: va6_no_fixed_args:
1105; RV32I-WITHFP: # %bb.0:
1106; RV32I-WITHFP-NEXT: addi sp, sp, -48
1107; RV32I-WITHFP-NEXT: sw ra, 12(sp)
1108; RV32I-WITHFP-NEXT: sw s0, 8(sp)
1109; RV32I-WITHFP-NEXT: addi s0, sp, 16
1110; RV32I-WITHFP-NEXT: sw a0, 0(s0)
1111; RV32I-WITHFP-NEXT: sw a7, 28(s0)
1112; RV32I-WITHFP-NEXT: sw a6, 24(s0)
1113; RV32I-WITHFP-NEXT: sw a5, 20(s0)
1114; RV32I-WITHFP-NEXT: sw a4, 16(s0)
1115; RV32I-WITHFP-NEXT: sw a3, 12(s0)
1116; RV32I-WITHFP-NEXT: sw a2, 8(s0)
1117; RV32I-WITHFP-NEXT: sw a1, 4(s0)
1118; RV32I-WITHFP-NEXT: addi a0, s0, 4
1119; RV32I-WITHFP-NEXT: sw a0, -12(s0)
1120; RV32I-WITHFP-NEXT: lw a0, 0(s0)
1121; RV32I-WITHFP-NEXT: lw s0, 8(sp)
1122; RV32I-WITHFP-NEXT: lw ra, 12(sp)
1123; RV32I-WITHFP-NEXT: addi sp, sp, 48
1124; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1125 %va = alloca i8*, align 4
1126 %1 = bitcast i8** %va to i8*
1127 call void @llvm.va_start(i8* %1)
1128 %2 = va_arg i8** %va, i32
1129 call void @llvm.va_end(i8* %1)
1130 ret i32 %2
1131}