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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Tom Stellard75aadc22012-12-11 21:25:42 +00006//
7//===----------------------------------------------------------------------===//
8//
9/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000010/// Contains the definition of a TargetInstrInfo class that is common
Tom Stellard75aadc22012-12-11 21:25:42 +000011/// to all AMD GPUs.
12//
13//===----------------------------------------------------------------------===//
14
Matt Arsenault6b6a2c32016-03-11 08:00:27 +000015#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
Tom Stellard75aadc22012-12-11 21:25:42 +000017
Yaxun Liu1a14bfa2017-03-27 14:04:01 +000018#include "AMDGPU.h"
Sam Koltona3ec5c12016-10-07 14:46:06 +000019#include "Utils/AMDGPUBaseInfo.h"
David Blaikie3f833ed2017-11-08 01:01:31 +000020#include "llvm/CodeGen/TargetInstrInfo.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000021
Tom Stellard75aadc22012-12-11 21:25:42 +000022namespace llvm {
23
Tom Stellard5bfbae52018-07-11 20:59:01 +000024class GCNSubtarget;
Tom Stellard75aadc22012-12-11 21:25:42 +000025class MachineFunction;
26class MachineInstr;
27class MachineInstrBuilder;
28
Tom Stellardc5a154d2018-06-28 23:47:12 +000029class AMDGPUInstrInfo {
Tom Stellard75aadc22012-12-11 21:25:42 +000030public:
Tom Stellard5bfbae52018-07-11 20:59:01 +000031 explicit AMDGPUInstrInfo(const GCNSubtarget &st);
Tom Stellard75aadc22012-12-11 21:25:42 +000032
Matt Arsenaultbcf7bec2018-02-09 16:57:48 +000033 static bool isUniformMMO(const MachineMemOperand *MMO);
Tom Stellard75aadc22012-12-11 21:25:42 +000034};
Nicolai Haehnle5d0d3032018-04-01 17:09:07 +000035
36namespace AMDGPU {
37
38struct RsrcIntrinsic {
39 unsigned Intr;
40 uint8_t RsrcArg;
41 bool IsImage;
42};
Nicolai Haehnlee741d7e2018-06-21 13:36:33 +000043const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
Nicolai Haehnle5d0d3032018-04-01 17:09:07 +000044
Nicolai Haehnle2f5a7382018-04-04 10:58:54 +000045struct D16ImageDimIntrinsic {
46 unsigned Intr;
47 unsigned D16HelperIntr;
48};
Nicolai Haehnlee741d7e2018-06-21 13:36:33 +000049const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
Nicolai Haehnle2f5a7382018-04-04 10:58:54 +000050
Nicolai Haehnle7a9c03f2018-06-21 13:36:57 +000051struct ImageDimIntrinsicInfo {
52 unsigned Intr;
53 unsigned BaseOpcode;
54 MIMGDim Dim;
55};
56const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
57
Nicolai Haehnle5d0d3032018-04-01 17:09:07 +000058} // end AMDGPU namespace
Alexander Kornienkof00654e2015-06-23 09:49:53 +000059} // End llvm namespace
Tom Stellard75aadc22012-12-11 21:25:42 +000060
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000061#endif