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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Provides AMDGPU specific target descriptions.
12//
13//===----------------------------------------------------------------------===//
14//
15
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000016#ifndef LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCTARGETDESC_H
17#define LLVM_LIB_TARGET_R600_MCTARGETDESC_AMDGPUMCTARGETDESC_H
Tom Stellard75aadc22012-12-11 21:25:42 +000018
Reid Kleckner294fa7a2015-03-09 20:23:14 +000019#include "llvm/Support/DataTypes.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000020#include "llvm/ADT/StringRef.h"
21
22namespace llvm {
23class MCAsmBackend;
24class MCCodeEmitter;
25class MCContext;
26class MCInstrInfo;
Tom Stellard99916592013-04-15 17:51:21 +000027class MCObjectWriter;
Tom Stellard75aadc22012-12-11 21:25:42 +000028class MCRegisterInfo;
29class MCSubtargetInfo;
30class Target;
Daniel Sanders50f17232015-09-15 16:17:27 +000031class Triple;
Rafael Espindola5560a4c2015-04-14 22:14:34 +000032class raw_pwrite_stream;
Tom Stellard99916592013-04-15 17:51:21 +000033class raw_ostream;
Tom Stellard75aadc22012-12-11 21:25:42 +000034
35extern Target TheAMDGPUTarget;
Tom Stellard49f8bfd2015-01-06 18:00:21 +000036extern Target TheGCNTarget;
Tom Stellard75aadc22012-12-11 21:25:42 +000037
38MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
Tom Stellardedade942013-05-17 15:23:12 +000039 const MCRegisterInfo &MRI,
Eric Christopher0169e422015-03-10 22:03:14 +000040 MCContext &Ctx);
Tom Stellard75aadc22012-12-11 21:25:42 +000041
42MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
43 const MCRegisterInfo &MRI,
Tom Stellard75aadc22012-12-11 21:25:42 +000044 MCContext &Ctx);
45
Bill Wendling58e2d3d2013-09-09 02:37:14 +000046MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
Daniel Sanders50f17232015-09-15 16:17:27 +000047 const Triple &TT, StringRef CPU);
Tom Stellard99916592013-04-15 17:51:21 +000048
Tom Stellardf0296ce2015-06-22 21:03:54 +000049MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
50 raw_pwrite_stream &OS);
Alexander Kornienkof00654e2015-06-23 09:49:53 +000051} // End llvm namespace
Tom Stellard75aadc22012-12-11 21:25:42 +000052
53#define GET_REGINFO_ENUM
54#include "AMDGPUGenRegisterInfo.inc"
55
56#define GET_INSTRINFO_ENUM
57#include "AMDGPUGenInstrInfo.inc"
58
59#define GET_SUBTARGETINFO_ENUM
60#include "AMDGPUGenSubtargetInfo.inc"
61
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000062#endif