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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000011#ifndef LLVM_LIB_TARGET_R600_AMDGPU_H
12#define LLVM_LIB_TARGET_R600_AMDGPU_H
Tom Stellard75aadc22012-12-11 21:25:42 +000013
Tom Stellard75aadc22012-12-11 21:25:42 +000014#include "llvm/Support/TargetRegistry.h"
15#include "llvm/Target/TargetMachine.h"
16
17namespace llvm {
18
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000019class AMDGPUInstrPrinter;
Tom Stellard880a80a2014-06-17 16:53:14 +000020class AMDGPUSubtarget;
Tom Stellard75aadc22012-12-11 21:25:42 +000021class AMDGPUTargetMachine;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000022class FunctionPass;
Hans Wennborg81efb6b2016-01-13 18:59:45 +000023struct MachineSchedContext;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000024class MCAsmInfo;
25class raw_ostream;
Nicolai Haehnle02c32912016-01-13 16:10:10 +000026class ScheduleDAGInstrs;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000027class Target;
28class TargetMachine;
Tom Stellard75aadc22012-12-11 21:25:42 +000029
30// R600 Passes
Vincent Lejeunedec18752013-06-05 21:38:04 +000031FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000032FunctionPass *createR600TextureIntrinsicsReplacer();
Tom Stellard75aadc22012-12-11 21:25:42 +000033FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
Tom Stellard1de55822013-12-11 17:51:41 +000034FunctionPass *createR600EmitClauseMarkers();
Vincent Lejeunea4da6fb2013-10-01 19:32:58 +000035FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
Vincent Lejeune147700b2013-04-30 00:14:27 +000036FunctionPass *createR600Packetizer(TargetMachine &tm);
Vincent Lejeunebfaa63a62013-04-01 21:48:05 +000037FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
Tom Stellardf2ba9722013-12-11 17:51:47 +000038FunctionPass *createAMDGPUCFGStructurizerPass();
Tom Stellard75aadc22012-12-11 21:25:42 +000039
40// SI Passes
Tom Stellard9fa17912013-08-14 23:24:45 +000041FunctionPass *createSITypeRewriter();
Tom Stellardf8794352012-12-19 22:10:31 +000042FunctionPass *createSIAnnotateControlFlowPass();
Tom Stellard6596ba72014-11-21 22:06:37 +000043FunctionPass *createSIFoldOperandsPass();
Tom Stellard1bd80722014-04-30 15:31:33 +000044FunctionPass *createSILowerI1CopiesPass();
Tom Stellard1aaad692014-07-21 16:55:33 +000045FunctionPass *createSIShrinkInstructionsPass();
Matt Arsenault41033282014-10-10 22:01:59 +000046FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
Matt Arsenault55d49cf2016-02-12 02:16:10 +000047FunctionPass *createSILowerControlFlowPass();
Tom Stellard28d13a42015-05-12 17:13:02 +000048FunctionPass *createSIFixControlFlowLiveIntervalsPass();
Matt Arsenault782c03b2015-11-03 22:30:13 +000049FunctionPass *createSIFixSGPRCopiesPass();
Tom Stellardb2de94e2014-07-02 20:53:48 +000050FunctionPass *createSIFixSGPRLiveRangesPass();
Tom Stellard75aadc22012-12-11 21:25:42 +000051FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
Tom Stellard6e1967e2016-02-05 17:42:38 +000052FunctionPass *createSIInsertWaitsPass();
Tom Stellard75aadc22012-12-11 21:25:42 +000053
Nicolai Haehnle02c32912016-01-13 16:10:10 +000054ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C);
55
Matt Arsenault39319482015-11-06 18:01:57 +000056ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
57void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
58extern char &AMDGPUAnnotateKernelFeaturesID;
59
Tom Stellard6596ba72014-11-21 22:06:37 +000060void initializeSIFoldOperandsPass(PassRegistry &);
61extern char &SIFoldOperandsID;
62
Matt Arsenault782c03b2015-11-03 22:30:13 +000063void initializeSIFixSGPRCopiesPass(PassRegistry &);
64extern char &SIFixSGPRCopiesID;
65
Tom Stellard1bd80722014-04-30 15:31:33 +000066void initializeSILowerI1CopiesPass(PassRegistry &);
67extern char &SILowerI1CopiesID;
68
Matt Arsenault41033282014-10-10 22:01:59 +000069void initializeSILoadStoreOptimizerPass(PassRegistry &);
70extern char &SILoadStoreOptimizerID;
71
Matt Arsenault55d49cf2016-02-12 02:16:10 +000072void initializeSILowerControlFlowPass(PassRegistry &);
73extern char &SILowerControlFlowPassID;
74
75
Tom Stellard75aadc22012-12-11 21:25:42 +000076// Passes common to R600 and SI
Matt Arsenaulte0132462016-01-30 05:19:45 +000077FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
78void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
79extern char &AMDGPUPromoteAllocaID;
80
Tom Stellardbc4497b2016-02-12 23:45:29 +000081FunctionPass *createAMDGPUAddDivergenceMetadata(const AMDGPUSubtarget &ST);
Tom Stellardf8794352012-12-19 22:10:31 +000082Pass *createAMDGPUStructurizeCFGPass();
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000083FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
Tom Stellard5cbb53c2014-11-03 19:49:05 +000084ModulePass *createAMDGPUAlwaysInlinePass();
Tom Stellardfd253952015-08-07 23:19:30 +000085ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
Tom Stellarda6f24c62015-12-15 20:55:55 +000086FunctionPass *createAMDGPUAnnotateUniformValues();
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000087
Tom Stellard28d13a42015-05-12 17:13:02 +000088void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
89extern char &SIFixControlFlowLiveIntervalsID;
90
Tom Stellardb2de94e2014-07-02 20:53:48 +000091void initializeSIFixSGPRLiveRangesPass(PassRegistry&);
92extern char &SIFixSGPRLiveRangesID;
93
Tom Stellarda6f24c62015-12-15 20:55:55 +000094void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
95extern char &AMDGPUAnnotateUniformValuesPassID;
Tom Stellardb2de94e2014-07-02 20:53:48 +000096
Tom Stellard77a17772016-01-20 15:48:27 +000097void initializeSIAnnotateControlFlowPass(PassRegistry&);
98extern char &SIAnnotateControlFlowPassID;
99
Tom Stellard6e1967e2016-02-05 17:42:38 +0000100void initializeSIInsertWaitsPass(PassRegistry&);
101extern char &SIInsertWaitsID;
102
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000103extern Target TheAMDGPUTarget;
Tom Stellard49f8bfd2015-01-06 18:00:21 +0000104extern Target TheGCNTarget;
Tom Stellard75aadc22012-12-11 21:25:42 +0000105
Tom Stellard067c8152014-07-21 14:01:14 +0000106namespace AMDGPU {
107enum TargetIndex {
Tom Stellard95292bb2015-01-20 17:49:47 +0000108 TI_CONSTDATA_START,
109 TI_SCRATCH_RSRC_DWORD0,
110 TI_SCRATCH_RSRC_DWORD1,
111 TI_SCRATCH_RSRC_DWORD2,
112 TI_SCRATCH_RSRC_DWORD3
Tom Stellard067c8152014-07-21 14:01:14 +0000113};
114}
115
Tom Stellard75aadc22012-12-11 21:25:42 +0000116} // End namespace llvm
117
118namespace ShaderType {
119 enum Type {
120 PIXEL = 0,
121 VERTEX = 1,
122 GEOMETRY = 2,
123 COMPUTE = 3
124 };
125}
126
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000127/// OpenCL uses address spaces to differentiate between
128/// various memory regions on the hardware. On the CPU
129/// all of the address spaces point to the same memory,
130/// however on the GPU, each address space points to
Alp Tokercb402912014-01-24 17:20:08 +0000131/// a separate piece of memory that is unique from other
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000132/// memory locations.
133namespace AMDGPUAS {
Reid Kleckner218a9592015-06-08 21:57:57 +0000134enum AddressSpaces : unsigned {
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000135 PRIVATE_ADDRESS = 0, ///< Address space for private memory.
136 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
137 CONSTANT_ADDRESS = 2, ///< Address space for constant memory
138 LOCAL_ADDRESS = 3, ///< Address space for local memory.
Matt Arsenault46b51b72014-05-22 18:27:07 +0000139 FLAT_ADDRESS = 4, ///< Address space for flat memory.
140 REGION_ADDRESS = 5, ///< Address space for region memory.
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000141 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
142 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
Tom Stellard1e803092013-07-23 01:48:18 +0000143
144 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
145 // order to be able to dynamically index a constant buffer, for example:
146 //
147 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
148
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000149 CONSTANT_BUFFER_0 = 8,
150 CONSTANT_BUFFER_1 = 9,
151 CONSTANT_BUFFER_2 = 10,
152 CONSTANT_BUFFER_3 = 11,
153 CONSTANT_BUFFER_4 = 12,
154 CONSTANT_BUFFER_5 = 13,
155 CONSTANT_BUFFER_6 = 14,
156 CONSTANT_BUFFER_7 = 15,
157 CONSTANT_BUFFER_8 = 16,
158 CONSTANT_BUFFER_9 = 17,
159 CONSTANT_BUFFER_10 = 18,
160 CONSTANT_BUFFER_11 = 19,
161 CONSTANT_BUFFER_12 = 20,
162 CONSTANT_BUFFER_13 = 21,
163 CONSTANT_BUFFER_14 = 22,
164 CONSTANT_BUFFER_15 = 23,
Matt Arsenault46b51b72014-05-22 18:27:07 +0000165 ADDRESS_NONE = 24, ///< Address space for unknown memory.
Matt Arsenault73e06fa2015-06-04 16:17:42 +0000166 LAST_ADDRESS = ADDRESS_NONE,
167
168 // Some places use this if the address space can't be determined.
169 UNKNOWN_ADDRESS_SPACE = ~0u
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000170};
171
172} // namespace AMDGPUAS
173
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000174#endif