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gerrit-public.fairphone.software / toolchain / llvm-project / ce3ddd2de4c5dbd5a7a68b51ea38f96cf7fbf3aa / . / llvm / test / Transforms / LoopUnswitch / 2011-11-18-TwoSwitches-Threshold.ll
blob: 393dd5c313a4c0dccdb17b05acb6812f3879eefd [file] [log] [blame]
Jan Wen Voung6dc30762013-03-12 16:27:52 +0000[diff] [blame]1; REQUIRES: asserts
Stepan Dyatkovskiy82165692012-01-11 08:40:51 +0000[diff] [blame]2; RUN: opt -loop-unswitch -loop-unswitch-threshold 13 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s
Dmitri Gribenkob137c9e2012-12-30 01:28:40 +0000[diff] [blame]3; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 13 -verify-loop-info -verify-dom-info < %s | FileCheck %s
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]4
5; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted
6; STATS: 1 loop-unswitch - Number of switches unswitched
7
8; ModuleID = '../llvm/test/Transforms/LoopUnswitch/2011-11-18-TwoSwitches.ll'
9
10; CHECK: %1 = icmp eq i32 %c, 1
11; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge
12
13; CHECK: ..split_crit_edge: ; preds = %0
14; CHECK-NEXT: br label %.split
15
16; CHECK: .split.us: ; preds = %0
17; CHECK-NEXT: br label %loop_begin.us
18
19; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us
20; CHECK: switch i32 1, label %second_switch.us [
21; CHECK-NEXT: i32 1, label %inc.us
22
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]23; CHECK: second_switch.us: ; preds = %loop_begin.us
24; CHECK-NEXT: switch i32 %d, label %default.us [
25; CHECK-NEXT: i32 1, label %inc.us
26; CHECK-NEXT: ]
27
Andrew Trickfb2ba3e2012-06-26 04:11:38 +0000[diff] [blame]28; CHECK: inc.us: ; preds = %second_switch.us, %loop_begin.us
Bill Wendlinga0323742013-02-22 09:09:42 +0000[diff] [blame]29; CHECK-NEXT: call void @incf() [[NOR_NUW:#[0-9]+]]
Andrew Trickfb2ba3e2012-06-26 04:11:38 +0000[diff] [blame]30; CHECK-NEXT: br label %loop_begin.backedge.us
31
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]32; CHECK: .split: ; preds = %..split_crit_edge
33; CHECK-NEXT: br label %loop_begin
34
35; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split
36; CHECK: switch i32 %c, label %second_switch [
37; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge
38; CHECK-NEXT: ]
39
40; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin
41; CHECK-NEXT: br i1 true, label %us-unreachable, label %inc
42
43; CHECK: second_switch: ; preds = %loop_begin
44; CHECK-NEXT: switch i32 %d, label %default [
45; CHECK-NEXT: i32 1, label %inc
46; CHECK-NEXT: ]
47
48; CHECK: inc: ; preds = %loop_begin.inc_crit_edge, %second_switch
Bill Wendlinga0323742013-02-22 09:09:42 +0000[diff] [blame]49; CHECK-NEXT: call void @incf() [[NOR_NUW]]
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]50; CHECK-NEXT: br label %loop_begin.backedge
51
52define i32 @test(i32* %var) {
53 %mem = alloca i32
54 store i32 2, i32* %mem
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]55 %c = load i32, i32* %mem
56 %d = load i32, i32* %mem
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]57
58 br label %loop_begin
59
60loop_begin:
61
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]62 %var_val = load i32, i32* %var
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]63
64 switch i32 %c, label %second_switch [
65 i32 1, label %inc
66 ]
67
68second_switch:
69 switch i32 %d, label %default [
70 i32 1, label %inc
71 ]
72
73inc:
74 call void @incf() noreturn nounwind
75 br label %loop_begin
76
Andrew Trickfb2ba3e2012-06-26 04:11:38 +0000[diff] [blame]77default:
Chad Rosier38876942011-12-22 21:06:36 +0000[diff] [blame]78 br label %loop_begin
79
80loop_exit:
81 ret i32 0
82}
83
84declare void @incf() noreturn
85declare void @decf() noreturn
Bill Wendlinga0323742013-02-22 09:09:42 +0000[diff] [blame]86
87; CHECK: attributes #0 = { noreturn }
88; CHECK: attributes [[NOR_NUW]] = { noreturn nounwind }