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gerrit-public.fairphone.software / toolchain / llvm-project / 4b96ce96c60c01e96b865bcc08f212f8ea0983d2 / . / llvm / lib / Target / Hexagon / HexagonIntrinsicsV4.td
blob: 556e19d2cc0e6f45bb3bd5740576f6ad274ad3c8 [file] [log] [blame]
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]1//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is populated based on the following specs:
10// Hexagon V4 Architecture Extensions
11// Application-Level Specification
12// 80-V9418-12 Rev. A
13// June 15, 2010
14
Colin LeMahieu99cc7c12015-02-03 19:15:11 +0000[diff] [blame]15// Vector reduce multiply word by signed half (32x16)
16//Rdd=vrmpyweh(Rss,Rtt)[:<<1]
17def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
18def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
19
20//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
21def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
22def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
23
24//Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
25def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
26def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
27
28//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
29def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
30def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
31
32// Vector multiply halfwords, signed by unsigned
33// Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
34def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
35def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
36
37// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
38def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>;
39def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>;
40
41// Vector polynomial multiply halfwords
42// Rdd=vpmpyh(Rs,Rt)
43def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>;
44// Rxx[^]=vpmpyh(Rs,Rt)
45def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>;
46
Colin LeMahieu94c33212015-01-28 19:16:17 +0000[diff] [blame]47// Polynomial multiply words
48// Rdd=pmpyw(Rs,Rt)
49def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
50// Rxx^=pmpyw(Rs,Rt)
51def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
52
53//Rxx^=asr(Rss,Rt)
54def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
55//Rxx^=asl(Rss,Rt)
56def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
57//Rxx^=lsr(Rss,Rt)
58def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
59//Rxx^=lsl(Rss,Rt)
60def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
61
62// Multiply and use upper result
63def : MType_R32_pat <int_hexagon_M2_mpysu_up, M2_mpysu_up>;
64def : MType_R32_pat <int_hexagon_M2_mpy_up_s1, M2_mpy_up_s1>;
65def : MType_R32_pat <int_hexagon_M2_hmmpyh_s1, M2_hmmpyh_s1>;
66def : MType_R32_pat <int_hexagon_M2_hmmpyl_s1, M2_hmmpyl_s1>;
67def : MType_R32_pat <int_hexagon_M2_mpy_up_s1_sat, M2_mpy_up_s1_sat>;
68
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]69// Vector reduce add unsigned halfwords
70def : Pat <(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2),
71 (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>;
72
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]73def : T_P_pat <S2_brevp, int_hexagon_S2_brevp>;
74
75def: T_P_pat <S2_ct0p, int_hexagon_S2_ct0p>;
76def: T_P_pat <S2_ct1p, int_hexagon_S2_ct1p>;
77def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
78def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
79def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
80
Colin LeMahieua749b3e2015-01-29 16:08:43 +0000[diff] [blame]81def : T_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>;
82def : T_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>;
83def : T_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>;
84def : T_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>;
85def : T_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>;
86def : T_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>;
87
88def : T_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>;
89def : T_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>;
90def : T_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>;
91
92def : T_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>;
93def : T_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>;
94def : T_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>;
95
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]96def : T_RP_pat <A4_boundscheck, int_hexagon_A4_boundscheck>;
97
98def : T_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>;
99
Colin LeMahieu94c33212015-01-28 19:16:17 +0000[diff] [blame]100def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
101 IntRegs:$src3),
102 (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
103
104def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>;
105def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>;
106def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
107def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
108// Multiply 32x32 and use upper result
109def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
110def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
111
Colin LeMahieua6632452015-02-03 18:16:28 +0000[diff] [blame]112// Complex multiply 32x16
113def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>;
114def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>;
115
116def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>;
117def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>;
118
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]119def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
120def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>;
121
Colin LeMahieua6632452015-02-03 18:16:28 +0000[diff] [blame]122// Complex add/sub halfwords/words
123def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>;
124def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>;
125def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>;
126def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>;
127
128def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>;
129def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>;
130
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]131// Extract bitfield
132def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
133def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
134def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
135def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
136
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]137// Vector conditional negate
138// Rdd=vcnegh(Rss,Rt)
139def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>;
140
Colin LeMahieufe03c9a2015-01-28 17:37:59 +0000[diff] [blame]141// Shift an immediate left by register amount
142def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
143
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]144// Vector reduce maximum halfwords
145def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>;
146def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>;
147
148// Vector reduce maximum words
149def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>;
150def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>;
151
152// Vector reduce minimum halfwords
153def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>;
154def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>;
155
156// Vector reduce minimum words
157def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>;
158def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>;
159
Colin LeMahieua6632452015-02-03 18:16:28 +0000[diff] [blame]160// Rotate and reduce bytes
161def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
162 u2ImmPred:$src3),
163 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2ImmPred:$src3)>;
164
165// Rotate and reduce bytes with accumulation
166// Rxx+=vrcrotate(Rss,Rt,#u2)
167def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
168 IntRegs:$src3, u2ImmPred:$src4),
169 (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
170 IntRegs:$src3, u2ImmPred:$src4)>;
171
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]172// Vector conditional negate
173def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>;
174
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]175// Logical xor with xor accumulation
176def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
177
Colin LeMahieucdba4e12015-02-03 18:01:45 +0000[diff] [blame]178// ALU64 - Vector min/max byte
179def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>;
180def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>;
181
Colin LeMahieufe03c9a2015-01-28 17:37:59 +0000[diff] [blame]182// Shift and add/sub/and/or
183def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
184def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
185def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
186def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
187def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
188def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>;
189def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
190def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]191
Colin LeMahieu39b846c2015-01-28 18:06:23 +0000[diff] [blame]192// Split bitfield
193def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
194def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>;
195
196def: T_RR_pat<S4_parity, int_hexagon_S4_parity>;
197
198def: T_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
199def: T_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
200
201def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>;
202def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
203def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
204
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]205/********************************************************************
206* ALU32/ALU *
207*********************************************************************/
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]208
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]209// ALU32 / ALU / Logical Operations.
210def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
211def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]212
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]213/********************************************************************
214* ALU32/PERM *
215*********************************************************************/
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]216
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]217// Combine Words Into Doublewords.
218def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s8ExtPred>;
219def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
220
221/********************************************************************
222* ALU32/PRED *
223*********************************************************************/
224
Colin LeMahieu860210b2015-01-29 16:55:37 +0000[diff] [blame]225// Compare
226def : T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s10ExtPred>;
227def : T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s10ExtPred>;
228def : T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u9ExtPred>;
229
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]230def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>;
231def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
232
233def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>;
234def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
235
236/********************************************************************
Colin LeMahieu860210b2015-01-29 16:55:37 +0000[diff] [blame]237* CR *
238*********************************************************************/
239
240// CR / Logical Operations On Predicates.
241
242class qi_CRInst_qiqiqi_pat<Intrinsic IntID, InstHexagon Inst> :
243 Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt, IntRegs:$Ru)),
244 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs),
245 (C2_tfrrp IntRegs:$Rt),
246 (C2_tfrrp IntRegs:$Ru))))>;
247
248def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_and, C4_and_and>;
249def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_andn, C4_and_andn>;
250def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_or, C4_and_or>;
251def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_and_orn, C4_and_orn>;
252def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_and, C4_or_and>;
253def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_andn, C4_or_andn>;
254def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_or, C4_or_or>;
255def: qi_CRInst_qiqiqi_pat<int_hexagon_C4_or_orn, C4_or_orn>;
256
257/********************************************************************
Colin LeMahieu1de7e0d2015-01-28 19:39:09 +0000[diff] [blame]258* XTYPE/ALU *
259*********************************************************************/
260
261// Add And Accumulate.
262
263def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
264def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
265
266
267// XTYPE / ALU / Logical-logical Words.
268def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>;
269def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>;
270def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>;
271def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>;
272def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>;
273def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>;
274def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>;
275def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>;
276def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>;
277def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
278def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
279
280def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
281def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>;
282def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
283
284// Modulo wrap.
285def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
286
287// Arithmetic/Convergent round
288// Rd=[cround|round](Rs,Rt)[:sat]
289// Rd=[cround|round](Rs,#u5)[:sat]
290def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
291def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
292
293def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
294def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
295
296def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
297def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
298
299def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;