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Tom Stellardcb6ba622016-04-30 00:23:06 +00001//===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines hazard recognizers for scheduling on GCN processors.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
15#define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
16
Benjamin Kramerd3f4c052016-06-12 16:13:55 +000017#include "llvm/ADT/STLExtras.h"
Tom Stellardcb6ba622016-04-30 00:23:06 +000018#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
Tom Stellardcb6ba622016-04-30 00:23:06 +000019#include <list>
20
21namespace llvm {
22
23class MachineFunction;
24class MachineInstr;
25class ScheduleDAG;
26class SIInstrInfo;
Matt Arsenault43e92fe2016-06-24 06:30:11 +000027class SISubtarget;
Tom Stellardcb6ba622016-04-30 00:23:06 +000028
29class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
Matt Arsenault43e92fe2016-06-24 06:30:11 +000030 // This variable stores the instruction that has been emitted this cycle. It
31 // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
Tom Stellardcb6ba622016-04-30 00:23:06 +000032 // called.
33 MachineInstr *CurrCycleInstr;
34 std::list<MachineInstr*> EmittedInstrs;
35 const MachineFunction &MF;
Matt Arsenault43e92fe2016-06-24 06:30:11 +000036 const SISubtarget &ST;
Tom Stellardcb6ba622016-04-30 00:23:06 +000037
38 int getWaitStatesSinceDef(unsigned Reg,
Benjamin Kramerd3f4c052016-06-12 16:13:55 +000039 function_ref<bool(MachineInstr *)> IsHazardDef =
40 [](MachineInstr *) { return true; });
Tom Stellardcb6ba622016-04-30 00:23:06 +000041
Tom Stellard1f520e52016-05-02 17:39:06 +000042 int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
Tom Stellardcb6ba622016-04-30 00:23:06 +000043 int checkSMRDHazards(MachineInstr *SMRD);
44 int checkVMEMHazards(MachineInstr* VMEM);
Tom Stellarda27007e2016-05-02 16:23:09 +000045 int checkDPPHazards(MachineInstr *DPP);
Tom Stellardcb6ba622016-04-30 00:23:06 +000046public:
47 GCNHazardRecognizer(const MachineFunction &MF);
48 // We can only issue one instruction per cycle.
49 bool atIssueLimit() const override { return true; }
50 void EmitInstruction(SUnit *SU) override;
51 void EmitInstruction(MachineInstr *MI) override;
52 HazardType getHazardType(SUnit *SU, int Stalls) override;
53 void EmitNoop() override;
54 unsigned PreEmitNoops(SUnit *SU) override;
55 unsigned PreEmitNoops(MachineInstr *) override;
56 void AdvanceCycle() override;
57 void RecedeCycle() override;
58};
59
60} // end namespace llvm
61
62#endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H