Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 1 | //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines hazard recognizers for scheduling on GCN processors. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H |
| 15 | #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H |
| 16 | |
Benjamin Kramer | d3f4c05 | 2016-06-12 16:13:55 +0000 | [diff] [blame] | 17 | #include "llvm/ADT/STLExtras.h" |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/ScheduleHazardRecognizer.h" |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 19 | #include <list> |
| 20 | |
| 21 | namespace llvm { |
| 22 | |
| 23 | class MachineFunction; |
| 24 | class MachineInstr; |
| 25 | class ScheduleDAG; |
| 26 | class SIInstrInfo; |
Matt Arsenault | 43e92fe | 2016-06-24 06:30:11 +0000 | [diff] [blame] | 27 | class SISubtarget; |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 28 | |
| 29 | class GCNHazardRecognizer final : public ScheduleHazardRecognizer { |
Matt Arsenault | 43e92fe | 2016-06-24 06:30:11 +0000 | [diff] [blame] | 30 | // This variable stores the instruction that has been emitted this cycle. It |
| 31 | // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 32 | // called. |
| 33 | MachineInstr *CurrCycleInstr; |
| 34 | std::list<MachineInstr*> EmittedInstrs; |
| 35 | const MachineFunction &MF; |
Matt Arsenault | 43e92fe | 2016-06-24 06:30:11 +0000 | [diff] [blame] | 36 | const SISubtarget &ST; |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 37 | |
| 38 | int getWaitStatesSinceDef(unsigned Reg, |
Benjamin Kramer | d3f4c05 | 2016-06-12 16:13:55 +0000 | [diff] [blame] | 39 | function_ref<bool(MachineInstr *)> IsHazardDef = |
| 40 | [](MachineInstr *) { return true; }); |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 41 | |
Tom Stellard | 1f520e5 | 2016-05-02 17:39:06 +0000 | [diff] [blame] | 42 | int checkSMEMSoftClauseHazards(MachineInstr *SMEM); |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 43 | int checkSMRDHazards(MachineInstr *SMRD); |
| 44 | int checkVMEMHazards(MachineInstr* VMEM); |
Tom Stellard | a27007e | 2016-05-02 16:23:09 +0000 | [diff] [blame] | 45 | int checkDPPHazards(MachineInstr *DPP); |
Tom Stellard | cb6ba62 | 2016-04-30 00:23:06 +0000 | [diff] [blame] | 46 | public: |
| 47 | GCNHazardRecognizer(const MachineFunction &MF); |
| 48 | // We can only issue one instruction per cycle. |
| 49 | bool atIssueLimit() const override { return true; } |
| 50 | void EmitInstruction(SUnit *SU) override; |
| 51 | void EmitInstruction(MachineInstr *MI) override; |
| 52 | HazardType getHazardType(SUnit *SU, int Stalls) override; |
| 53 | void EmitNoop() override; |
| 54 | unsigned PreEmitNoops(SUnit *SU) override; |
| 55 | unsigned PreEmitNoops(MachineInstr *) override; |
| 56 | void AdvanceCycle() override; |
| 57 | void RecedeCycle() override; |
| 58 | }; |
| 59 | |
| 60 | } // end namespace llvm |
| 61 | |
| 62 | #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H |