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gerrit-public.fairphone.software / toolchain / llvm-project / 9e18922d671f3999ef2b5f865c40faf845b47925 / . / llvm / lib / Target / ARM / ARMISelLowering.h
blob: 1d1b42abeda8af5f99c0cb35cf838cbb09b995ab [file] [log] [blame]
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Craig Topper188ed9d2012-03-17 07:33:42 +0000[diff] [blame]18#include "ARM.h"
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]19#include "ARMSubtarget.h"
Chandler Carruth802d7552012-12-04 07:12:27 +0000[diff] [blame]20#include "llvm/CodeGen/CallingConvLower.h"
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]21#include "llvm/CodeGen/FastISel.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]22#include "llvm/CodeGen/SelectionDAG.h"
Chandler Carruth802d7552012-12-04 07:12:27 +0000[diff] [blame]23#include "llvm/Target/TargetLowering.h"
24#include "llvm/Target/TargetRegisterInfo.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]25#include <vector>
26
27namespace llvm {
28 class ARMConstantPoolValue;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]29
30 namespace ARMISD {
31 // ARM Specific DAG Nodes
32 enum NodeType {
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]33 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohmaned1cf1a2008-09-23 18:42:32 +0000[diff] [blame]34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]35
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng2f2435d2011-01-21 18:55:51 +0000[diff] [blame]38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
39 // DYN mode.
Evan Chengdfce83c2011-01-17 08:03:18 +0000[diff] [blame]40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
41 // PIC mode.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]43
Manman Ren9f911162012-06-01 02:44:42 +0000[diff] [blame]44 // Add pseudo op to model memcpy for struct byval.
45 COPY_STRUCT_BYVAL,
46
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]47 CALL, // Function call.
Evan Chengc3c949b42007-06-19 21:05:09 +0000[diff] [blame]48 CALL_PRED, // Function call that's predicable.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]49 CALL_NOLINK, // Function call with branch not branch-and-link.
50 tCALL, // Thumb function call.
51 BRCOND, // Conditional branch.
52 BR_JT, // Jumptable branch.
Evan Chengc6d70ae2009-07-29 02:18:14 +0000[diff] [blame]53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]54 RET_FLAG, // Return with a flag operand.
55
56 PIC_ADD, // Add with a PC operand and a PIC label.
57
58 CMP, // ARM compare instructions.
Bill Wendling4b796472012-06-11 08:07:26 +0000[diff] [blame]59 CMN, // ARM CMN instructions.
David Goodwindbf11ba2009-06-29 15:33:01 +0000[diff] [blame]60 CMPZ, // ARM compare that sets only Z flag.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]61 CMPFP, // ARM VFP compare instruction, sets FPSCR.
62 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
63 FMSTAT, // ARM fmstat instruction.
Evan Chenge87681c2012-02-23 01:19:06 +0000[diff] [blame]64
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]65 CMOV, // ARM conditional move instructions.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]66
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]67 BCC_i64,
68
Jim Grosbach8546ec92010-01-18 19:58:49 +0000[diff] [blame]69 RBIT, // ARM bitreverse instruction
70
Bob Wilsone4191e72010-03-19 22:51:32 +0000[diff] [blame]71 FTOSI, // FP to sint within a FP register.
72 FTOUI, // FP to uint within a FP register.
73 SITOF, // sint to FP within a FP register.
74 UITOF, // uint to FP within a FP register.
75
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]76 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
77 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
78 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]79
Evan Chenge8916542011-08-30 01:34:54 +0000[diff] [blame]80 ADDC, // Add with carry
81 ADDE, // Add using carry
82 SUBC, // Sub with carry
83 SUBE, // Sub using carry
84
Jim Grosbachd7cf55c2009-11-09 00:11:35 +0000[diff] [blame]85 VMOVRRD, // double to two gprs.
86 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +0000[diff] [blame]87
Jim Grosbachbbdc5d22010-10-19 23:27:08 +0000[diff] [blame]88 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
89 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbachaeca45d2009-05-12 23:59:14 +0000[diff] [blame]90
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]91 TC_RETURN, // Tail call return pseudo.
92
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]93 THREAD_POINTER,
94
Evan Chengb972e562009-08-07 00:34:42 +0000[diff] [blame]95 DYN_ALLOC, // Dynamic allocation on the stack.
96
Bob Wilson7ed59712010-10-30 00:54:37 +0000[diff] [blame]97 MEMBARRIER, // Memory barrier (DMB)
98 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]99
100 PRELOAD, // Preload
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]101
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]102 VCEQ, // Vector compare equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]103 VCEQZ, // Vector compare equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]104 VCGE, // Vector compare greater than or equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]105 VCGEZ, // Vector compare greater than or equal to zero.
106 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]107 VCGEU, // Vector compare unsigned greater than or equal.
108 VCGT, // Vector compare greater than.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]109 VCGTZ, // Vector compare greater than zero.
110 VCLTZ, // Vector compare less than zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]111 VCGTU, // Vector compare unsigned greater than.
112 VTST, // Vector test bits.
113
114 // Vector shift by immediate:
115 VSHL, // ...left
116 VSHRs, // ...right (signed)
117 VSHRu, // ...right (unsigned)
118 VSHLLs, // ...left long (signed)
119 VSHLLu, // ...left long (unsigned)
120 VSHLLi, // ...left long (with maximum shift count)
121 VSHRN, // ...right narrow
122
123 // Vector rounding shift by immediate:
124 VRSHRs, // ...right (signed)
125 VRSHRu, // ...right (unsigned)
126 VRSHRN, // ...right narrow
127
128 // Vector saturating shift by immediate:
129 VQSHLs, // ...left (signed)
130 VQSHLu, // ...left (unsigned)
131 VQSHLsu, // ...left (signed to unsigned)
132 VQSHRNs, // ...right narrow (signed)
133 VQSHRNu, // ...right narrow (unsigned)
134 VQSHRNsu, // ...right narrow (signed to unsigned)
135
136 // Vector saturating rounding shift by immediate:
137 VQRSHRNs, // ...right narrow (signed)
138 VQRSHRNu, // ...right narrow (unsigned)
139 VQRSHRNsu, // ...right narrow (signed to unsigned)
140
141 // Vector shift and insert:
142 VSLI, // ...left
143 VSRI, // ...right
144
145 // Vector get lane (VMOV scalar to ARM core register)
146 // (These are used for 8- and 16-bit element types only.)
147 VGETLANEu, // zero-extend vector extract element
148 VGETLANEs, // sign-extend vector extract element
149
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]150 // Vector move immediate and move negated immediate:
Bob Wilsona3f19012010-07-13 21:16:48 +0000[diff] [blame]151 VMOVIMM,
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]152 VMVNIMM,
153
Evan Cheng7ca4b6e2011-11-15 02:12:34 +0000[diff] [blame]154 // Vector move f32 immediate:
155 VMOVFPIMM,
156
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]157 // Vector duplicate:
Bob Wilsoneb54d512009-08-14 05:13:08 +0000[diff] [blame]158 VDUP,
Bob Wilsoncce31f62009-08-14 05:08:32 +0000[diff] [blame]159 VDUPLANE,
Bob Wilsonf45dee32009-08-04 00:36:16 +0000[diff] [blame]160
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]161 // Vector shuffles:
Bob Wilson32cd8552009-08-19 17:03:43 +0000[diff] [blame]162 VEXT, // extract
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]163 VREV64, // reverse elements within 64-bit doublewords
164 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov9a232f42009-08-21 12:41:24 +0000[diff] [blame]165 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsona7062312009-08-21 20:54:19 +0000[diff] [blame]166 VZIP, // zip (interleave)
167 VUZP, // unzip (deinterleave)
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]168 VTRN, // transpose
Bill Wendlinge1fd78f2011-03-14 23:02:38 +0000[diff] [blame]169 VTBL1, // 1-register shuffle with mask
170 VTBL2, // 2-register shuffle with mask
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]171
Bob Wilson38ab35a2010-09-01 23:50:19 +0000[diff] [blame]172 // Vector multiply long:
173 VMULLs, // ...signed
174 VMULLu, // ...unsigned
175
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000[diff] [blame]176 UMLAL, // 64bit Unsigned Accumulate Multiply
177 SMLAL, // 64bit Signed Accumulate Multiply
178
Bob Wilsond8a9a042010-06-04 00:04:02 +0000[diff] [blame]179 // Operands of the standard BUILD_VECTOR node are not legalized, which
180 // is fine if BUILD_VECTORs are always lowered to shuffles or other
181 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
182 // operands need to be legalized. Define an ARM-specific version of
183 // BUILD_VECTOR for this purpose.
184 BUILD_VECTOR,
185
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]186 // Floating-point max and min:
187 FMAX,
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]188 FMIN,
189
190 // Bit-field insert
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]191 BFI,
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]192
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]193 // Vector OR with immediate
Owen Anderson30c48922010-11-05 19:27:46 +0000[diff] [blame]194 VORRIMM,
195 // Vector AND with NOT of immediate
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]196 VBICIMM,
197
Cameron Zwarich53dd03d2011-03-30 23:01:21 +0000[diff] [blame]198 // Vector bitwise select
199 VBSL,
200
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]201 // Vector load N-element structure to all lanes:
202 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
203 VLD3DUP,
Bob Wilson06fce872011-02-07 17:43:21 +0000[diff] [blame]204 VLD4DUP,
205
206 // NEON loads with post-increment base updates:
207 VLD1_UPD,
208 VLD2_UPD,
209 VLD3_UPD,
210 VLD4_UPD,
211 VLD2LN_UPD,
212 VLD3LN_UPD,
213 VLD4LN_UPD,
214 VLD2DUP_UPD,
215 VLD3DUP_UPD,
216 VLD4DUP_UPD,
217
218 // NEON stores with post-increment base updates:
219 VST1_UPD,
220 VST2_UPD,
221 VST3_UPD,
222 VST4_UPD,
223 VST2LN_UPD,
224 VST3LN_UPD,
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]225 VST4LN_UPD,
226
227 // 64-bit atomic ops (value split into two registers)
228 ATOMADD64_DAG,
229 ATOMSUB64_DAG,
230 ATOMOR64_DAG,
231 ATOMXOR64_DAG,
232 ATOMAND64_DAG,
233 ATOMNAND64_DAG,
234 ATOMSWAP64_DAG,
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]235 ATOMCMPXCHG64_DAG,
236 ATOMMIN64_DAG,
237 ATOMUMIN64_DAG,
238 ATOMMAX64_DAG,
239 ATOMUMAX64_DAG
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]240 };
241 }
242
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]243 /// Define some predicates that are used for node matching.
244 namespace ARM {
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]245 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]246 }
247
Bob Wilsondd0e2362009-05-20 16:30:25 +0000[diff] [blame]248 //===--------------------------------------------------------------------===//
Dale Johannesen8447d342007-03-20 00:30:56 +0000[diff] [blame]249 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]250
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]251 class ARMTargetLowering : public TargetLowering {
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]252 public:
Dan Gohman5f6a9da52007-08-02 21:21:54 +0000[diff] [blame]253 explicit ARMTargetLowering(TargetMachine &TM);
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]254
Dmitri Gribenko0011bbf2012-11-15 16:51:49 +0000[diff] [blame]255 virtual unsigned getJumpTableEncoding() const;
Jim Grosbach8d3ba732010-07-19 17:20:38 +0000[diff] [blame]256
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]257 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]258
259 /// ReplaceNodeResults - Replace the results of node with an illegal result
260 /// type with new values built out of custom code.
261 ///
262 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]263 SelectionDAG &DAG) const;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]264
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]265 virtual const char *getTargetNodeName(unsigned Opcode) const;
266
Nadav Rotem9d832022012-09-02 12:10:19 +0000[diff] [blame]267 virtual bool isSelectSupported(SelectSupportKind Kind) const {
268 // ARM does not support scalar condition selects on vectors.
269 return (Kind != ScalarCondVectorVal);
270 }
271
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]272 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]273 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]274
Dan Gohman25c16532010-05-01 00:01:06 +0000[diff] [blame]275 virtual MachineBasicBlock *
276 EmitInstrWithCustomInserter(MachineInstr *MI,
277 MachineBasicBlock *MBB) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]278
Evan Chenge6fba772011-08-30 19:09:48 +0000[diff] [blame]279 virtual void
280 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
281
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]282 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Evan Chengd42641c2011-02-02 01:06:55 +0000[diff] [blame]283 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
284
285 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
286
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]287 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
Evan Cheng79e2ca92012-12-10 23:21:26 +0000[diff] [blame]288 /// unaligned memory accesses of the specified type. Returns whether it
289 /// is "fast" by reference in the second argument.
290 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]291
Lang Hames9929c422011-11-02 22:52:45 +0000[diff] [blame]292 virtual EVT getOptimalMemOpType(uint64_t Size,
293 unsigned DstAlign, unsigned SrcAlign,
Evan Cheng962711e2012-12-12 02:34:41 +0000[diff] [blame]294 bool IsMemset, bool ZeroMemset,
Lang Hames9929c422011-11-02 22:52:45 +0000[diff] [blame]295 bool MemcpyStrSrc,
296 MachineFunction &MF) const;
297
Matt Beaumont-Gay4a04c922012-12-06 23:15:36 +0000[diff] [blame]298 using TargetLowering::isZExtFree;
Evan Cheng9ec512d2012-12-06 19:13:27 +0000[diff] [blame]299 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
300
Chris Lattner1eb94d92007-03-30 23:15:24 +0000[diff] [blame]301 /// isLegalAddressingMode - Return true if the addressing mode represented
302 /// by AM is legal for this target, for a load/store of the specified type.
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]303 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
Evan Chengdc49a8d2009-08-14 20:09:37 +0000[diff] [blame]304 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]305
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]306 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]307 /// icmp immediate, that is the target has icmp instructions which can
308 /// compare a register against the immediate without having to materialize
309 /// the immediate into a register.
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]310 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]311
Dan Gohman6136e942011-05-03 00:46:49 +0000[diff] [blame]312 /// isLegalAddImmediate - Return true if the specified immediate is legal
313 /// add immediate, that is the target has add instructions which can
314 /// add a register and the immediate without having to materialize
315 /// the immediate into a register.
316 virtual bool isLegalAddImmediate(int64_t Imm) const;
317
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]318 /// getPreIndexedAddressParts - returns true by value, base pointer and
319 /// offset pointer and addressing mode by reference if the node's address
320 /// can be legally represented as pre-indexed load / store address.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]321 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
322 SDValue &Offset,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]323 ISD::MemIndexedMode &AM,
Dan Gohman02b93132009-01-15 16:29:45 +0000[diff] [blame]324 SelectionDAG &DAG) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]325
326 /// getPostIndexedAddressParts - returns true by value, base pointer and
327 /// offset pointer and addressing mode by reference if this node can be
328 /// combined with a load / store to form a post-indexed load / store.
329 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]330 SDValue &Base, SDValue &Offset,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]331 ISD::MemIndexedMode &AM,
Dan Gohman02b93132009-01-15 16:29:45 +0000[diff] [blame]332 SelectionDAG &DAG) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]333
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]334 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]335 APInt &KnownZero,
Dan Gohmanf990faf2008-02-13 00:35:47 +0000[diff] [blame]336 APInt &KnownOne,
Dan Gohman309d3d52007-06-22 14:59:07 +0000[diff] [blame]337 const SelectionDAG &DAG,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]338 unsigned Depth) const;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]339
340
Evan Cheng078b0b02011-01-08 01:24:27 +0000[diff] [blame]341 virtual bool ExpandInlineAsm(CallInst *CI) const;
342
Chris Lattnerd6855142007-03-25 02:14:49 +0000[diff] [blame]343 ConstraintType getConstraintType(const std::string &Constraint) const;
John Thompsone8360b72010-10-29 17:29:13 +0000[diff] [blame]344
345 /// Examine constraint string and operand type and determine a weight value.
346 /// The operand object must already have been set up with the operand type.
347 ConstraintWeight getSingleConstraintMatchWeight(
348 AsmOperandInfo &info, const char *constraint) const;
349
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]350 std::pair<unsigned, const TargetRegisterClass*>
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]351 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]352 EVT VT) const;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]353
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +0000[diff] [blame]354 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
355 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
356 /// true it means one of the asm constraint of the inline asm instruction
357 /// being processed is 'm'.
358 virtual void LowerAsmOperandForConstraint(SDValue Op,
Eric Christopherde9399b2011-06-02 23:16:42 +0000[diff] [blame]359 std::string &Constraint,
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +0000[diff] [blame]360 std::vector<SDValue> &Ops,
361 SelectionDAG &DAG) const;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]362
Dan Gohman4df9d9c2010-05-11 16:21:03 +0000[diff] [blame]363 const ARMSubtarget* getSubtarget() const {
Dan Gohman544ab2c2008-04-12 04:36:06 +0000[diff] [blame]364 return Subtarget;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]365 }
366
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]367 /// getRegClassFor - Return the register class that should be used for the
368 /// specified value type.
Patrik Hagglund5e6c3612012-12-13 06:34:11 +0000[diff] [blame]369 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]370
Anton Korobeynikov19edda02010-07-24 21:52:08 +0000[diff] [blame]371 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
372 /// be used for loads / stores from the global.
373 virtual unsigned getMaximalGlobalOffset() const;
374
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]375 /// createFastISel - This method returns a target specific FastISel object,
376 /// or null if the target does not support "fast" ISel.
Bob Wilson3e6fa462012-08-03 04:06:28 +0000[diff] [blame]377 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
378 const TargetLibraryInfo *libInfo) const;
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]379
Evan Cheng4401f882010-05-20 23:26:43 +0000[diff] [blame]380 Sched::Preference getSchedulingPreference(SDNode *N) const;
381
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +0000[diff] [blame]382 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov29a44df2009-09-23 19:04:09 +0000[diff] [blame]383 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000[diff] [blame]384
385 /// isFPImmLegal - Returns true if the target can instruction select the
386 /// specified FP immediate natively. If false, the legalizer will
387 /// materialize the FP immediate as a load from a constant pool.
388 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
389
Bob Wilson5549d492010-09-21 17:56:22 +0000[diff] [blame]390 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
391 const CallInst &I,
392 unsigned Intrinsic) const;
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]393 protected:
Evan Chenga77f3d32010-07-21 06:09:07 +0000[diff] [blame]394 std::pair<const TargetRegisterClass*, uint8_t>
Patrik Hagglundf9eb1682012-12-19 11:30:36 +0000[diff] [blame]395 findRepresentativeClass(MVT VT) const;
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]396
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]397 private:
398 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
399 /// make the right decision when generating code for different targets.
400 const ARMSubtarget *Subtarget;
401
Evan Chengdf907f42010-07-23 22:39:59 +0000[diff] [blame]402 const TargetRegisterInfo *RegInfo;
403
Evan Chengbf407072010-09-10 01:29:16 +0000[diff] [blame]404 const InstrItineraryData *Itins;
405
Bob Wilson844d6c82009-07-13 18:11:36 +0000[diff] [blame]406 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]407 ///
408 unsigned ARMPCLabelIndex;
409
Craig Topper4fa625f2012-08-12 03:16:37 +0000[diff] [blame]410 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
411 void addDRTypeForNEON(MVT VT);
412 void addQRTypeForNEON(MVT VT);
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]413
414 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]415 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]416 SDValue Chain, SDValue &Arg,
417 RegsToPassVector &RegsToPass,
418 CCValAssign &VA, CCValAssign &NextVA,
419 SDValue &StackPtr,
420 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]421 ISD::ArgFlagsTy Flags) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]422 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]423 SDValue &Root, SelectionDAG &DAG,
424 DebugLoc dl) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]425
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]426 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
427 bool isVarArg) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]428 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
429 DebugLoc dl, SelectionDAG &DAG,
430 const CCValAssign &VA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]431 ISD::ArgFlagsTy Flags) const;
Jim Grosbachc98892f2010-05-26 20:22:18 +0000[diff] [blame]432 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbachbd9485d2010-05-22 01:06:18 +0000[diff] [blame]433 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha570d052010-02-08 23:22:00 +0000[diff] [blame]434 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]435 const ARMSubtarget *Subtarget) const;
436 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
438 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
439 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]440 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]441 SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]442 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgaea41202012-05-04 09:40:39 +0000[diff] [blame]443 SelectionDAG &DAG,
444 TLSModel::Model model) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]445 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
446 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Bill Wendling6a981312010-08-11 08:43:16 +0000[diff] [blame]447 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]448 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
449 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng25f93642010-07-08 02:08:50 +0000[diff] [blame]450 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng168ced92010-05-22 01:47:14 +0000[diff] [blame]451 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]452 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]453 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
454 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemanb69b1822010-08-03 21:31:55 +0000[diff] [blame]455 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hamesc35ee8b2012-03-15 18:49:02 +0000[diff] [blame]456 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
457 const ARMSubtarget *ST) const;
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]458 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]459 const ARMSubtarget *ST) const;
460
461 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola18a831d2007-10-19 14:35:17 +0000[diff] [blame]462
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]463 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]464 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]465 const SmallVectorImpl<ISD::InputArg> &Ins,
466 DebugLoc dl, SelectionDAG &DAG,
Stephen Linb8bd2322013-04-20 05:14:40 +0000[diff] [blame]467 SmallVectorImpl<SDValue> &InVals,
468 bool isThisReturn, SDValue ThisVal) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]469
470 virtual SDValue
471 LowerFormalArguments(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]472 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]473 const SmallVectorImpl<ISD::InputArg> &Ins,
474 DebugLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]475 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]476
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]477 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
478 DebugLoc dl, SDValue &Chain,
479 const Value *OrigArg,
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +0000[diff] [blame]480 unsigned InRegsParamRecordIdx,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]481 unsigned OffsetFromOrigArg,
482 unsigned ArgOffset,
483 bool ForceMutable) const;
484
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]485 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
Stepan Dyatkovskiyf13dbb82012-10-10 11:37:36 +0000[diff] [blame]486 DebugLoc dl, SDValue &Chain,
Stepan Dyatkovskiydab80432012-10-19 08:23:06 +0000[diff] [blame]487 unsigned ArgOffset,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]488 bool ForceMutable = false) const;
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]489
490 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +0000[diff] [blame]491 unsigned InRegsParamRecordIdx,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]492 unsigned &ArgRegsSize,
493 unsigned &ArgRegsSaveSize) const;
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]494
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]495 virtual SDValue
Justin Holewinskiaa583972012-05-25 16:35:28 +0000[diff] [blame]496 LowerCall(TargetLowering::CallLoweringInfo &CLI,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]497 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]498
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]499 /// HandleByVal - Target-specific cleanup for ByVal support.
Stepan Dyatkovskiye59a9202012-10-16 07:16:47 +0000[diff] [blame]500 virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]501
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]502 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
503 /// for tail call optimization. Targets which want to do tail call
504 /// optimization should implement this function.
505 bool IsEligibleForTailCallOptimization(SDValue Callee,
506 CallingConv::ID CalleeCC,
507 bool isVarArg,
508 bool isCalleeStructRet,
509 bool isCallerStructRet,
510 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]511 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]512 const SmallVectorImpl<ISD::InputArg> &Ins,
513 SelectionDAG& DAG) const;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000[diff] [blame]514
515 virtual bool CanLowerReturn(CallingConv::ID CallConv,
516 MachineFunction &MF, bool isVarArg,
517 const SmallVectorImpl<ISD::OutputArg> &Outs,
518 LLVMContext &Context) const;
519
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]520 virtual SDValue
521 LowerReturn(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]522 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]523 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]524 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]525 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]526
Evan Chengf8bad082012-04-10 01:51:00 +0000[diff] [blame]527 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
Evan Chengd4b08732010-11-30 23:55:39 +0000[diff] [blame]528
Evan Cheng0663f232011-03-21 01:19:09 +0000[diff] [blame]529 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
530
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]531 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]532 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
533 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
534 SelectionDAG &DAG, DebugLoc dl) const;
Bob Wilson45acbd02011-03-08 01:17:20 +0000[diff] [blame]535 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]536
537 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000[diff] [blame]538
Jim Grosbach8f9a3ac2009-12-12 01:40:06 +0000[diff] [blame]539 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
540 MachineBasicBlock *BB,
541 unsigned Size) const;
542 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
543 MachineBasicBlock *BB,
544 unsigned Size,
545 unsigned BinOpcode) const;
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]546 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
547 MachineBasicBlock *BB,
548 unsigned Op1,
549 unsigned Op2,
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]550 bool NeedsCarry = false,
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]551 bool IsCmpxchg = false,
552 bool IsMinMax = false,
553 ARMCC::CondCodes CC = ARMCC::AL) const;
Jim Grosbachd4b733e2011-04-26 19:44:18 +0000[diff] [blame]554 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
555 MachineBasicBlock *BB,
556 unsigned Size,
557 bool signExtend,
558 ARMCC::CondCodes Cond) const;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000[diff] [blame]559
Bill Wendling030b58e2011-10-06 22:18:16 +0000[diff] [blame]560 void SetupEntryBlockForSjLj(MachineInstr *MI,
561 MachineBasicBlock *MBB,
562 MachineBasicBlock *DispatchBB, int FI) const;
563
Bill Wendling374ee192011-10-03 21:25:38 +0000[diff] [blame]564 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
565 MachineBasicBlock *MBB) const;
566
Andrew Trick0ed57782011-04-23 03:55:32 +0000[diff] [blame]567 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Manman Rene8735522012-06-01 19:33:18 +0000[diff] [blame]568
569 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
570 MachineBasicBlock *MBB) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]571 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]572
Owen Andersona4076922010-11-05 21:57:54 +0000[diff] [blame]573 enum NEONModImmType {
574 VMOVModImm,
575 VMVNModImm,
576 OtherModImm
577 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]578
579
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]580 namespace ARM {
Bob Wilson3e6fa462012-08-03 04:06:28 +0000[diff] [blame]581 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
582 const TargetLibraryInfo *libInfo);
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]583 }
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]584}
585
586#endif // ARMISELLOWERING_H