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gerrit-public.fairphone.software / toolchain / llvm-project / d7bae451de6df3e925efccc2abaeb2df9d402529 / . / llvm / lib / Target / X86 / InstPrinter / X86InstComments.cpp
blob: db981edb27b2fe94590bc21f738b4a6e8086cc1b [file] [log] [blame]
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This defines functionality used to emit comments about X86 instructions to
11// an output stream for -fverbose-asm.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86InstComments.h"
16#include "MCTargetDesc/X86MCTargetDesc.h"
17#include "Utils/X86ShuffleDecode.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/CodeGen/MachineValueType.h"
20#include "llvm/Support/raw_ostream.h"
21
22using namespace llvm;
23
24/// \brief Extracts the src/dst types for a given zero extension instruction.
25/// \note While the number of elements in DstVT type correct, the
26/// number in the SrcVT type is expanded to fill the src xmm register and the
27/// upper elements may not be included in the dst xmm/ymm register.
28static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
29 switch (MI->getOpcode()) {
30 default:
31 llvm_unreachable("Unknown zero extension instruction");
32 // i8 zero extension
33 case X86::PMOVZXBWrm:
34 case X86::PMOVZXBWrr:
35 case X86::VPMOVZXBWrm:
36 case X86::VPMOVZXBWrr:
37 SrcVT = MVT::v16i8;
38 DstVT = MVT::v8i16;
39 break;
40 case X86::VPMOVZXBWYrm:
41 case X86::VPMOVZXBWYrr:
42 SrcVT = MVT::v16i8;
43 DstVT = MVT::v16i16;
44 break;
45 case X86::PMOVZXBDrm:
46 case X86::PMOVZXBDrr:
47 case X86::VPMOVZXBDrm:
48 case X86::VPMOVZXBDrr:
49 SrcVT = MVT::v16i8;
50 DstVT = MVT::v4i32;
51 break;
52 case X86::VPMOVZXBDYrm:
53 case X86::VPMOVZXBDYrr:
54 SrcVT = MVT::v16i8;
55 DstVT = MVT::v8i32;
56 break;
57 case X86::PMOVZXBQrm:
58 case X86::PMOVZXBQrr:
59 case X86::VPMOVZXBQrm:
60 case X86::VPMOVZXBQrr:
61 SrcVT = MVT::v16i8;
62 DstVT = MVT::v2i64;
63 break;
64 case X86::VPMOVZXBQYrm:
65 case X86::VPMOVZXBQYrr:
66 SrcVT = MVT::v16i8;
67 DstVT = MVT::v4i64;
68 break;
69 // i16 zero extension
70 case X86::PMOVZXWDrm:
71 case X86::PMOVZXWDrr:
72 case X86::VPMOVZXWDrm:
73 case X86::VPMOVZXWDrr:
74 SrcVT = MVT::v8i16;
75 DstVT = MVT::v4i32;
76 break;
77 case X86::VPMOVZXWDYrm:
78 case X86::VPMOVZXWDYrr:
79 SrcVT = MVT::v8i16;
80 DstVT = MVT::v8i32;
81 break;
82 case X86::PMOVZXWQrm:
83 case X86::PMOVZXWQrr:
84 case X86::VPMOVZXWQrm:
85 case X86::VPMOVZXWQrr:
86 SrcVT = MVT::v8i16;
87 DstVT = MVT::v2i64;
88 break;
89 case X86::VPMOVZXWQYrm:
90 case X86::VPMOVZXWQYrr:
91 SrcVT = MVT::v8i16;
92 DstVT = MVT::v4i64;
93 break;
94 // i32 zero extension
95 case X86::PMOVZXDQrm:
96 case X86::PMOVZXDQrr:
97 case X86::VPMOVZXDQrm:
98 case X86::VPMOVZXDQrr:
99 SrcVT = MVT::v4i32;
100 DstVT = MVT::v2i64;
101 break;
102 case X86::VPMOVZXDQYrm:
103 case X86::VPMOVZXDQYrr:
104 SrcVT = MVT::v4i32;
105 DstVT = MVT::v4i64;
106 break;
107 }
108}
109
Igor Bregerd7bae452015-10-15 13:29:07 +0000[diff] [blame^]110#define CASE_VSHUF_COMMON(Inst, Suffix, src2) \
111 case X86::VSHUFF##Inst##Suffix##r##src2##i: \
112 case X86::VSHUFF##Inst##Suffix##r##src2##ik: \
113 case X86::VSHUFF##Inst##Suffix##r##src2##ikz: \
114 case X86::VSHUFI##Inst##Suffix##r##src2##i: \
115 case X86::VSHUFI##Inst##Suffix##r##src2##ik: \
116 case X86::VSHUFI##Inst##Suffix##r##src2##ikz:
117
118#define CASE_VSHUF(Inst) \
119 CASE_VSHUF_COMMON(Inst, Z, r) \
120 CASE_VSHUF_COMMON(Inst, Z, m) \
121 CASE_VSHUF_COMMON(Inst, Z256, r) \
122 CASE_VSHUF_COMMON(Inst, Z256, m) \
123
124/// \brief Extracts the types and if it has memory operand for a given
125/// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
126static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
127 HasMemOp = false;
128 switch (MI->getOpcode()) {
129 default:
130 llvm_unreachable("Unknown VSHUF64x2 family instructions.");
131 break;
132 CASE_VSHUF_COMMON(64X2, Z, m)
133 HasMemOp = true; // FALL THROUGH.
134 CASE_VSHUF_COMMON(64X2, Z, r)
135 VT = MVT::v8i64;
136 break;
137 CASE_VSHUF_COMMON(64X2, Z256, m)
138 HasMemOp = true; // FALL THROUGH.
139 CASE_VSHUF_COMMON(64X2, Z256, r)
140 VT = MVT::v4i64;
141 break;
142 CASE_VSHUF_COMMON(32X4, Z, m)
143 HasMemOp = true; // FALL THROUGH.
144 CASE_VSHUF_COMMON(32X4, Z, r)
145 VT = MVT::v16i32;
146 break;
147 CASE_VSHUF_COMMON(32X4, Z256, m)
148 HasMemOp = true; // FALL THROUGH.
149 CASE_VSHUF_COMMON(32X4, Z256, r)
150 VT = MVT::v8i32;
151 break;
152 }
153}
154
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]155//===----------------------------------------------------------------------===//
156// Top Level Entrypoint
157//===----------------------------------------------------------------------===//
158
159/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
160/// newline terminated strings to the specified string if desired. This
161/// information is shown in disassembly dumps when verbose assembly is enabled.
162bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
163 const char *(*getRegName)(unsigned)) {
164 // If this is a shuffle operation, the switch should fill in this state.
165 SmallVector<int, 8> ShuffleMask;
166 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
167
168 switch (MI->getOpcode()) {
169 default:
170 // Not an instruction for which we can decode comments.
171 return false;
172
173 case X86::BLENDPDrri:
174 case X86::VBLENDPDrri:
175 Src2Name = getRegName(MI->getOperand(2).getReg());
176 // FALL THROUGH.
177 case X86::BLENDPDrmi:
178 case X86::VBLENDPDrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]179 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]180 DecodeBLENDMask(MVT::v2f64,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]181 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]182 ShuffleMask);
183 Src1Name = getRegName(MI->getOperand(1).getReg());
184 DestName = getRegName(MI->getOperand(0).getReg());
185 break;
186 case X86::VBLENDPDYrri:
187 Src2Name = getRegName(MI->getOperand(2).getReg());
188 // FALL THROUGH.
189 case X86::VBLENDPDYrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]190 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]191 DecodeBLENDMask(MVT::v4f64,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]192 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]193 ShuffleMask);
194 Src1Name = getRegName(MI->getOperand(1).getReg());
195 DestName = getRegName(MI->getOperand(0).getReg());
196 break;
197
198 case X86::BLENDPSrri:
199 case X86::VBLENDPSrri:
200 Src2Name = getRegName(MI->getOperand(2).getReg());
201 // FALL THROUGH.
202 case X86::BLENDPSrmi:
203 case X86::VBLENDPSrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]204 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]205 DecodeBLENDMask(MVT::v4f32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]206 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]207 ShuffleMask);
208 Src1Name = getRegName(MI->getOperand(1).getReg());
209 DestName = getRegName(MI->getOperand(0).getReg());
210 break;
211 case X86::VBLENDPSYrri:
212 Src2Name = getRegName(MI->getOperand(2).getReg());
213 // FALL THROUGH.
214 case X86::VBLENDPSYrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]215 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]216 DecodeBLENDMask(MVT::v8f32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]217 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]218 ShuffleMask);
219 Src1Name = getRegName(MI->getOperand(1).getReg());
220 DestName = getRegName(MI->getOperand(0).getReg());
221 break;
222
223 case X86::PBLENDWrri:
224 case X86::VPBLENDWrri:
225 Src2Name = getRegName(MI->getOperand(2).getReg());
226 // FALL THROUGH.
227 case X86::PBLENDWrmi:
228 case X86::VPBLENDWrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]229 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]230 DecodeBLENDMask(MVT::v8i16,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]231 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]232 ShuffleMask);
233 Src1Name = getRegName(MI->getOperand(1).getReg());
234 DestName = getRegName(MI->getOperand(0).getReg());
235 break;
236 case X86::VPBLENDWYrri:
237 Src2Name = getRegName(MI->getOperand(2).getReg());
238 // FALL THROUGH.
239 case X86::VPBLENDWYrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]240 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]241 DecodeBLENDMask(MVT::v16i16,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]242 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]243 ShuffleMask);
244 Src1Name = getRegName(MI->getOperand(1).getReg());
245 DestName = getRegName(MI->getOperand(0).getReg());
246 break;
247
248 case X86::VPBLENDDrri:
249 Src2Name = getRegName(MI->getOperand(2).getReg());
250 // FALL THROUGH.
251 case X86::VPBLENDDrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]252 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]253 DecodeBLENDMask(MVT::v4i32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]254 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]255 ShuffleMask);
256 Src1Name = getRegName(MI->getOperand(1).getReg());
257 DestName = getRegName(MI->getOperand(0).getReg());
258 break;
259
260 case X86::VPBLENDDYrri:
261 Src2Name = getRegName(MI->getOperand(2).getReg());
262 // FALL THROUGH.
263 case X86::VPBLENDDYrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]264 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]265 DecodeBLENDMask(MVT::v8i32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]266 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]267 ShuffleMask);
268 Src1Name = getRegName(MI->getOperand(1).getReg());
269 DestName = getRegName(MI->getOperand(0).getReg());
270 break;
271
272 case X86::INSERTPSrr:
273 case X86::VINSERTPSrr:
274 Src2Name = getRegName(MI->getOperand(2).getReg());
275 // FALL THROUGH.
276 case X86::INSERTPSrm:
277 case X86::VINSERTPSrm:
278 DestName = getRegName(MI->getOperand(0).getReg());
279 Src1Name = getRegName(MI->getOperand(1).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]280 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
281 DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]282 ShuffleMask);
283 break;
284
285 case X86::MOVLHPSrr:
286 case X86::VMOVLHPSrr:
287 Src2Name = getRegName(MI->getOperand(2).getReg());
288 Src1Name = getRegName(MI->getOperand(1).getReg());
289 DestName = getRegName(MI->getOperand(0).getReg());
290 DecodeMOVLHPSMask(2, ShuffleMask);
291 break;
292
293 case X86::MOVHLPSrr:
294 case X86::VMOVHLPSrr:
295 Src2Name = getRegName(MI->getOperand(2).getReg());
296 Src1Name = getRegName(MI->getOperand(1).getReg());
297 DestName = getRegName(MI->getOperand(0).getReg());
298 DecodeMOVHLPSMask(2, ShuffleMask);
299 break;
300
301 case X86::MOVSLDUPrr:
302 case X86::VMOVSLDUPrr:
303 Src1Name = getRegName(MI->getOperand(1).getReg());
304 // FALL THROUGH.
305 case X86::MOVSLDUPrm:
306 case X86::VMOVSLDUPrm:
307 DestName = getRegName(MI->getOperand(0).getReg());
308 DecodeMOVSLDUPMask(MVT::v4f32, ShuffleMask);
309 break;
310
311 case X86::VMOVSHDUPYrr:
312 Src1Name = getRegName(MI->getOperand(1).getReg());
313 // FALL THROUGH.
314 case X86::VMOVSHDUPYrm:
315 DestName = getRegName(MI->getOperand(0).getReg());
316 DecodeMOVSHDUPMask(MVT::v8f32, ShuffleMask);
317 break;
318
319 case X86::VMOVSLDUPYrr:
320 Src1Name = getRegName(MI->getOperand(1).getReg());
321 // FALL THROUGH.
322 case X86::VMOVSLDUPYrm:
323 DestName = getRegName(MI->getOperand(0).getReg());
324 DecodeMOVSLDUPMask(MVT::v8f32, ShuffleMask);
325 break;
326
327 case X86::MOVSHDUPrr:
328 case X86::VMOVSHDUPrr:
329 Src1Name = getRegName(MI->getOperand(1).getReg());
330 // FALL THROUGH.
331 case X86::MOVSHDUPrm:
332 case X86::VMOVSHDUPrm:
333 DestName = getRegName(MI->getOperand(0).getReg());
334 DecodeMOVSHDUPMask(MVT::v4f32, ShuffleMask);
335 break;
336
337 case X86::VMOVDDUPYrr:
338 Src1Name = getRegName(MI->getOperand(1).getReg());
339 // FALL THROUGH.
340 case X86::VMOVDDUPYrm:
341 DestName = getRegName(MI->getOperand(0).getReg());
342 DecodeMOVDDUPMask(MVT::v4f64, ShuffleMask);
343 break;
344
345 case X86::MOVDDUPrr:
346 case X86::VMOVDDUPrr:
347 Src1Name = getRegName(MI->getOperand(1).getReg());
348 // FALL THROUGH.
349 case X86::MOVDDUPrm:
350 case X86::VMOVDDUPrm:
351 DestName = getRegName(MI->getOperand(0).getReg());
352 DecodeMOVDDUPMask(MVT::v2f64, ShuffleMask);
353 break;
354
355 case X86::PSLLDQri:
356 case X86::VPSLLDQri:
357 Src1Name = getRegName(MI->getOperand(1).getReg());
358 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]359 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]360 DecodePSLLDQMask(MVT::v16i8,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]361 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]362 ShuffleMask);
363 break;
364
365 case X86::VPSLLDQYri:
366 Src1Name = getRegName(MI->getOperand(1).getReg());
367 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]368 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]369 DecodePSLLDQMask(MVT::v32i8,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]370 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]371 ShuffleMask);
372 break;
373
374 case X86::PSRLDQri:
375 case X86::VPSRLDQri:
376 Src1Name = getRegName(MI->getOperand(1).getReg());
377 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]378 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]379 DecodePSRLDQMask(MVT::v16i8,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]380 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]381 ShuffleMask);
382 break;
383
384 case X86::VPSRLDQYri:
385 Src1Name = getRegName(MI->getOperand(1).getReg());
386 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]387 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]388 DecodePSRLDQMask(MVT::v32i8,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]389 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]390 ShuffleMask);
391 break;
392
393 case X86::PALIGNR128rr:
394 case X86::VPALIGNR128rr:
395 Src1Name = getRegName(MI->getOperand(2).getReg());
396 // FALL THROUGH.
397 case X86::PALIGNR128rm:
398 case X86::VPALIGNR128rm:
399 Src2Name = getRegName(MI->getOperand(1).getReg());
400 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]401 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]402 DecodePALIGNRMask(MVT::v16i8,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]403 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]404 ShuffleMask);
405 break;
406 case X86::VPALIGNR256rr:
407 Src1Name = getRegName(MI->getOperand(2).getReg());
408 // FALL THROUGH.
409 case X86::VPALIGNR256rm:
410 Src2Name = getRegName(MI->getOperand(1).getReg());
411 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]412 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]413 DecodePALIGNRMask(MVT::v32i8,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]414 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]415 ShuffleMask);
416 break;
417
418 case X86::PSHUFDri:
419 case X86::VPSHUFDri:
420 Src1Name = getRegName(MI->getOperand(1).getReg());
421 // FALL THROUGH.
422 case X86::PSHUFDmi:
423 case X86::VPSHUFDmi:
424 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]425 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]426 DecodePSHUFMask(MVT::v4i32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]427 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]428 ShuffleMask);
429 break;
430 case X86::VPSHUFDYri:
431 Src1Name = getRegName(MI->getOperand(1).getReg());
432 // FALL THROUGH.
433 case X86::VPSHUFDYmi:
434 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]435 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]436 DecodePSHUFMask(MVT::v8i32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]437 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]438 ShuffleMask);
439 break;
440
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]441 case X86::PSHUFHWri:
442 case X86::VPSHUFHWri:
443 Src1Name = getRegName(MI->getOperand(1).getReg());
444 // FALL THROUGH.
445 case X86::PSHUFHWmi:
446 case X86::VPSHUFHWmi:
447 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]448 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]449 DecodePSHUFHWMask(MVT::v8i16,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]450 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]451 ShuffleMask);
452 break;
453 case X86::VPSHUFHWYri:
454 Src1Name = getRegName(MI->getOperand(1).getReg());
455 // FALL THROUGH.
456 case X86::VPSHUFHWYmi:
457 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]458 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]459 DecodePSHUFHWMask(MVT::v16i16,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]460 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]461 ShuffleMask);
462 break;
463 case X86::PSHUFLWri:
464 case X86::VPSHUFLWri:
465 Src1Name = getRegName(MI->getOperand(1).getReg());
466 // FALL THROUGH.
467 case X86::PSHUFLWmi:
468 case X86::VPSHUFLWmi:
469 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]470 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]471 DecodePSHUFLWMask(MVT::v8i16,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]472 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]473 ShuffleMask);
474 break;
475 case X86::VPSHUFLWYri:
476 Src1Name = getRegName(MI->getOperand(1).getReg());
477 // FALL THROUGH.
478 case X86::VPSHUFLWYmi:
479 DestName = getRegName(MI->getOperand(0).getReg());
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]480 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]481 DecodePSHUFLWMask(MVT::v16i16,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]482 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]483 ShuffleMask);
484 break;
485
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]486 case X86::MMX_PSHUFWri:
487 Src1Name = getRegName(MI->getOperand(1).getReg());
488 // FALL THROUGH.
489 case X86::MMX_PSHUFWmi:
490 DestName = getRegName(MI->getOperand(0).getReg());
491 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
492 DecodePSHUFMask(MVT::v4i16,
493 MI->getOperand(MI->getNumOperands() - 1).getImm(),
494 ShuffleMask);
495 break;
496
497 case X86::PSWAPDrr:
498 Src1Name = getRegName(MI->getOperand(1).getReg());
499 // FALL THROUGH.
500 case X86::PSWAPDrm:
501 DestName = getRegName(MI->getOperand(0).getReg());
502 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
503 break;
504
505 case X86::MMX_PUNPCKHBWirr:
506 Src2Name = getRegName(MI->getOperand(2).getReg());
507 case X86::MMX_PUNPCKHBWirm:
508 Src1Name = getRegName(MI->getOperand(1).getReg());
509 DestName = getRegName(MI->getOperand(0).getReg());
510 DecodeUNPCKHMask(MVT::v8i8, ShuffleMask);
511 break;
512 case X86::MMX_PUNPCKHWDirr:
513 Src2Name = getRegName(MI->getOperand(2).getReg());
514 case X86::MMX_PUNPCKHWDirm:
515 Src1Name = getRegName(MI->getOperand(1).getReg());
516 DestName = getRegName(MI->getOperand(0).getReg());
517 DecodeUNPCKHMask(MVT::v4i16, ShuffleMask);
518 break;
519 case X86::MMX_PUNPCKHDQirr:
520 Src2Name = getRegName(MI->getOperand(2).getReg());
521 case X86::MMX_PUNPCKHDQirm:
522 Src1Name = getRegName(MI->getOperand(1).getReg());
523 DestName = getRegName(MI->getOperand(0).getReg());
524 DecodeUNPCKHMask(MVT::v2i32, ShuffleMask);
525 break;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]526 case X86::PUNPCKHBWrr:
527 case X86::VPUNPCKHBWrr:
528 Src2Name = getRegName(MI->getOperand(2).getReg());
529 // FALL THROUGH.
530 case X86::PUNPCKHBWrm:
531 case X86::VPUNPCKHBWrm:
532 Src1Name = getRegName(MI->getOperand(1).getReg());
533 DestName = getRegName(MI->getOperand(0).getReg());
534 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask);
535 break;
536 case X86::VPUNPCKHBWYrr:
537 Src2Name = getRegName(MI->getOperand(2).getReg());
538 // FALL THROUGH.
539 case X86::VPUNPCKHBWYrm:
540 Src1Name = getRegName(MI->getOperand(1).getReg());
541 DestName = getRegName(MI->getOperand(0).getReg());
542 DecodeUNPCKHMask(MVT::v32i8, ShuffleMask);
543 break;
544 case X86::PUNPCKHWDrr:
545 case X86::VPUNPCKHWDrr:
546 Src2Name = getRegName(MI->getOperand(2).getReg());
547 // FALL THROUGH.
548 case X86::PUNPCKHWDrm:
549 case X86::VPUNPCKHWDrm:
550 Src1Name = getRegName(MI->getOperand(1).getReg());
551 DestName = getRegName(MI->getOperand(0).getReg());
552 DecodeUNPCKHMask(MVT::v8i16, ShuffleMask);
553 break;
554 case X86::VPUNPCKHWDYrr:
555 Src2Name = getRegName(MI->getOperand(2).getReg());
556 // FALL THROUGH.
557 case X86::VPUNPCKHWDYrm:
558 Src1Name = getRegName(MI->getOperand(1).getReg());
559 DestName = getRegName(MI->getOperand(0).getReg());
560 DecodeUNPCKHMask(MVT::v16i16, ShuffleMask);
561 break;
562 case X86::PUNPCKHDQrr:
563 case X86::VPUNPCKHDQrr:
564 Src2Name = getRegName(MI->getOperand(2).getReg());
565 // FALL THROUGH.
566 case X86::PUNPCKHDQrm:
567 case X86::VPUNPCKHDQrm:
568 Src1Name = getRegName(MI->getOperand(1).getReg());
569 DestName = getRegName(MI->getOperand(0).getReg());
570 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
571 break;
572 case X86::VPUNPCKHDQYrr:
573 Src2Name = getRegName(MI->getOperand(2).getReg());
574 // FALL THROUGH.
575 case X86::VPUNPCKHDQYrm:
576 Src1Name = getRegName(MI->getOperand(1).getReg());
577 DestName = getRegName(MI->getOperand(0).getReg());
578 DecodeUNPCKHMask(MVT::v8i32, ShuffleMask);
579 break;
580 case X86::VPUNPCKHDQZrr:
581 Src2Name = getRegName(MI->getOperand(2).getReg());
582 // FALL THROUGH.
583 case X86::VPUNPCKHDQZrm:
584 Src1Name = getRegName(MI->getOperand(1).getReg());
585 DestName = getRegName(MI->getOperand(0).getReg());
586 DecodeUNPCKHMask(MVT::v16i32, ShuffleMask);
587 break;
588 case X86::PUNPCKHQDQrr:
589 case X86::VPUNPCKHQDQrr:
590 Src2Name = getRegName(MI->getOperand(2).getReg());
591 // FALL THROUGH.
592 case X86::PUNPCKHQDQrm:
593 case X86::VPUNPCKHQDQrm:
594 Src1Name = getRegName(MI->getOperand(1).getReg());
595 DestName = getRegName(MI->getOperand(0).getReg());
596 DecodeUNPCKHMask(MVT::v2i64, ShuffleMask);
597 break;
598 case X86::VPUNPCKHQDQYrr:
599 Src2Name = getRegName(MI->getOperand(2).getReg());
600 // FALL THROUGH.
601 case X86::VPUNPCKHQDQYrm:
602 Src1Name = getRegName(MI->getOperand(1).getReg());
603 DestName = getRegName(MI->getOperand(0).getReg());
604 DecodeUNPCKHMask(MVT::v4i64, ShuffleMask);
605 break;
606 case X86::VPUNPCKHQDQZrr:
607 Src2Name = getRegName(MI->getOperand(2).getReg());
608 // FALL THROUGH.
609 case X86::VPUNPCKHQDQZrm:
610 Src1Name = getRegName(MI->getOperand(1).getReg());
611 DestName = getRegName(MI->getOperand(0).getReg());
612 DecodeUNPCKHMask(MVT::v8i64, ShuffleMask);
613 break;
614
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]615 case X86::MMX_PUNPCKLBWirr:
616 Src2Name = getRegName(MI->getOperand(2).getReg());
617 case X86::MMX_PUNPCKLBWirm:
618 Src1Name = getRegName(MI->getOperand(1).getReg());
619 DestName = getRegName(MI->getOperand(0).getReg());
620 DecodeUNPCKLMask(MVT::v8i8, ShuffleMask);
621 break;
622 case X86::MMX_PUNPCKLWDirr:
623 Src2Name = getRegName(MI->getOperand(2).getReg());
624 case X86::MMX_PUNPCKLWDirm:
625 Src1Name = getRegName(MI->getOperand(1).getReg());
626 DestName = getRegName(MI->getOperand(0).getReg());
627 DecodeUNPCKLMask(MVT::v4i16, ShuffleMask);
628 break;
629 case X86::MMX_PUNPCKLDQirr:
630 Src2Name = getRegName(MI->getOperand(2).getReg());
631 case X86::MMX_PUNPCKLDQirm:
632 Src1Name = getRegName(MI->getOperand(1).getReg());
633 DestName = getRegName(MI->getOperand(0).getReg());
634 DecodeUNPCKLMask(MVT::v2i32, ShuffleMask);
635 break;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]636 case X86::PUNPCKLBWrr:
637 case X86::VPUNPCKLBWrr:
638 Src2Name = getRegName(MI->getOperand(2).getReg());
639 // FALL THROUGH.
640 case X86::PUNPCKLBWrm:
641 case X86::VPUNPCKLBWrm:
642 Src1Name = getRegName(MI->getOperand(1).getReg());
643 DestName = getRegName(MI->getOperand(0).getReg());
644 DecodeUNPCKLMask(MVT::v16i8, ShuffleMask);
645 break;
646 case X86::VPUNPCKLBWYrr:
647 Src2Name = getRegName(MI->getOperand(2).getReg());
648 // FALL THROUGH.
649 case X86::VPUNPCKLBWYrm:
650 Src1Name = getRegName(MI->getOperand(1).getReg());
651 DestName = getRegName(MI->getOperand(0).getReg());
652 DecodeUNPCKLMask(MVT::v32i8, ShuffleMask);
653 break;
654 case X86::PUNPCKLWDrr:
655 case X86::VPUNPCKLWDrr:
656 Src2Name = getRegName(MI->getOperand(2).getReg());
657 // FALL THROUGH.
658 case X86::PUNPCKLWDrm:
659 case X86::VPUNPCKLWDrm:
660 Src1Name = getRegName(MI->getOperand(1).getReg());
661 DestName = getRegName(MI->getOperand(0).getReg());
662 DecodeUNPCKLMask(MVT::v8i16, ShuffleMask);
663 break;
664 case X86::VPUNPCKLWDYrr:
665 Src2Name = getRegName(MI->getOperand(2).getReg());
666 // FALL THROUGH.
667 case X86::VPUNPCKLWDYrm:
668 Src1Name = getRegName(MI->getOperand(1).getReg());
669 DestName = getRegName(MI->getOperand(0).getReg());
670 DecodeUNPCKLMask(MVT::v16i16, ShuffleMask);
671 break;
672 case X86::PUNPCKLDQrr:
673 case X86::VPUNPCKLDQrr:
674 Src2Name = getRegName(MI->getOperand(2).getReg());
675 // FALL THROUGH.
676 case X86::PUNPCKLDQrm:
677 case X86::VPUNPCKLDQrm:
678 Src1Name = getRegName(MI->getOperand(1).getReg());
679 DestName = getRegName(MI->getOperand(0).getReg());
680 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
681 break;
682 case X86::VPUNPCKLDQYrr:
683 Src2Name = getRegName(MI->getOperand(2).getReg());
684 // FALL THROUGH.
685 case X86::VPUNPCKLDQYrm:
686 Src1Name = getRegName(MI->getOperand(1).getReg());
687 DestName = getRegName(MI->getOperand(0).getReg());
688 DecodeUNPCKLMask(MVT::v8i32, ShuffleMask);
689 break;
690 case X86::VPUNPCKLDQZrr:
691 Src2Name = getRegName(MI->getOperand(2).getReg());
692 // FALL THROUGH.
693 case X86::VPUNPCKLDQZrm:
694 Src1Name = getRegName(MI->getOperand(1).getReg());
695 DestName = getRegName(MI->getOperand(0).getReg());
696 DecodeUNPCKLMask(MVT::v16i32, ShuffleMask);
697 break;
698 case X86::PUNPCKLQDQrr:
699 case X86::VPUNPCKLQDQrr:
700 Src2Name = getRegName(MI->getOperand(2).getReg());
701 // FALL THROUGH.
702 case X86::PUNPCKLQDQrm:
703 case X86::VPUNPCKLQDQrm:
704 Src1Name = getRegName(MI->getOperand(1).getReg());
705 DestName = getRegName(MI->getOperand(0).getReg());
706 DecodeUNPCKLMask(MVT::v2i64, ShuffleMask);
707 break;
708 case X86::VPUNPCKLQDQYrr:
709 Src2Name = getRegName(MI->getOperand(2).getReg());
710 // FALL THROUGH.
711 case X86::VPUNPCKLQDQYrm:
712 Src1Name = getRegName(MI->getOperand(1).getReg());
713 DestName = getRegName(MI->getOperand(0).getReg());
714 DecodeUNPCKLMask(MVT::v4i64, ShuffleMask);
715 break;
716 case X86::VPUNPCKLQDQZrr:
717 Src2Name = getRegName(MI->getOperand(2).getReg());
718 // FALL THROUGH.
719 case X86::VPUNPCKLQDQZrm:
720 Src1Name = getRegName(MI->getOperand(1).getReg());
721 DestName = getRegName(MI->getOperand(0).getReg());
722 DecodeUNPCKLMask(MVT::v8i64, ShuffleMask);
723 break;
724
725 case X86::SHUFPDrri:
726 case X86::VSHUFPDrri:
727 Src2Name = getRegName(MI->getOperand(2).getReg());
728 // FALL THROUGH.
729 case X86::SHUFPDrmi:
730 case X86::VSHUFPDrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]731 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]732 DecodeSHUFPMask(MVT::v2f64,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]733 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]734 ShuffleMask);
735 Src1Name = getRegName(MI->getOperand(1).getReg());
736 DestName = getRegName(MI->getOperand(0).getReg());
737 break;
738 case X86::VSHUFPDYrri:
739 Src2Name = getRegName(MI->getOperand(2).getReg());
740 // FALL THROUGH.
741 case X86::VSHUFPDYrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]742 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]743 DecodeSHUFPMask(MVT::v4f64,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]744 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]745 ShuffleMask);
746 Src1Name = getRegName(MI->getOperand(1).getReg());
747 DestName = getRegName(MI->getOperand(0).getReg());
748 break;
749
750 case X86::SHUFPSrri:
751 case X86::VSHUFPSrri:
752 Src2Name = getRegName(MI->getOperand(2).getReg());
753 // FALL THROUGH.
754 case X86::SHUFPSrmi:
755 case X86::VSHUFPSrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]756 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]757 DecodeSHUFPMask(MVT::v4f32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]758 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]759 ShuffleMask);
760 Src1Name = getRegName(MI->getOperand(1).getReg());
761 DestName = getRegName(MI->getOperand(0).getReg());
762 break;
763 case X86::VSHUFPSYrri:
764 Src2Name = getRegName(MI->getOperand(2).getReg());
765 // FALL THROUGH.
766 case X86::VSHUFPSYrmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]767 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]768 DecodeSHUFPMask(MVT::v8f32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]769 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]770 ShuffleMask);
771 Src1Name = getRegName(MI->getOperand(1).getReg());
772 DestName = getRegName(MI->getOperand(0).getReg());
773 break;
Igor Bregerd7bae452015-10-15 13:29:07 +0000[diff] [blame^]774 CASE_VSHUF(64X2)
775 CASE_VSHUF(32X4) {
776 MVT VT;
777 bool HasMemOp;
778 unsigned NumOp = MI->getNumOperands();
779 getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
780 decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
781 ShuffleMask);
782 DestName = getRegName(MI->getOperand(0).getReg());
783 if (HasMemOp) {
784 assert((NumOp >= 8) && "Expected at least 8 operands!");
785 Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
786 } else {
787 assert((NumOp >= 4) && "Expected at least 4 operands!");
788 Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
789 Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
790 }
791 break;
792 }
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]793 case X86::UNPCKLPDrr:
794 case X86::VUNPCKLPDrr:
795 Src2Name = getRegName(MI->getOperand(2).getReg());
796 // FALL THROUGH.
797 case X86::UNPCKLPDrm:
798 case X86::VUNPCKLPDrm:
799 DecodeUNPCKLMask(MVT::v2f64, ShuffleMask);
800 Src1Name = getRegName(MI->getOperand(1).getReg());
801 DestName = getRegName(MI->getOperand(0).getReg());
802 break;
803 case X86::VUNPCKLPDYrr:
804 Src2Name = getRegName(MI->getOperand(2).getReg());
805 // FALL THROUGH.
806 case X86::VUNPCKLPDYrm:
807 DecodeUNPCKLMask(MVT::v4f64, ShuffleMask);
808 Src1Name = getRegName(MI->getOperand(1).getReg());
809 DestName = getRegName(MI->getOperand(0).getReg());
810 break;
811 case X86::VUNPCKLPDZrr:
812 Src2Name = getRegName(MI->getOperand(2).getReg());
813 // FALL THROUGH.
814 case X86::VUNPCKLPDZrm:
815 DecodeUNPCKLMask(MVT::v8f64, ShuffleMask);
816 Src1Name = getRegName(MI->getOperand(1).getReg());
817 DestName = getRegName(MI->getOperand(0).getReg());
818 break;
819 case X86::UNPCKLPSrr:
820 case X86::VUNPCKLPSrr:
821 Src2Name = getRegName(MI->getOperand(2).getReg());
822 // FALL THROUGH.
823 case X86::UNPCKLPSrm:
824 case X86::VUNPCKLPSrm:
825 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask);
826 Src1Name = getRegName(MI->getOperand(1).getReg());
827 DestName = getRegName(MI->getOperand(0).getReg());
828 break;
829 case X86::VUNPCKLPSYrr:
830 Src2Name = getRegName(MI->getOperand(2).getReg());
831 // FALL THROUGH.
832 case X86::VUNPCKLPSYrm:
833 DecodeUNPCKLMask(MVT::v8f32, ShuffleMask);
834 Src1Name = getRegName(MI->getOperand(1).getReg());
835 DestName = getRegName(MI->getOperand(0).getReg());
836 break;
837 case X86::VUNPCKLPSZrr:
838 Src2Name = getRegName(MI->getOperand(2).getReg());
839 // FALL THROUGH.
840 case X86::VUNPCKLPSZrm:
841 DecodeUNPCKLMask(MVT::v16f32, ShuffleMask);
842 Src1Name = getRegName(MI->getOperand(1).getReg());
843 DestName = getRegName(MI->getOperand(0).getReg());
844 break;
845 case X86::UNPCKHPDrr:
846 case X86::VUNPCKHPDrr:
847 Src2Name = getRegName(MI->getOperand(2).getReg());
848 // FALL THROUGH.
849 case X86::UNPCKHPDrm:
850 case X86::VUNPCKHPDrm:
851 DecodeUNPCKHMask(MVT::v2f64, ShuffleMask);
852 Src1Name = getRegName(MI->getOperand(1).getReg());
853 DestName = getRegName(MI->getOperand(0).getReg());
854 break;
855 case X86::VUNPCKHPDYrr:
856 Src2Name = getRegName(MI->getOperand(2).getReg());
857 // FALL THROUGH.
858 case X86::VUNPCKHPDYrm:
859 DecodeUNPCKHMask(MVT::v4f64, ShuffleMask);
860 Src1Name = getRegName(MI->getOperand(1).getReg());
861 DestName = getRegName(MI->getOperand(0).getReg());
862 break;
863 case X86::VUNPCKHPDZrr:
864 Src2Name = getRegName(MI->getOperand(2).getReg());
865 // FALL THROUGH.
866 case X86::VUNPCKHPDZrm:
867 DecodeUNPCKHMask(MVT::v8f64, ShuffleMask);
868 Src1Name = getRegName(MI->getOperand(1).getReg());
869 DestName = getRegName(MI->getOperand(0).getReg());
870 break;
871 case X86::UNPCKHPSrr:
872 case X86::VUNPCKHPSrr:
873 Src2Name = getRegName(MI->getOperand(2).getReg());
874 // FALL THROUGH.
875 case X86::UNPCKHPSrm:
876 case X86::VUNPCKHPSrm:
877 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask);
878 Src1Name = getRegName(MI->getOperand(1).getReg());
879 DestName = getRegName(MI->getOperand(0).getReg());
880 break;
881 case X86::VUNPCKHPSYrr:
882 Src2Name = getRegName(MI->getOperand(2).getReg());
883 // FALL THROUGH.
884 case X86::VUNPCKHPSYrm:
885 DecodeUNPCKHMask(MVT::v8f32, ShuffleMask);
886 Src1Name = getRegName(MI->getOperand(1).getReg());
887 DestName = getRegName(MI->getOperand(0).getReg());
888 break;
889 case X86::VUNPCKHPSZrr:
890 Src2Name = getRegName(MI->getOperand(2).getReg());
891 // FALL THROUGH.
892 case X86::VUNPCKHPSZrm:
893 DecodeUNPCKHMask(MVT::v16f32, ShuffleMask);
894 Src1Name = getRegName(MI->getOperand(1).getReg());
895 DestName = getRegName(MI->getOperand(0).getReg());
896 break;
897 case X86::VPERMILPSri:
898 Src1Name = getRegName(MI->getOperand(1).getReg());
899 // FALL THROUGH.
900 case X86::VPERMILPSmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]901 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]902 DecodePSHUFMask(MVT::v4f32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]903 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]904 ShuffleMask);
905 DestName = getRegName(MI->getOperand(0).getReg());
906 break;
907 case X86::VPERMILPSYri:
908 Src1Name = getRegName(MI->getOperand(1).getReg());
909 // FALL THROUGH.
910 case X86::VPERMILPSYmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]911 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]912 DecodePSHUFMask(MVT::v8f32,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]913 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]914 ShuffleMask);
915 DestName = getRegName(MI->getOperand(0).getReg());
916 break;
917 case X86::VPERMILPDri:
918 Src1Name = getRegName(MI->getOperand(1).getReg());
919 // FALL THROUGH.
920 case X86::VPERMILPDmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]921 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]922 DecodePSHUFMask(MVT::v2f64,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]923 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]924 ShuffleMask);
925 DestName = getRegName(MI->getOperand(0).getReg());
926 break;
927 case X86::VPERMILPDYri:
928 Src1Name = getRegName(MI->getOperand(1).getReg());
929 // FALL THROUGH.
930 case X86::VPERMILPDYmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]931 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]932 DecodePSHUFMask(MVT::v4f64,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]933 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]934 ShuffleMask);
935 DestName = getRegName(MI->getOperand(0).getReg());
936 break;
937 case X86::VPERM2F128rr:
938 case X86::VPERM2I128rr:
939 Src2Name = getRegName(MI->getOperand(2).getReg());
940 // FALL THROUGH.
941 case X86::VPERM2F128rm:
942 case X86::VPERM2I128rm:
943 // For instruction comments purpose, assume the 256-bit vector is v4i64.
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]944 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]945 DecodeVPERM2X128Mask(MVT::v4i64,
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]946 MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]947 ShuffleMask);
948 Src1Name = getRegName(MI->getOperand(1).getReg());
949 DestName = getRegName(MI->getOperand(0).getReg());
950 break;
951 case X86::VPERMQYri:
952 case X86::VPERMPDYri:
953 Src1Name = getRegName(MI->getOperand(1).getReg());
954 // FALL THROUGH.
955 case X86::VPERMQYmi:
956 case X86::VPERMPDYmi:
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]957 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
958 DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]959 ShuffleMask);
960 DestName = getRegName(MI->getOperand(0).getReg());
961 break;
962
963 case X86::MOVSDrr:
964 case X86::VMOVSDrr:
965 Src2Name = getRegName(MI->getOperand(2).getReg());
966 Src1Name = getRegName(MI->getOperand(1).getReg());
967 // FALL THROUGH.
968 case X86::MOVSDrm:
969 case X86::VMOVSDrm:
970 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
971 DestName = getRegName(MI->getOperand(0).getReg());
972 break;
973 case X86::MOVSSrr:
974 case X86::VMOVSSrr:
975 Src2Name = getRegName(MI->getOperand(2).getReg());
976 Src1Name = getRegName(MI->getOperand(1).getReg());
977 // FALL THROUGH.
978 case X86::MOVSSrm:
979 case X86::VMOVSSrm:
980 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
981 DestName = getRegName(MI->getOperand(0).getReg());
982 break;
983
984 case X86::MOVPQI2QIrr:
985 case X86::MOVZPQILo2PQIrr:
986 case X86::VMOVPQI2QIrr:
987 case X86::VMOVZPQILo2PQIrr:
988 Src1Name = getRegName(MI->getOperand(1).getReg());
989 // FALL THROUGH.
990 case X86::MOVQI2PQIrm:
991 case X86::MOVZQI2PQIrm:
992 case X86::MOVZPQILo2PQIrm:
993 case X86::VMOVQI2PQIrm:
994 case X86::VMOVZQI2PQIrm:
995 case X86::VMOVZPQILo2PQIrm:
996 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
997 DestName = getRegName(MI->getOperand(0).getReg());
998 break;
999 case X86::MOVDI2PDIrm:
1000 case X86::VMOVDI2PDIrm:
1001 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
1002 DestName = getRegName(MI->getOperand(0).getReg());
1003 break;
1004
Simon Pilgrimd85cae32015-07-06 20:46:41 +0000[diff] [blame]1005 case X86::EXTRQI:
1006 if (MI->getOperand(2).isImm() &&
1007 MI->getOperand(3).isImm())
1008 DecodeEXTRQIMask(MI->getOperand(2).getImm(),
1009 MI->getOperand(3).getImm(),
1010 ShuffleMask);
1011
1012 DestName = getRegName(MI->getOperand(0).getReg());
1013 Src1Name = getRegName(MI->getOperand(1).getReg());
1014 break;
1015
1016 case X86::INSERTQI:
1017 if (MI->getOperand(3).isImm() &&
1018 MI->getOperand(4).isImm())
1019 DecodeINSERTQIMask(MI->getOperand(3).getImm(),
1020 MI->getOperand(4).getImm(),
1021 ShuffleMask);
1022
1023 DestName = getRegName(MI->getOperand(0).getReg());
1024 Src1Name = getRegName(MI->getOperand(1).getReg());
1025 Src2Name = getRegName(MI->getOperand(2).getReg());
1026 break;
1027
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1028 case X86::PMOVZXBWrr:
1029 case X86::PMOVZXBDrr:
1030 case X86::PMOVZXBQrr:
1031 case X86::PMOVZXWDrr:
1032 case X86::PMOVZXWQrr:
1033 case X86::PMOVZXDQrr:
1034 case X86::VPMOVZXBWrr:
1035 case X86::VPMOVZXBDrr:
1036 case X86::VPMOVZXBQrr:
1037 case X86::VPMOVZXWDrr:
1038 case X86::VPMOVZXWQrr:
1039 case X86::VPMOVZXDQrr:
1040 case X86::VPMOVZXBWYrr:
1041 case X86::VPMOVZXBDYrr:
1042 case X86::VPMOVZXBQYrr:
1043 case X86::VPMOVZXWDYrr:
1044 case X86::VPMOVZXWQYrr:
1045 case X86::VPMOVZXDQYrr:
1046 Src1Name = getRegName(MI->getOperand(1).getReg());
1047 // FALL THROUGH.
1048 case X86::PMOVZXBWrm:
1049 case X86::PMOVZXBDrm:
1050 case X86::PMOVZXBQrm:
1051 case X86::PMOVZXWDrm:
1052 case X86::PMOVZXWQrm:
1053 case X86::PMOVZXDQrm:
1054 case X86::VPMOVZXBWrm:
1055 case X86::VPMOVZXBDrm:
1056 case X86::VPMOVZXBQrm:
1057 case X86::VPMOVZXWDrm:
1058 case X86::VPMOVZXWQrm:
1059 case X86::VPMOVZXDQrm:
1060 case X86::VPMOVZXBWYrm:
1061 case X86::VPMOVZXBDYrm:
1062 case X86::VPMOVZXBQYrm:
1063 case X86::VPMOVZXWDYrm:
1064 case X86::VPMOVZXWQYrm:
1065 case X86::VPMOVZXDQYrm: {
1066 MVT SrcVT, DstVT;
1067 getZeroExtensionTypes(MI, SrcVT, DstVT);
1068 DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask);
1069 DestName = getRegName(MI->getOperand(0).getReg());
1070 } break;
1071 }
1072
1073 // The only comments we decode are shuffles, so give up if we were unable to
1074 // decode a shuffle mask.
1075 if (ShuffleMask.empty())
1076 return false;
1077
1078 if (!DestName) DestName = Src1Name;
1079 OS << (DestName ? DestName : "mem") << " = ";
1080
1081 // If the two sources are the same, canonicalize the input elements to be
1082 // from the first src so that we get larger element spans.
1083 if (Src1Name == Src2Name) {
1084 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1085 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]1086 ShuffleMask[i] >= (int)e) // From second mask.
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1087 ShuffleMask[i] -= e;
1088 }
1089 }
1090
1091 // The shuffle mask specifies which elements of the src1/src2 fill in the
1092 // destination, with a few sentinel values. Loop through and print them
1093 // out.
1094 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1095 if (i != 0)
1096 OS << ',';
1097 if (ShuffleMask[i] == SM_SentinelZero) {
1098 OS << "zero";
1099 continue;
1100 }
1101
1102 // Otherwise, it must come from src1 or src2. Print the span of elements
1103 // that comes from this src.
1104 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1105 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1106 OS << (SrcName ? SrcName : "mem") << '[';
1107 bool IsFirst = true;
1108 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1109 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1110 if (!IsFirst)
1111 OS << ',';
1112 else
1113 IsFirst = false;
1114 if (ShuffleMask[i] == SM_SentinelUndef)
1115 OS << "u";
1116 else
1117 OS << ShuffleMask[i] % ShuffleMask.size();
1118 ++i;
1119 }
1120 OS << ']';
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]1121 --i; // For loop increments element #.
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1122 }
1123 //MI->print(OS, 0);
1124 OS << "\n";
1125
1126 // We successfully added a comment to this instruction.
1127 return true;
1128}