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gerrit-public.fairphone.software / toolchain / llvm-project / d834d8301d7d2219f4c6c29e7e0906d18a52fbe3 / . / llvm / test / CodeGen / RISCV / float-fcmp.ll
blob: 16f441847911b73a3a543e9df39991009c37448e [file] [log] [blame]
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN: | FileCheck -check-prefix=RV32IF %s
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN: | FileCheck -check-prefix=RV64IF %s
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]6
7define i32 @fcmp_false(float %a, float %b) nounwind {
8; RV32IF-LABEL: fcmp_false:
9; RV32IF: # %bb.0:
10; RV32IF-NEXT: mv a0, zero
11; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]12;
13; RV64IF-LABEL: fcmp_false:
14; RV64IF: # %bb.0:
15; RV64IF-NEXT: mv a0, zero
16; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]17 %1 = fcmp false float %a, %b
18 %2 = zext i1 %1 to i32
19 ret i32 %2
20}
21
22define i32 @fcmp_oeq(float %a, float %b) nounwind {
23; RV32IF-LABEL: fcmp_oeq:
24; RV32IF: # %bb.0:
25; RV32IF-NEXT: fmv.w.x ft0, a1
26; RV32IF-NEXT: fmv.w.x ft1, a0
27; RV32IF-NEXT: feq.s a0, ft1, ft0
28; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]29;
30; RV64IF-LABEL: fcmp_oeq:
31; RV64IF: # %bb.0:
32; RV64IF-NEXT: fmv.w.x ft0, a1
33; RV64IF-NEXT: fmv.w.x ft1, a0
34; RV64IF-NEXT: feq.s a0, ft1, ft0
35; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]36 %1 = fcmp oeq float %a, %b
37 %2 = zext i1 %1 to i32
38 ret i32 %2
39}
40
41define i32 @fcmp_ogt(float %a, float %b) nounwind {
42; RV32IF-LABEL: fcmp_ogt:
43; RV32IF: # %bb.0:
44; RV32IF-NEXT: fmv.w.x ft0, a0
45; RV32IF-NEXT: fmv.w.x ft1, a1
46; RV32IF-NEXT: flt.s a0, ft1, ft0
47; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]48;
49; RV64IF-LABEL: fcmp_ogt:
50; RV64IF: # %bb.0:
51; RV64IF-NEXT: fmv.w.x ft0, a0
52; RV64IF-NEXT: fmv.w.x ft1, a1
53; RV64IF-NEXT: flt.s a0, ft1, ft0
54; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]55 %1 = fcmp ogt float %a, %b
56 %2 = zext i1 %1 to i32
57 ret i32 %2
58}
59
60define i32 @fcmp_oge(float %a, float %b) nounwind {
61; RV32IF-LABEL: fcmp_oge:
62; RV32IF: # %bb.0:
63; RV32IF-NEXT: fmv.w.x ft0, a0
64; RV32IF-NEXT: fmv.w.x ft1, a1
65; RV32IF-NEXT: fle.s a0, ft1, ft0
66; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]67;
68; RV64IF-LABEL: fcmp_oge:
69; RV64IF: # %bb.0:
70; RV64IF-NEXT: fmv.w.x ft0, a0
71; RV64IF-NEXT: fmv.w.x ft1, a1
72; RV64IF-NEXT: fle.s a0, ft1, ft0
73; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]74 %1 = fcmp oge float %a, %b
75 %2 = zext i1 %1 to i32
76 ret i32 %2
77}
78
79define i32 @fcmp_olt(float %a, float %b) nounwind {
80; RV32IF-LABEL: fcmp_olt:
81; RV32IF: # %bb.0:
82; RV32IF-NEXT: fmv.w.x ft0, a1
83; RV32IF-NEXT: fmv.w.x ft1, a0
84; RV32IF-NEXT: flt.s a0, ft1, ft0
85; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]86;
87; RV64IF-LABEL: fcmp_olt:
88; RV64IF: # %bb.0:
89; RV64IF-NEXT: fmv.w.x ft0, a1
90; RV64IF-NEXT: fmv.w.x ft1, a0
91; RV64IF-NEXT: flt.s a0, ft1, ft0
92; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]93 %1 = fcmp olt float %a, %b
94 %2 = zext i1 %1 to i32
95 ret i32 %2
96}
97
98define i32 @fcmp_ole(float %a, float %b) nounwind {
99; RV32IF-LABEL: fcmp_ole:
100; RV32IF: # %bb.0:
101; RV32IF-NEXT: fmv.w.x ft0, a1
102; RV32IF-NEXT: fmv.w.x ft1, a0
103; RV32IF-NEXT: fle.s a0, ft1, ft0
104; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]105;
106; RV64IF-LABEL: fcmp_ole:
107; RV64IF: # %bb.0:
108; RV64IF-NEXT: fmv.w.x ft0, a1
109; RV64IF-NEXT: fmv.w.x ft1, a0
110; RV64IF-NEXT: fle.s a0, ft1, ft0
111; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]112 %1 = fcmp ole float %a, %b
113 %2 = zext i1 %1 to i32
114 ret i32 %2
115}
116
117define i32 @fcmp_one(float %a, float %b) nounwind {
118; RV32IF-LABEL: fcmp_one:
119; RV32IF: # %bb.0:
120; RV32IF-NEXT: fmv.w.x ft0, a0
121; RV32IF-NEXT: fmv.w.x ft1, a1
122; RV32IF-NEXT: feq.s a0, ft1, ft1
123; RV32IF-NEXT: feq.s a1, ft0, ft0
124; RV32IF-NEXT: and a0, a1, a0
125; RV32IF-NEXT: feq.s a1, ft0, ft1
126; RV32IF-NEXT: not a1, a1
127; RV32IF-NEXT: seqz a0, a0
128; RV32IF-NEXT: xori a0, a0, 1
129; RV32IF-NEXT: and a0, a1, a0
130; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]131;
132; RV64IF-LABEL: fcmp_one:
133; RV64IF: # %bb.0:
134; RV64IF-NEXT: fmv.w.x ft0, a0
135; RV64IF-NEXT: fmv.w.x ft1, a1
136; RV64IF-NEXT: feq.s a0, ft1, ft1
137; RV64IF-NEXT: feq.s a1, ft0, ft0
138; RV64IF-NEXT: and a0, a1, a0
139; RV64IF-NEXT: feq.s a1, ft0, ft1
140; RV64IF-NEXT: not a1, a1
141; RV64IF-NEXT: seqz a0, a0
142; RV64IF-NEXT: xori a0, a0, 1
143; RV64IF-NEXT: and a0, a1, a0
144; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]145 %1 = fcmp one float %a, %b
146 %2 = zext i1 %1 to i32
147 ret i32 %2
148}
149
150define i32 @fcmp_ord(float %a, float %b) nounwind {
151; RV32IF-LABEL: fcmp_ord:
152; RV32IF: # %bb.0:
153; RV32IF-NEXT: fmv.w.x ft0, a1
154; RV32IF-NEXT: feq.s a1, ft0, ft0
155; RV32IF-NEXT: fmv.w.x ft0, a0
156; RV32IF-NEXT: feq.s a0, ft0, ft0
157; RV32IF-NEXT: and a0, a0, a1
158; RV32IF-NEXT: seqz a0, a0
159; RV32IF-NEXT: xori a0, a0, 1
160; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]161;
162; RV64IF-LABEL: fcmp_ord:
163; RV64IF: # %bb.0:
164; RV64IF-NEXT: fmv.w.x ft0, a1
165; RV64IF-NEXT: feq.s a1, ft0, ft0
166; RV64IF-NEXT: fmv.w.x ft0, a0
167; RV64IF-NEXT: feq.s a0, ft0, ft0
168; RV64IF-NEXT: and a0, a0, a1
169; RV64IF-NEXT: seqz a0, a0
170; RV64IF-NEXT: xori a0, a0, 1
171; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]172 %1 = fcmp ord float %a, %b
173 %2 = zext i1 %1 to i32
174 ret i32 %2
175}
176
177define i32 @fcmp_ueq(float %a, float %b) nounwind {
178; RV32IF-LABEL: fcmp_ueq:
179; RV32IF: # %bb.0:
180; RV32IF-NEXT: fmv.w.x ft0, a1
181; RV32IF-NEXT: fmv.w.x ft1, a0
182; RV32IF-NEXT: feq.s a0, ft1, ft0
183; RV32IF-NEXT: feq.s a1, ft0, ft0
184; RV32IF-NEXT: feq.s a2, ft1, ft1
185; RV32IF-NEXT: and a1, a2, a1
186; RV32IF-NEXT: seqz a1, a1
187; RV32IF-NEXT: or a0, a0, a1
188; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]189;
190; RV64IF-LABEL: fcmp_ueq:
191; RV64IF: # %bb.0:
192; RV64IF-NEXT: fmv.w.x ft0, a1
193; RV64IF-NEXT: fmv.w.x ft1, a0
194; RV64IF-NEXT: feq.s a0, ft1, ft0
195; RV64IF-NEXT: feq.s a1, ft0, ft0
196; RV64IF-NEXT: feq.s a2, ft1, ft1
197; RV64IF-NEXT: and a1, a2, a1
198; RV64IF-NEXT: seqz a1, a1
199; RV64IF-NEXT: or a0, a0, a1
200; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]201 %1 = fcmp ueq float %a, %b
202 %2 = zext i1 %1 to i32
203 ret i32 %2
204}
205
206define i32 @fcmp_ugt(float %a, float %b) nounwind {
207; RV32IF-LABEL: fcmp_ugt:
208; RV32IF: # %bb.0:
209; RV32IF-NEXT: fmv.w.x ft0, a1
210; RV32IF-NEXT: fmv.w.x ft1, a0
211; RV32IF-NEXT: fle.s a0, ft1, ft0
212; RV32IF-NEXT: xori a0, a0, 1
213; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]214;
215; RV64IF-LABEL: fcmp_ugt:
216; RV64IF: # %bb.0:
217; RV64IF-NEXT: fmv.w.x ft0, a1
218; RV64IF-NEXT: fmv.w.x ft1, a0
219; RV64IF-NEXT: fle.s a0, ft1, ft0
220; RV64IF-NEXT: xori a0, a0, 1
221; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]222 %1 = fcmp ugt float %a, %b
223 %2 = zext i1 %1 to i32
224 ret i32 %2
225}
226
227define i32 @fcmp_uge(float %a, float %b) nounwind {
228; RV32IF-LABEL: fcmp_uge:
229; RV32IF: # %bb.0:
230; RV32IF-NEXT: fmv.w.x ft0, a1
231; RV32IF-NEXT: fmv.w.x ft1, a0
232; RV32IF-NEXT: flt.s a0, ft1, ft0
233; RV32IF-NEXT: xori a0, a0, 1
234; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]235;
236; RV64IF-LABEL: fcmp_uge:
237; RV64IF: # %bb.0:
238; RV64IF-NEXT: fmv.w.x ft0, a1
239; RV64IF-NEXT: fmv.w.x ft1, a0
240; RV64IF-NEXT: flt.s a0, ft1, ft0
241; RV64IF-NEXT: xori a0, a0, 1
242; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]243 %1 = fcmp uge float %a, %b
244 %2 = zext i1 %1 to i32
245 ret i32 %2
246}
247
248define i32 @fcmp_ult(float %a, float %b) nounwind {
249; RV32IF-LABEL: fcmp_ult:
250; RV32IF: # %bb.0:
251; RV32IF-NEXT: fmv.w.x ft0, a0
252; RV32IF-NEXT: fmv.w.x ft1, a1
253; RV32IF-NEXT: fle.s a0, ft1, ft0
254; RV32IF-NEXT: xori a0, a0, 1
255; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]256;
257; RV64IF-LABEL: fcmp_ult:
258; RV64IF: # %bb.0:
259; RV64IF-NEXT: fmv.w.x ft0, a0
260; RV64IF-NEXT: fmv.w.x ft1, a1
261; RV64IF-NEXT: fle.s a0, ft1, ft0
262; RV64IF-NEXT: xori a0, a0, 1
263; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]264 %1 = fcmp ult float %a, %b
265 %2 = zext i1 %1 to i32
266 ret i32 %2
267}
268
269define i32 @fcmp_ule(float %a, float %b) nounwind {
270; RV32IF-LABEL: fcmp_ule:
271; RV32IF: # %bb.0:
272; RV32IF-NEXT: fmv.w.x ft0, a0
273; RV32IF-NEXT: fmv.w.x ft1, a1
274; RV32IF-NEXT: flt.s a0, ft1, ft0
275; RV32IF-NEXT: xori a0, a0, 1
276; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]277;
278; RV64IF-LABEL: fcmp_ule:
279; RV64IF: # %bb.0:
280; RV64IF-NEXT: fmv.w.x ft0, a0
281; RV64IF-NEXT: fmv.w.x ft1, a1
282; RV64IF-NEXT: flt.s a0, ft1, ft0
283; RV64IF-NEXT: xori a0, a0, 1
284; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]285 %1 = fcmp ule float %a, %b
286 %2 = zext i1 %1 to i32
287 ret i32 %2
288}
289
290define i32 @fcmp_une(float %a, float %b) nounwind {
291; RV32IF-LABEL: fcmp_une:
292; RV32IF: # %bb.0:
293; RV32IF-NEXT: fmv.w.x ft0, a1
294; RV32IF-NEXT: fmv.w.x ft1, a0
295; RV32IF-NEXT: feq.s a0, ft1, ft0
296; RV32IF-NEXT: xori a0, a0, 1
297; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]298;
299; RV64IF-LABEL: fcmp_une:
300; RV64IF: # %bb.0:
301; RV64IF-NEXT: fmv.w.x ft0, a1
302; RV64IF-NEXT: fmv.w.x ft1, a0
303; RV64IF-NEXT: feq.s a0, ft1, ft0
304; RV64IF-NEXT: xori a0, a0, 1
305; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]306 %1 = fcmp une float %a, %b
307 %2 = zext i1 %1 to i32
308 ret i32 %2
309}
310
311define i32 @fcmp_uno(float %a, float %b) nounwind {
312; RV32IF-LABEL: fcmp_uno:
313; RV32IF: # %bb.0:
314; RV32IF-NEXT: fmv.w.x ft0, a1
315; RV32IF-NEXT: feq.s a1, ft0, ft0
316; RV32IF-NEXT: fmv.w.x ft0, a0
317; RV32IF-NEXT: feq.s a0, ft0, ft0
318; RV32IF-NEXT: and a0, a0, a1
319; RV32IF-NEXT: seqz a0, a0
320; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]321;
322; RV64IF-LABEL: fcmp_uno:
323; RV64IF: # %bb.0:
324; RV64IF-NEXT: fmv.w.x ft0, a1
325; RV64IF-NEXT: feq.s a1, ft0, ft0
326; RV64IF-NEXT: fmv.w.x ft0, a0
327; RV64IF-NEXT: feq.s a0, ft0, ft0
328; RV64IF-NEXT: and a0, a0, a1
329; RV64IF-NEXT: seqz a0, a0
330; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]331 %1 = fcmp uno float %a, %b
332 %2 = zext i1 %1 to i32
333 ret i32 %2
334}
335
336define i32 @fcmp_true(float %a, float %b) nounwind {
337; RV32IF-LABEL: fcmp_true:
338; RV32IF: # %bb.0:
339; RV32IF-NEXT: addi a0, zero, 1
340; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]341;
342; RV64IF-LABEL: fcmp_true:
343; RV64IF: # %bb.0:
344; RV64IF-NEXT: addi a0, zero, 1
345; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]346 %1 = fcmp true float %a, %b
347 %2 = zext i1 %1 to i32
348 ret i32 %2
349}