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gerrit-public.fairphone.software / toolchain / llvm-project / d834d8301d7d2219f4c6c29e7e0906d18a52fbe3 / . / llvm / test / CodeGen / RISCV / float-select-fcmp.ll
blob: 3659ed2d17504f53d7dfdd6e0befda192dec2515 [file] [log] [blame]
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN: | FileCheck -check-prefix=RV32IF %s
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]4; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
5; RUN: | FileCheck -check-prefix=RV64IF %s
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]6
7define float @select_fcmp_false(float %a, float %b) nounwind {
8; RV32IF-LABEL: select_fcmp_false:
9; RV32IF: # %bb.0:
10; RV32IF-NEXT: mv a0, a1
11; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]12;
13; RV64IF-LABEL: select_fcmp_false:
14; RV64IF: # %bb.0:
15; RV64IF-NEXT: mv a0, a1
16; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]17 %1 = fcmp false float %a, %b
18 %2 = select i1 %1, float %a, float %b
19 ret float %2
20}
21
22define float @select_fcmp_oeq(float %a, float %b) nounwind {
23; RV32IF-LABEL: select_fcmp_oeq:
24; RV32IF: # %bb.0:
25; RV32IF-NEXT: fmv.w.x ft1, a1
26; RV32IF-NEXT: fmv.w.x ft0, a0
27; RV32IF-NEXT: feq.s a0, ft0, ft1
28; RV32IF-NEXT: bnez a0, .LBB1_2
29; RV32IF-NEXT: # %bb.1:
30; RV32IF-NEXT: fmv.s ft0, ft1
31; RV32IF-NEXT: .LBB1_2:
32; RV32IF-NEXT: fmv.x.w a0, ft0
33; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]34;
35; RV64IF-LABEL: select_fcmp_oeq:
36; RV64IF: # %bb.0:
37; RV64IF-NEXT: fmv.w.x ft1, a1
38; RV64IF-NEXT: fmv.w.x ft0, a0
39; RV64IF-NEXT: feq.s a0, ft0, ft1
40; RV64IF-NEXT: bnez a0, .LBB1_2
41; RV64IF-NEXT: # %bb.1:
42; RV64IF-NEXT: fmv.s ft0, ft1
43; RV64IF-NEXT: .LBB1_2:
44; RV64IF-NEXT: fmv.x.w a0, ft0
45; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]46 %1 = fcmp oeq float %a, %b
47 %2 = select i1 %1, float %a, float %b
48 ret float %2
49}
50
51define float @select_fcmp_ogt(float %a, float %b) nounwind {
52; RV32IF-LABEL: select_fcmp_ogt:
53; RV32IF: # %bb.0:
54; RV32IF-NEXT: fmv.w.x ft0, a0
55; RV32IF-NEXT: fmv.w.x ft1, a1
56; RV32IF-NEXT: flt.s a0, ft1, ft0
57; RV32IF-NEXT: bnez a0, .LBB2_2
58; RV32IF-NEXT: # %bb.1:
59; RV32IF-NEXT: fmv.s ft0, ft1
60; RV32IF-NEXT: .LBB2_2:
61; RV32IF-NEXT: fmv.x.w a0, ft0
62; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]63;
64; RV64IF-LABEL: select_fcmp_ogt:
65; RV64IF: # %bb.0:
66; RV64IF-NEXT: fmv.w.x ft0, a0
67; RV64IF-NEXT: fmv.w.x ft1, a1
68; RV64IF-NEXT: flt.s a0, ft1, ft0
69; RV64IF-NEXT: bnez a0, .LBB2_2
70; RV64IF-NEXT: # %bb.1:
71; RV64IF-NEXT: fmv.s ft0, ft1
72; RV64IF-NEXT: .LBB2_2:
73; RV64IF-NEXT: fmv.x.w a0, ft0
74; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]75 %1 = fcmp ogt float %a, %b
76 %2 = select i1 %1, float %a, float %b
77 ret float %2
78}
79
80define float @select_fcmp_oge(float %a, float %b) nounwind {
81; RV32IF-LABEL: select_fcmp_oge:
82; RV32IF: # %bb.0:
83; RV32IF-NEXT: fmv.w.x ft0, a0
84; RV32IF-NEXT: fmv.w.x ft1, a1
85; RV32IF-NEXT: fle.s a0, ft1, ft0
86; RV32IF-NEXT: bnez a0, .LBB3_2
87; RV32IF-NEXT: # %bb.1:
88; RV32IF-NEXT: fmv.s ft0, ft1
89; RV32IF-NEXT: .LBB3_2:
90; RV32IF-NEXT: fmv.x.w a0, ft0
91; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]92;
93; RV64IF-LABEL: select_fcmp_oge:
94; RV64IF: # %bb.0:
95; RV64IF-NEXT: fmv.w.x ft0, a0
96; RV64IF-NEXT: fmv.w.x ft1, a1
97; RV64IF-NEXT: fle.s a0, ft1, ft0
98; RV64IF-NEXT: bnez a0, .LBB3_2
99; RV64IF-NEXT: # %bb.1:
100; RV64IF-NEXT: fmv.s ft0, ft1
101; RV64IF-NEXT: .LBB3_2:
102; RV64IF-NEXT: fmv.x.w a0, ft0
103; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]104 %1 = fcmp oge float %a, %b
105 %2 = select i1 %1, float %a, float %b
106 ret float %2
107}
108
109define float @select_fcmp_olt(float %a, float %b) nounwind {
110; RV32IF-LABEL: select_fcmp_olt:
111; RV32IF: # %bb.0:
112; RV32IF-NEXT: fmv.w.x ft1, a1
113; RV32IF-NEXT: fmv.w.x ft0, a0
114; RV32IF-NEXT: flt.s a0, ft0, ft1
115; RV32IF-NEXT: bnez a0, .LBB4_2
116; RV32IF-NEXT: # %bb.1:
117; RV32IF-NEXT: fmv.s ft0, ft1
118; RV32IF-NEXT: .LBB4_2:
119; RV32IF-NEXT: fmv.x.w a0, ft0
120; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]121;
122; RV64IF-LABEL: select_fcmp_olt:
123; RV64IF: # %bb.0:
124; RV64IF-NEXT: fmv.w.x ft1, a1
125; RV64IF-NEXT: fmv.w.x ft0, a0
126; RV64IF-NEXT: flt.s a0, ft0, ft1
127; RV64IF-NEXT: bnez a0, .LBB4_2
128; RV64IF-NEXT: # %bb.1:
129; RV64IF-NEXT: fmv.s ft0, ft1
130; RV64IF-NEXT: .LBB4_2:
131; RV64IF-NEXT: fmv.x.w a0, ft0
132; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]133 %1 = fcmp olt float %a, %b
134 %2 = select i1 %1, float %a, float %b
135 ret float %2
136}
137
138define float @select_fcmp_ole(float %a, float %b) nounwind {
139; RV32IF-LABEL: select_fcmp_ole:
140; RV32IF: # %bb.0:
141; RV32IF-NEXT: fmv.w.x ft1, a1
142; RV32IF-NEXT: fmv.w.x ft0, a0
143; RV32IF-NEXT: fle.s a0, ft0, ft1
144; RV32IF-NEXT: bnez a0, .LBB5_2
145; RV32IF-NEXT: # %bb.1:
146; RV32IF-NEXT: fmv.s ft0, ft1
147; RV32IF-NEXT: .LBB5_2:
148; RV32IF-NEXT: fmv.x.w a0, ft0
149; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]150;
151; RV64IF-LABEL: select_fcmp_ole:
152; RV64IF: # %bb.0:
153; RV64IF-NEXT: fmv.w.x ft1, a1
154; RV64IF-NEXT: fmv.w.x ft0, a0
155; RV64IF-NEXT: fle.s a0, ft0, ft1
156; RV64IF-NEXT: bnez a0, .LBB5_2
157; RV64IF-NEXT: # %bb.1:
158; RV64IF-NEXT: fmv.s ft0, ft1
159; RV64IF-NEXT: .LBB5_2:
160; RV64IF-NEXT: fmv.x.w a0, ft0
161; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]162 %1 = fcmp ole float %a, %b
163 %2 = select i1 %1, float %a, float %b
164 ret float %2
165}
166
167define float @select_fcmp_one(float %a, float %b) nounwind {
168; TODO: feq.s+sltiu+bne sequence could be optimised
169; RV32IF-LABEL: select_fcmp_one:
170; RV32IF: # %bb.0:
171; RV32IF-NEXT: fmv.w.x ft0, a0
172; RV32IF-NEXT: fmv.w.x ft1, a1
173; RV32IF-NEXT: feq.s a0, ft1, ft1
174; RV32IF-NEXT: feq.s a1, ft0, ft0
175; RV32IF-NEXT: and a0, a1, a0
176; RV32IF-NEXT: feq.s a1, ft0, ft1
177; RV32IF-NEXT: not a1, a1
178; RV32IF-NEXT: seqz a0, a0
179; RV32IF-NEXT: xori a0, a0, 1
180; RV32IF-NEXT: and a0, a1, a0
181; RV32IF-NEXT: bnez a0, .LBB6_2
182; RV32IF-NEXT: # %bb.1:
183; RV32IF-NEXT: fmv.s ft0, ft1
184; RV32IF-NEXT: .LBB6_2:
185; RV32IF-NEXT: fmv.x.w a0, ft0
186; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]187;
188; RV64IF-LABEL: select_fcmp_one:
189; RV64IF: # %bb.0:
190; RV64IF-NEXT: fmv.w.x ft0, a0
191; RV64IF-NEXT: fmv.w.x ft1, a1
192; RV64IF-NEXT: feq.s a0, ft1, ft1
193; RV64IF-NEXT: feq.s a1, ft0, ft0
194; RV64IF-NEXT: and a0, a1, a0
195; RV64IF-NEXT: feq.s a1, ft0, ft1
196; RV64IF-NEXT: not a1, a1
197; RV64IF-NEXT: seqz a0, a0
198; RV64IF-NEXT: xori a0, a0, 1
199; RV64IF-NEXT: and a0, a1, a0
200; RV64IF-NEXT: bnez a0, .LBB6_2
201; RV64IF-NEXT: # %bb.1:
202; RV64IF-NEXT: fmv.s ft0, ft1
203; RV64IF-NEXT: .LBB6_2:
204; RV64IF-NEXT: fmv.x.w a0, ft0
205; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]206 %1 = fcmp one float %a, %b
207 %2 = select i1 %1, float %a, float %b
208 ret float %2
209}
210
211define float @select_fcmp_ord(float %a, float %b) nounwind {
212; RV32IF-LABEL: select_fcmp_ord:
213; RV32IF: # %bb.0:
214; RV32IF-NEXT: fmv.w.x ft0, a0
215; RV32IF-NEXT: fmv.w.x ft1, a1
216; RV32IF-NEXT: feq.s a0, ft1, ft1
217; RV32IF-NEXT: feq.s a1, ft0, ft0
218; RV32IF-NEXT: and a0, a1, a0
219; RV32IF-NEXT: seqz a0, a0
220; RV32IF-NEXT: xori a0, a0, 1
221; RV32IF-NEXT: bnez a0, .LBB7_2
222; RV32IF-NEXT: # %bb.1:
223; RV32IF-NEXT: fmv.s ft0, ft1
224; RV32IF-NEXT: .LBB7_2:
225; RV32IF-NEXT: fmv.x.w a0, ft0
226; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]227;
228; RV64IF-LABEL: select_fcmp_ord:
229; RV64IF: # %bb.0:
230; RV64IF-NEXT: fmv.w.x ft0, a0
231; RV64IF-NEXT: fmv.w.x ft1, a1
232; RV64IF-NEXT: feq.s a0, ft1, ft1
233; RV64IF-NEXT: feq.s a1, ft0, ft0
234; RV64IF-NEXT: and a0, a1, a0
235; RV64IF-NEXT: seqz a0, a0
236; RV64IF-NEXT: xori a0, a0, 1
237; RV64IF-NEXT: bnez a0, .LBB7_2
238; RV64IF-NEXT: # %bb.1:
239; RV64IF-NEXT: fmv.s ft0, ft1
240; RV64IF-NEXT: .LBB7_2:
241; RV64IF-NEXT: fmv.x.w a0, ft0
242; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]243 %1 = fcmp ord float %a, %b
244 %2 = select i1 %1, float %a, float %b
245 ret float %2
246}
247
248define float @select_fcmp_ueq(float %a, float %b) nounwind {
249; RV32IF-LABEL: select_fcmp_ueq:
250; RV32IF: # %bb.0:
251; RV32IF-NEXT: fmv.w.x ft0, a0
252; RV32IF-NEXT: fmv.w.x ft1, a1
253; RV32IF-NEXT: feq.s a0, ft1, ft1
254; RV32IF-NEXT: feq.s a1, ft0, ft0
255; RV32IF-NEXT: and a0, a1, a0
256; RV32IF-NEXT: seqz a0, a0
257; RV32IF-NEXT: feq.s a1, ft0, ft1
258; RV32IF-NEXT: or a0, a1, a0
259; RV32IF-NEXT: bnez a0, .LBB8_2
260; RV32IF-NEXT: # %bb.1:
261; RV32IF-NEXT: fmv.s ft0, ft1
262; RV32IF-NEXT: .LBB8_2:
263; RV32IF-NEXT: fmv.x.w a0, ft0
264; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]265;
266; RV64IF-LABEL: select_fcmp_ueq:
267; RV64IF: # %bb.0:
268; RV64IF-NEXT: fmv.w.x ft0, a0
269; RV64IF-NEXT: fmv.w.x ft1, a1
270; RV64IF-NEXT: feq.s a0, ft1, ft1
271; RV64IF-NEXT: feq.s a1, ft0, ft0
272; RV64IF-NEXT: and a0, a1, a0
273; RV64IF-NEXT: seqz a0, a0
274; RV64IF-NEXT: feq.s a1, ft0, ft1
275; RV64IF-NEXT: or a0, a1, a0
276; RV64IF-NEXT: bnez a0, .LBB8_2
277; RV64IF-NEXT: # %bb.1:
278; RV64IF-NEXT: fmv.s ft0, ft1
279; RV64IF-NEXT: .LBB8_2:
280; RV64IF-NEXT: fmv.x.w a0, ft0
281; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]282 %1 = fcmp ueq float %a, %b
283 %2 = select i1 %1, float %a, float %b
284 ret float %2
285}
286
287define float @select_fcmp_ugt(float %a, float %b) nounwind {
288; RV32IF-LABEL: select_fcmp_ugt:
289; RV32IF: # %bb.0:
290; RV32IF-NEXT: fmv.w.x ft1, a1
291; RV32IF-NEXT: fmv.w.x ft0, a0
292; RV32IF-NEXT: fle.s a0, ft0, ft1
293; RV32IF-NEXT: xori a0, a0, 1
294; RV32IF-NEXT: bnez a0, .LBB9_2
295; RV32IF-NEXT: # %bb.1:
296; RV32IF-NEXT: fmv.s ft0, ft1
297; RV32IF-NEXT: .LBB9_2:
298; RV32IF-NEXT: fmv.x.w a0, ft0
299; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]300;
301; RV64IF-LABEL: select_fcmp_ugt:
302; RV64IF: # %bb.0:
303; RV64IF-NEXT: fmv.w.x ft1, a1
304; RV64IF-NEXT: fmv.w.x ft0, a0
305; RV64IF-NEXT: fle.s a0, ft0, ft1
306; RV64IF-NEXT: xori a0, a0, 1
307; RV64IF-NEXT: bnez a0, .LBB9_2
308; RV64IF-NEXT: # %bb.1:
309; RV64IF-NEXT: fmv.s ft0, ft1
310; RV64IF-NEXT: .LBB9_2:
311; RV64IF-NEXT: fmv.x.w a0, ft0
312; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]313 %1 = fcmp ugt float %a, %b
314 %2 = select i1 %1, float %a, float %b
315 ret float %2
316}
317
318define float @select_fcmp_uge(float %a, float %b) nounwind {
319; RV32IF-LABEL: select_fcmp_uge:
320; RV32IF: # %bb.0:
321; RV32IF-NEXT: fmv.w.x ft1, a1
322; RV32IF-NEXT: fmv.w.x ft0, a0
323; RV32IF-NEXT: flt.s a0, ft0, ft1
324; RV32IF-NEXT: xori a0, a0, 1
325; RV32IF-NEXT: bnez a0, .LBB10_2
326; RV32IF-NEXT: # %bb.1:
327; RV32IF-NEXT: fmv.s ft0, ft1
328; RV32IF-NEXT: .LBB10_2:
329; RV32IF-NEXT: fmv.x.w a0, ft0
330; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]331;
332; RV64IF-LABEL: select_fcmp_uge:
333; RV64IF: # %bb.0:
334; RV64IF-NEXT: fmv.w.x ft1, a1
335; RV64IF-NEXT: fmv.w.x ft0, a0
336; RV64IF-NEXT: flt.s a0, ft0, ft1
337; RV64IF-NEXT: xori a0, a0, 1
338; RV64IF-NEXT: bnez a0, .LBB10_2
339; RV64IF-NEXT: # %bb.1:
340; RV64IF-NEXT: fmv.s ft0, ft1
341; RV64IF-NEXT: .LBB10_2:
342; RV64IF-NEXT: fmv.x.w a0, ft0
343; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]344 %1 = fcmp uge float %a, %b
345 %2 = select i1 %1, float %a, float %b
346 ret float %2
347}
348
349define float @select_fcmp_ult(float %a, float %b) nounwind {
350; RV32IF-LABEL: select_fcmp_ult:
351; RV32IF: # %bb.0:
352; RV32IF-NEXT: fmv.w.x ft0, a0
353; RV32IF-NEXT: fmv.w.x ft1, a1
354; RV32IF-NEXT: fle.s a0, ft1, ft0
355; RV32IF-NEXT: xori a0, a0, 1
356; RV32IF-NEXT: bnez a0, .LBB11_2
357; RV32IF-NEXT: # %bb.1:
358; RV32IF-NEXT: fmv.s ft0, ft1
359; RV32IF-NEXT: .LBB11_2:
360; RV32IF-NEXT: fmv.x.w a0, ft0
361; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]362;
363; RV64IF-LABEL: select_fcmp_ult:
364; RV64IF: # %bb.0:
365; RV64IF-NEXT: fmv.w.x ft0, a0
366; RV64IF-NEXT: fmv.w.x ft1, a1
367; RV64IF-NEXT: fle.s a0, ft1, ft0
368; RV64IF-NEXT: xori a0, a0, 1
369; RV64IF-NEXT: bnez a0, .LBB11_2
370; RV64IF-NEXT: # %bb.1:
371; RV64IF-NEXT: fmv.s ft0, ft1
372; RV64IF-NEXT: .LBB11_2:
373; RV64IF-NEXT: fmv.x.w a0, ft0
374; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]375 %1 = fcmp ult float %a, %b
376 %2 = select i1 %1, float %a, float %b
377 ret float %2
378}
379
380define float @select_fcmp_ule(float %a, float %b) nounwind {
381; RV32IF-LABEL: select_fcmp_ule:
382; RV32IF: # %bb.0:
383; RV32IF-NEXT: fmv.w.x ft0, a0
384; RV32IF-NEXT: fmv.w.x ft1, a1
385; RV32IF-NEXT: flt.s a0, ft1, ft0
386; RV32IF-NEXT: xori a0, a0, 1
387; RV32IF-NEXT: bnez a0, .LBB12_2
388; RV32IF-NEXT: # %bb.1:
389; RV32IF-NEXT: fmv.s ft0, ft1
390; RV32IF-NEXT: .LBB12_2:
391; RV32IF-NEXT: fmv.x.w a0, ft0
392; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]393;
394; RV64IF-LABEL: select_fcmp_ule:
395; RV64IF: # %bb.0:
396; RV64IF-NEXT: fmv.w.x ft0, a0
397; RV64IF-NEXT: fmv.w.x ft1, a1
398; RV64IF-NEXT: flt.s a0, ft1, ft0
399; RV64IF-NEXT: xori a0, a0, 1
400; RV64IF-NEXT: bnez a0, .LBB12_2
401; RV64IF-NEXT: # %bb.1:
402; RV64IF-NEXT: fmv.s ft0, ft1
403; RV64IF-NEXT: .LBB12_2:
404; RV64IF-NEXT: fmv.x.w a0, ft0
405; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]406 %1 = fcmp ule float %a, %b
407 %2 = select i1 %1, float %a, float %b
408 ret float %2
409}
410
411define float @select_fcmp_une(float %a, float %b) nounwind {
412; RV32IF-LABEL: select_fcmp_une:
413; RV32IF: # %bb.0:
414; RV32IF-NEXT: fmv.w.x ft1, a1
415; RV32IF-NEXT: fmv.w.x ft0, a0
416; RV32IF-NEXT: feq.s a0, ft0, ft1
417; RV32IF-NEXT: xori a0, a0, 1
418; RV32IF-NEXT: bnez a0, .LBB13_2
419; RV32IF-NEXT: # %bb.1:
420; RV32IF-NEXT: fmv.s ft0, ft1
421; RV32IF-NEXT: .LBB13_2:
422; RV32IF-NEXT: fmv.x.w a0, ft0
423; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]424;
425; RV64IF-LABEL: select_fcmp_une:
426; RV64IF: # %bb.0:
427; RV64IF-NEXT: fmv.w.x ft1, a1
428; RV64IF-NEXT: fmv.w.x ft0, a0
429; RV64IF-NEXT: feq.s a0, ft0, ft1
430; RV64IF-NEXT: xori a0, a0, 1
431; RV64IF-NEXT: bnez a0, .LBB13_2
432; RV64IF-NEXT: # %bb.1:
433; RV64IF-NEXT: fmv.s ft0, ft1
434; RV64IF-NEXT: .LBB13_2:
435; RV64IF-NEXT: fmv.x.w a0, ft0
436; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]437 %1 = fcmp une float %a, %b
438 %2 = select i1 %1, float %a, float %b
439 ret float %2
440}
441
442define float @select_fcmp_uno(float %a, float %b) nounwind {
443; TODO: sltiu+bne could be optimized
444; RV32IF-LABEL: select_fcmp_uno:
445; RV32IF: # %bb.0:
446; RV32IF-NEXT: fmv.w.x ft0, a0
447; RV32IF-NEXT: fmv.w.x ft1, a1
448; RV32IF-NEXT: feq.s a0, ft1, ft1
449; RV32IF-NEXT: feq.s a1, ft0, ft0
450; RV32IF-NEXT: and a0, a1, a0
451; RV32IF-NEXT: seqz a0, a0
452; RV32IF-NEXT: bnez a0, .LBB14_2
453; RV32IF-NEXT: # %bb.1:
454; RV32IF-NEXT: fmv.s ft0, ft1
455; RV32IF-NEXT: .LBB14_2:
456; RV32IF-NEXT: fmv.x.w a0, ft0
457; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]458;
459; RV64IF-LABEL: select_fcmp_uno:
460; RV64IF: # %bb.0:
461; RV64IF-NEXT: fmv.w.x ft0, a0
462; RV64IF-NEXT: fmv.w.x ft1, a1
463; RV64IF-NEXT: feq.s a0, ft1, ft1
464; RV64IF-NEXT: feq.s a1, ft0, ft0
465; RV64IF-NEXT: and a0, a1, a0
466; RV64IF-NEXT: seqz a0, a0
467; RV64IF-NEXT: bnez a0, .LBB14_2
468; RV64IF-NEXT: # %bb.1:
469; RV64IF-NEXT: fmv.s ft0, ft1
470; RV64IF-NEXT: .LBB14_2:
471; RV64IF-NEXT: fmv.x.w a0, ft0
472; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]473 %1 = fcmp uno float %a, %b
474 %2 = select i1 %1, float %a, float %b
475 ret float %2
476}
477
478define float @select_fcmp_true(float %a, float %b) nounwind {
479; RV32IF-LABEL: select_fcmp_true:
480; RV32IF: # %bb.0:
481; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]482;
483; RV64IF-LABEL: select_fcmp_true:
484; RV64IF: # %bb.0:
485; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]486 %1 = fcmp true float %a, %b
487 %2 = select i1 %1, float %a, float %b
488 ret float %2
489}
490
491; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
492define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
493; RV32IF-LABEL: i32_select_fcmp_oeq:
494; RV32IF: # %bb.0:
495; RV32IF-NEXT: fmv.w.x ft0, a1
496; RV32IF-NEXT: fmv.w.x ft1, a0
497; RV32IF-NEXT: feq.s a0, ft1, ft0
498; RV32IF-NEXT: bnez a0, .LBB16_2
499; RV32IF-NEXT: # %bb.1:
500; RV32IF-NEXT: mv a2, a3
501; RV32IF-NEXT: .LBB16_2:
502; RV32IF-NEXT: mv a0, a2
503; RV32IF-NEXT: ret
Alex Bradburyd834d832019-01-31 22:48:38 +0000[diff] [blame^]504;
505; RV64IF-LABEL: i32_select_fcmp_oeq:
506; RV64IF: # %bb.0:
507; RV64IF-NEXT: fmv.w.x ft0, a1
508; RV64IF-NEXT: fmv.w.x ft1, a0
509; RV64IF-NEXT: feq.s a0, ft1, ft0
510; RV64IF-NEXT: bnez a0, .LBB16_2
511; RV64IF-NEXT: # %bb.1:
512; RV64IF-NEXT: mv a2, a3
513; RV64IF-NEXT: .LBB16_2:
514; RV64IF-NEXT: mv a0, a2
515; RV64IF-NEXT: ret
Alex Bradbury65d6ea52018-03-21 15:11:02 +0000[diff] [blame]516 %1 = fcmp oeq float %a, %b
517 %2 = select i1 %1, i32 %c, i32 %d
518 ret i32 %2
519}