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gerrit-public.fairphone.software / toolchain / llvm-project / dc44990c7dbc49e596bdd548b6b6500d82e75e68 / . / llvm / lib / Target / ARM / ARMScheduleA9.td
blob: c78f59383f2161ecbdbefbd86b921f972d959a7e [file] [log] [blame]
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1//=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]2//
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]7//
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM Cortex A9 processors.
11//
12//===----------------------------------------------------------------------===//
13
14//
15// Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
16// Reference Manual".
17//
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]18// Functional units
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]19def A9_Issue0 : FuncUnit; // Issue 0
20def A9_Issue1 : FuncUnit; // Issue 1
21def A9_Branch : FuncUnit; // Branch
22def A9_ALU0 : FuncUnit; // ALU / MUL pipeline 0
23def A9_ALU1 : FuncUnit; // ALU pipeline 1
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]24def A9_AGU : FuncUnit; // Address generation unit for ld / st
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]25def A9_NPipe : FuncUnit; // NEON pipeline
26def A9_MUX0 : FuncUnit; // AGU + NEON/FPU multiplexer
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]27def A9_LSUnit : FuncUnit; // L/S Unit
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]28def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
29def A9_DRegsN : FuncUnit; // FP register set, NEON side
30
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]31// Bypasses
32def A9_LdBypass : Bypass;
33
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]34def CortexA9Itineraries : ProcessorItineraries<
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]35 [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]36 A9_LSUnit, A9_DRegsVFP, A9_DRegsN],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]37 [A9_LdBypass], [
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]38 // Two fully-pipelined integer ALU pipelines
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]39
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]40 //
41 // Move instructions, unconditional
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]42 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
43 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
44 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
45 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
48 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
49 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
50 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
51 InstrStage<1, [A9_ALU0, A9_ALU1]>,
52 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]53 //
54 // MVN instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]55 InstrItinData<IIC_iMVNi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
56 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]57 [1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]58 InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
59 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]60 [1, 1], [NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]61 InstrItinData<IIC_iMVNsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
62 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]63 [2, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]64 InstrItinData<IIC_iMVNsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
65 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]66 [3, 1, 1]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]67 //
68 // No operand cycles
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]69 InstrItinData<IIC_iALUx , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
70 InstrStage<1, [A9_ALU0, A9_ALU1]>]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]71 //
72 // Binary Instructions that produce a result
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]73 InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
74 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]75 [1, 1], [NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]76 InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
77 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]78 [1, 1, 1], [NoBypass, A9_LdBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]79 InstrItinData<IIC_iALUsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
80 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]81 [2, 1, 1], [NoBypass, A9_LdBypass, NoBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]82 InstrItinData<IIC_iALUsir,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
83 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]84 [2, 1, 1], [NoBypass, NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]85 InstrItinData<IIC_iALUsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
86 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]87 [3, 1, 1, 1],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]88 [NoBypass, A9_LdBypass, NoBypass, NoBypass]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]89 //
Evan Chengc35d7bb2010-09-29 00:27:46 +0000[diff] [blame]90 // Bitwise Instructions that produce a result
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]91 InstrItinData<IIC_iBITi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
92 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
93 InstrItinData<IIC_iBITr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
94 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
95 InstrItinData<IIC_iBITsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
96 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
97 InstrItinData<IIC_iBITsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
98 InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
Evan Chengc35d7bb2010-09-29 00:27:46 +0000[diff] [blame]99 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]100 // Unary Instructions that produce a result
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]101
102 // CLZ, RBIT, etc.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]103 InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
104 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]105
106 // BFC, BFI, UBFX, SBFX
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]107 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
108 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]109
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]110 //
Evan Cheng62d626c2010-09-25 00:49:35 +0000[diff] [blame]111 // Zero and sign extension instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]112 InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
113 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>,
114 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
115 InstrStage<2, [A9_ALU0, A9_ALU1]>], [3, 1, 1]>,
116 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
117 InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
Evan Cheng62d626c2010-09-25 00:49:35 +0000[diff] [blame]118 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]119 // Compare instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]120 InstrItinData<IIC_iCMPi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
121 InstrStage<1, [A9_ALU0, A9_ALU1]>],
122 [1], [A9_LdBypass]>,
123 InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
124 InstrStage<1, [A9_ALU0, A9_ALU1]>],
125 [1, 1], [A9_LdBypass, A9_LdBypass]>,
126 InstrItinData<IIC_iCMPsi , [InstrStage<2, [A9_ALU0, A9_ALU1]>],
127 [1, 1], [A9_LdBypass, NoBypass]>,
128 InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
129 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]130 [1, 1, 1], [A9_LdBypass, NoBypass, NoBypass]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]131 //
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]132 // Test instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]133 InstrItinData<IIC_iTSTi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
134 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
135 InstrItinData<IIC_iTSTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
136 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
137 InstrItinData<IIC_iTSTsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
138 InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1]>,
139 InstrItinData<IIC_iTSTsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
140 InstrStage<3, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]141 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]142 // Move instructions, conditional
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]143 // FIXME: Correctly model the extra input dep on the destination.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]144 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
145 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
146 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
147 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
148 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
149 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
150 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
151 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]152
153 // Integer multiply pipeline
154 //
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]155 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
156 InstrStage<2, [A9_ALU0]>], [3, 1, 1]>,
157 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
158 InstrStage<2, [A9_ALU0]>],
159 [3, 1, 1, 1]>,
160 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
161 InstrStage<2, [A9_ALU0]>], [4, 1, 1]>,
162 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
163 InstrStage<2, [A9_ALU0]>],
164 [4, 1, 1, 1]>,
165 InstrItinData<IIC_iMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
166 InstrStage<3, [A9_ALU0]>], [4, 5, 1, 1]>,
167 InstrItinData<IIC_iMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
168 InstrStage<3, [A9_ALU0]>],
169 [4, 5, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]170 // Integer load pipeline
171 // FIXME: The timings are some rough approximations
172 //
173 // Immediate offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]174 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]175 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]176 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]177 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]178 [3, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]179 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]180 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]181 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]182 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]183 [4, 1], [A9_LdBypass]>,
184 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]185 InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]186 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]187 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]188 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]189 [3, 3, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]190 //
191 // Register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]192 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]193 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]194 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]195 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]196 [3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]197 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]198 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]199 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]200 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]201 [4, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]202 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]203 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]204 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]205 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]206 [3, 3, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]207 //
208 // Scaled register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]209 InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]210 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]211 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]212 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]213 [4, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]214 InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]215 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]216 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]217 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]218 [5, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]219 //
220 // Immediate offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]221 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]222 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]223 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]224 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]225 [3, 2, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]226 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]227 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]228 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]229 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]230 [4, 3, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]231 //
232 // Register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]233 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]234 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]235 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]236 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]237 [3, 2, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]238 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]239 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]240 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]241 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]242 [4, 3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]243 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]244 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]245 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]246 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]247 [3, 3, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]248 //
249 // Scaled register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]250 InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]251 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]252 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]253 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]254 [4, 3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]255 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]256 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]257 InstrStage<2, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]258 InstrStage<1, [A9_LSUnit]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]259 [5, 4, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]260 //
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]261 // Load multiple, def is the 5th operand.
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]262 // FIXME: This assumes 3 to 4 registers.
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]263 InstrItinData<IIC_iLoad_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]264 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]265 InstrStage<2, [A9_AGU], 1>,
266 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]267 [1, 1, 1, 1, 3],
268 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
269 //
270 // Load multiple + update, defs are the 1st and 5th operands.
271 InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
272 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]273 InstrStage<2, [A9_AGU], 1>,
274 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]275 [2, 1, 1, 1, 3],
276 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
Evan Cheng722cd122010-09-08 22:57:08 +0000[diff] [blame]277 //
278 // Load multiple plus branch
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]279 InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]280 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]281 InstrStage<1, [A9_AGU], 1>,
282 InstrStage<2, [A9_LSUnit]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]283 InstrStage<1, [A9_Branch]>],
284 [1, 2, 1, 1, 3],
285 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
286 //
287 // Pop, def is the 3rd operand.
288 InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
289 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]290 InstrStage<2, [A9_AGU], 1>,
291 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]292 [1, 1, 3],
293 [NoBypass, NoBypass, A9_LdBypass]>,
294 //
295 // Pop + branch, def is the 3rd operand.
296 InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
297 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]298 InstrStage<2, [A9_AGU], 1>,
299 InstrStage<2, [A9_LSUnit]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]300 InstrStage<1, [A9_Branch]>],
301 [1, 1, 3],
302 [NoBypass, NoBypass, A9_LdBypass]>,
Evan Cheng722cd122010-09-08 22:57:08 +0000[diff] [blame]303
Evan Chenge37da032010-09-24 22:41:41 +0000[diff] [blame]304 //
305 // iLoadi + iALUr for t2LDRpci_pic.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]306 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]307 InstrStage<1, [A9_MUX0], 0>,
308 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]309 InstrStage<1, [A9_LSUnit]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]310 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]311 [2, 1]>,
Evan Chenge37da032010-09-24 22:41:41 +0000[diff] [blame]312
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]313 // Integer store pipeline
314 ///
315 // Immediate offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]316 InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]317 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]318 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]319 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]320 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]321 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]322 InstrStage<2, [A9_AGU], 1>,
323 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]324 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]325 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]326 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]327 InstrStage<2, [A9_AGU], 1>,
328 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]329 //
330 // Register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]331 InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]332 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]333 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]334 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]335 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]336 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]337 InstrStage<2, [A9_AGU], 1>,
338 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]339 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]340 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]341 InstrStage<2, [A9_AGU], 1>,
342 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]343 //
344 // Scaled register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]345 InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
346 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]347 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]348 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]349 InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]350 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]351 InstrStage<2, [A9_AGU], 1>,
352 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]353 //
354 // Immediate offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]355 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
356 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]357 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]358 InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]359 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]360 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]361 InstrStage<2, [A9_AGU], 1>,
362 InstrStage<1, [A9_LSUnit]>], [3, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]363 //
364 // Register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]365 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
366 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]367 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]368 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]369 [2, 1, 1, 1]>,
370 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]371 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]372 InstrStage<2, [A9_AGU], 1>,
373 InstrStage<1, [A9_LSUnit]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]374 [3, 1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]375 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
376 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]377 InstrStage<2, [A9_AGU], 1>,
378 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]379 [3, 1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]380 //
381 // Scaled register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]382 InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
383 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]384 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]385 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]386 [2, 1, 1, 1]>,
387 InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
388 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]389 InstrStage<2, [A9_AGU], 1>,
390 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]391 [3, 1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]392 //
393 // Store multiple
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]394 InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]395 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]396 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]397 InstrStage<2, [A9_LSUnit]>]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]398 //
399 // Store multiple + update
400 InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
401 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]402 InstrStage<1, [A9_AGU]>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]403 InstrStage<2, [A9_LSUnit]>], [2]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]404
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]405 // Branch
406 //
407 // no delay slots, so the latency of a branch is unimportant
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]408 InstrItinData<IIC_Br , [InstrStage<1, [A9_Issue0], 0>,
409 InstrStage<1, [A9_Issue1], 0>,
410 InstrStage<1, [A9_Branch]>]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]411
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]412 // VFP and NEON shares the same register file. This means that every VFP
413 // instruction should wait for full completion of the consecutive NEON
414 // instruction and vice-versa. We model this behavior with two artificial FUs:
415 // DRegsVFP and DRegsVFP.
416 //
417 // Every VFP instruction:
418 // - Acquires DRegsVFP resource for 1 cycle
419 // - Reserves DRegsN resource for the whole duration (including time to
420 // register file writeback!).
421 // Every NEON instruction does the same but with FUs swapped.
422 //
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]423 // Since the reserved FU cannot be acquired, this models precisely
424 // "cross-domain" stalls.
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]425
426 // VFP
427 // Issue through integer pipeline, and execute in NEON unit.
428
429 // FP Special Register to Integer Register File Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]430 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]431 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]432 InstrStage<1, [A9_DRegsVFP], 0, Required>,
433 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng99cce362010-10-29 23:16:55 +0000[diff] [blame]434 InstrStage<1, [A9_NPipe]>],
435 [1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]436 //
437 // Single-precision FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]438 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
439 InstrStage<1, [A9_MUX0], 0>,
440 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]441 // Extra latency cycles since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]442 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]443 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]444 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]445 //
446 // Double-precision FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]447 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
448 InstrStage<1, [A9_MUX0], 0>,
449 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]450 // Extra latency cycles since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]451 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]452 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]453 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]454
455 //
456 // Single-precision FP Compare
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]457 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
458 InstrStage<1, [A9_MUX0], 0>,
459 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]460 // Extra latency cycles since wbck is 4 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]461 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]462 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]463 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]464 //
465 // Double-precision FP Compare
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]466 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
467 InstrStage<1, [A9_MUX0], 0>,
468 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]469 // Extra latency cycles since wbck is 4 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]470 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]471 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]472 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]473 //
474 // Single to Double FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]475 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]476 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]477 InstrStage<1, [A9_DRegsVFP], 0, Required>,
478 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]479 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]480 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]481 //
482 // Double to Single FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]483 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]484 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]485 InstrStage<1, [A9_DRegsVFP], 0, Required>,
486 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]487 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]488 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]489
490 //
491 // Single to Half FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]492 InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]493 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]494 InstrStage<1, [A9_DRegsVFP], 0, Required>,
495 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]496 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]497 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]498 //
499 // Half to Single FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]500 InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]501 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]502 InstrStage<1, [A9_DRegsVFP], 0, Required>,
503 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]504 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]505 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]506
507 //
508 // Single-Precision FP to Integer Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]509 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]510 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]511 InstrStage<1, [A9_DRegsVFP], 0, Required>,
512 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]513 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]514 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]515 //
516 // Double-Precision FP to Integer Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]517 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]518 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]519 InstrStage<1, [A9_DRegsVFP], 0, Required>,
520 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]521 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]522 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]523 //
524 // Integer to Single-Precision FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]525 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]526 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]527 InstrStage<1, [A9_DRegsVFP], 0, Required>,
528 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]529 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]530 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]531 //
532 // Integer to Double-Precision FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]533 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]534 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]535 InstrStage<1, [A9_DRegsVFP], 0, Required>,
536 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]537 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]538 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]539 //
540 // Single-precision FP ALU
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]541 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]542 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]543 InstrStage<1, [A9_DRegsVFP], 0, Required>,
544 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]545 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]546 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]547 //
548 // Double-precision FP ALU
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]549 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]550 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]551 InstrStage<1, [A9_DRegsVFP], 0, Required>,
552 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]553 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]554 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]555 //
556 // Single-precision FP Multiply
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]557 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]558 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]559 InstrStage<1, [A9_DRegsVFP], 0, Required>,
560 InstrStage<6, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]561 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]562 [5, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]563 //
564 // Double-precision FP Multiply
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]565 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]566 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]567 InstrStage<1, [A9_DRegsVFP], 0, Required>,
568 InstrStage<7, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]569 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]570 [6, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]571 //
572 // Single-precision FP MAC
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]573 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]574 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]575 InstrStage<1, [A9_DRegsVFP], 0, Required>,
576 InstrStage<9, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]577 InstrStage<1, [A9_NPipe]>],
Evan Chengff310732010-10-28 06:47:08 +0000[diff] [blame]578 [8, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]579 //
580 // Double-precision FP MAC
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]581 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]582 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]583 InstrStage<1, [A9_DRegsVFP], 0, Required>,
584 InstrStage<10, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]585 InstrStage<2, [A9_NPipe]>],
Evan Chengff310732010-10-28 06:47:08 +0000[diff] [blame]586 [9, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]587 //
588 // Single-precision FP DIV
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]589 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]590 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]591 InstrStage<1, [A9_DRegsVFP], 0, Required>,
592 InstrStage<16, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]593 InstrStage<10, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]594 [15, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]595 //
596 // Double-precision FP DIV
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]597 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]598 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]599 InstrStage<1, [A9_DRegsVFP], 0, Required>,
600 InstrStage<26, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]601 InstrStage<20, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]602 [25, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]603 //
604 // Single-precision FP SQRT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]605 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]606 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]607 InstrStage<1, [A9_DRegsVFP], 0, Required>,
608 InstrStage<18, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]609 InstrStage<13, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]610 [17, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]611 //
612 // Double-precision FP SQRT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]613 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]614 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]615 InstrStage<1, [A9_DRegsVFP], 0, Required>,
616 InstrStage<33, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]617 InstrStage<28, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]618 [32, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]619
620 //
621 // Integer to Single-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]622 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
623 InstrStage<1, [A9_MUX0], 0>,
624 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]625 // Extra 1 latency cycle since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]626 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]627 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]628 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]629 //
630 // Integer to Double-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]631 InstrItinData<IIC_fpMOVID, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
632 InstrStage<1, [A9_MUX0], 0>,
633 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]634 // Extra 1 latency cycle since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]635 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]636 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]637 [1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]638 //
639 // Single-precision to Integer Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]640 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]641 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]642 InstrStage<1, [A9_DRegsVFP], 0, Required>,
643 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]644 InstrStage<1, [A9_NPipe]>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]645 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]646 //
647 // Double-precision to Integer Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]648 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]649 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]650 InstrStage<1, [A9_DRegsVFP], 0, Required>,
651 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]652 InstrStage<1, [A9_NPipe]>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]653 [2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]654 //
655 // Single-precision FP Load
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]656 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]657 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]658 InstrStage<1, [A9_DRegsVFP], 0, Required>,
659 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]660 InstrStage<1, [A9_NPipe]>,
661 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]662 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]663 //
664 // Double-precision FP Load
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]665 // FIXME: Result latency is 1 if address is 64-bit aligned.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]666 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]667 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]668 InstrStage<1, [A9_DRegsVFP], 0, Required>,
669 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]670 InstrStage<1, [A9_NPipe]>,
671 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]672 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]673 //
674 // FP Load Multiple
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]675 InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]676 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]677 InstrStage<1, [A9_DRegsVFP], 0, Required>,
678 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]679 InstrStage<1, [A9_NPipe]>,
680 InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]681 //
682 // FP Load Multiple + update
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]683 InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]684 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]685 InstrStage<1, [A9_DRegsVFP], 0, Required>,
686 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]687 InstrStage<1, [A9_NPipe]>,
688 InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]689 //
690 // Single-precision FP Store
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]691 InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]692 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]693 InstrStage<1, [A9_DRegsVFP], 0, Required>,
694 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]695 InstrStage<1, [A9_NPipe]>,
696 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]697 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]698 //
699 // Double-precision FP Store
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]700 InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]701 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]702 InstrStage<1, [A9_DRegsVFP], 0, Required>,
703 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]704 InstrStage<1, [A9_NPipe]>,
705 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]706 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]707 //
708 // FP Store Multiple
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]709 InstrItinData<IIC_fpStore_m,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]710 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]711 InstrStage<1, [A9_DRegsVFP], 0, Required>,
712 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]713 InstrStage<1, [A9_NPipe]>,
714 InstrStage<1, [A9_LSUnit]>], [1, 1, 1, 1]>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]715 //
716 // FP Store Multiple + update
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]717 InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]718 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]719 InstrStage<1, [A9_DRegsVFP], 0, Required>,
720 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]721 InstrStage<1, [A9_NPipe]>,
722 InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]723 // NEON
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]724 // VLD1
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]725 // FIXME: Conservatively assume insufficent alignment.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]726 InstrItinData<IIC_VLD1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]727 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]728 InstrStage<1, [A9_DRegsN], 0, Required>,
729 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]730 InstrStage<2, [A9_NPipe], 1>,
731 InstrStage<2, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]732 [2, 1]>,
733 // VLD1x2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]734 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]735 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]736 InstrStage<1, [A9_DRegsN], 0, Required>,
737 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]738 InstrStage<2, [A9_NPipe], 1>,
739 InstrStage<2, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]740 [2, 2, 1]>,
741 // VLD1x3
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]742 InstrItinData<IIC_VLD1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]743 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]744 InstrStage<1, [A9_DRegsN], 0, Required>,
745 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]746 InstrStage<3, [A9_NPipe], 1>,
747 InstrStage<3, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]748 [2, 2, 3, 1]>,
749 // VLD1x4
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]750 InstrItinData<IIC_VLD1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]751 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]752 InstrStage<1, [A9_DRegsN], 0, Required>,
753 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]754 InstrStage<3, [A9_NPipe], 1>,
755 InstrStage<3, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]756 [2, 2, 3, 3, 1]>,
757 // VLD1u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]758 InstrItinData<IIC_VLD1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]759 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]760 InstrStage<1, [A9_DRegsN], 0, Required>,
761 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]762 InstrStage<2, [A9_NPipe], 1>,
763 InstrStage<2, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]764 [2, 2, 1]>,
765 // VLD1x2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]766 InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]767 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]768 InstrStage<1, [A9_DRegsN], 0, Required>,
769 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]770 InstrStage<2, [A9_NPipe], 1>,
771 InstrStage<2, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]772 [2, 2, 2, 1]>,
773 // VLD1x3u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]774 InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]775 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]776 InstrStage<1, [A9_DRegsN], 0, Required>,
777 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]778 InstrStage<3, [A9_NPipe], 1>,
779 InstrStage<3, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]780 [2, 2, 3, 2, 1]>,
781 // VLD1x4u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]782 InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]783 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]784 InstrStage<1, [A9_DRegsN], 0, Required>,
785 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]786 InstrStage<3, [A9_NPipe], 1>,
787 InstrStage<3, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]788 [2, 2, 3, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]789 //
Bob Wilsondc449902010-11-01 22:04:05 +0000[diff] [blame^]790 // VLD1ln
791 InstrItinData<IIC_VLD1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
792 InstrStage<1, [A9_MUX0], 0>,
793 InstrStage<1, [A9_DRegsN], 0, Required>,
794 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
795 InstrStage<3, [A9_NPipe], 1>,
796 InstrStage<3, [A9_LSUnit]>],
797 [4, 1, 1, 1]>,
798 //
799 // VLD1lnu
800 InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
801 InstrStage<1, [A9_MUX0], 0>,
802 InstrStage<1, [A9_DRegsN], 0, Required>,
803 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
804 InstrStage<3, [A9_NPipe], 1>,
805 InstrStage<3, [A9_LSUnit]>],
806 [4, 2, 1, 1, 1, 1]>,
807 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]808 // VLD2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]809 InstrItinData<IIC_VLD2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
810 InstrStage<1, [A9_MUX0], 0>,
811 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]812 // Extra latency cycles since wbck is 7 cycles
813 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]814 InstrStage<2, [A9_NPipe], 1>,
815 InstrStage<2, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]816 [3, 3, 1]>,
817 //
818 // VLD2x2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]819 InstrItinData<IIC_VLD2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]820 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]821 InstrStage<1, [A9_DRegsN], 0, Required>,
822 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]823 InstrStage<3, [A9_NPipe], 1>,
824 InstrStage<3, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]825 [3, 4, 3, 4, 1]>,
826 //
827 // VLD2ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]828 InstrItinData<IIC_VLD2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]829 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]830 InstrStage<1, [A9_DRegsN], 0, Required>,
831 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]832 InstrStage<3, [A9_NPipe], 1>,
833 InstrStage<3, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]834 [4, 4, 1, 1, 1, 1]>,
835 //
836 // VLD2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]837 InstrItinData<IIC_VLD2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
838 InstrStage<1, [A9_MUX0], 0>,
839 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]840 // Extra latency cycles since wbck is 7 cycles
841 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]842 InstrStage<2, [A9_NPipe], 1>,
843 InstrStage<2, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]844 [3, 3, 2, 1, 1, 1]>,
845 //
846 // VLD2x2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]847 InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]848 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]849 InstrStage<1, [A9_DRegsN], 0, Required>,
850 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]851 InstrStage<3, [A9_NPipe], 1>,
852 InstrStage<3, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]853 [3, 4, 3, 4, 2, 1]>,
854 //
855 // VLD2lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]856 InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]857 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]858 InstrStage<1, [A9_DRegsN], 0, Required>,
859 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]860 InstrStage<3, [A9_NPipe], 1>,
861 InstrStage<3, [A9_LSUnit]>],
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]862 [4, 4, 2, 1, 1, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]863 //
864 // VLD3
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]865 InstrItinData<IIC_VLD3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]866 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]867 InstrStage<1, [A9_DRegsN], 0, Required>,
868 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]869 InstrStage<4, [A9_NPipe], 1>,
870 InstrStage<4, [A9_LSUnit]>],
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]871 [4, 4, 5, 1]>,
872 //
873 // VLD3ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]874 InstrItinData<IIC_VLD3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]875 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]876 InstrStage<1, [A9_DRegsN], 0, Required>,
877 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]878 InstrStage<5, [A9_NPipe], 1>,
879 InstrStage<5, [A9_LSUnit]>],
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]880 [5, 5, 6, 1, 1, 1, 1, 2]>,
881 //
882 // VLD3u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]883 InstrItinData<IIC_VLD3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]884 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]885 InstrStage<1, [A9_DRegsN], 0, Required>,
886 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]887 InstrStage<4, [A9_NPipe], 1>,
888 InstrStage<4, [A9_LSUnit]>],
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]889 [4, 4, 5, 2, 1]>,
890 //
891 // VLD3lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]892 InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]893 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]894 InstrStage<1, [A9_DRegsN], 0, Required>,
895 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]896 InstrStage<5, [A9_NPipe], 1>,
897 InstrStage<5, [A9_LSUnit]>],
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]898 [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]899 //
900 // VLD4
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]901 InstrItinData<IIC_VLD4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]902 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]903 InstrStage<1, [A9_DRegsN], 0, Required>,
904 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]905 InstrStage<4, [A9_NPipe], 1>,
906 InstrStage<4, [A9_LSUnit]>],
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]907 [4, 4, 5, 5, 1]>,
908 //
909 // VLD4ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]910 InstrItinData<IIC_VLD4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]911 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]912 InstrStage<1, [A9_DRegsN], 0, Required>,
913 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]914 InstrStage<5, [A9_NPipe], 1>,
915 InstrStage<5, [A9_LSUnit]>],
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]916 [5, 5, 6, 6, 1, 1, 1, 1, 2, 2]>,
917 //
918 // VLD4u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]919 InstrItinData<IIC_VLD4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]920 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]921 InstrStage<1, [A9_DRegsN], 0, Required>,
922 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]923 InstrStage<4, [A9_NPipe], 1>,
924 InstrStage<4, [A9_LSUnit]>],
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]925 [4, 4, 5, 5, 2, 1]>,
926 //
927 // VLD4lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]928 InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]929 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]930 InstrStage<1, [A9_DRegsN], 0, Required>,
931 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]932 InstrStage<5, [A9_NPipe], 1>,
933 InstrStage<5, [A9_LSUnit]>],
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]934 [5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]935 //
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]936 // VST1
937 InstrItinData<IIC_VST1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]938 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]939 InstrStage<1, [A9_DRegsN], 0, Required>,
940 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]941 InstrStage<2, [A9_NPipe], 1>,
942 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]943 [1, 1, 1]>,
944 //
945 // VST1x2
946 InstrItinData<IIC_VST1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
947 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]948 InstrStage<1, [A9_DRegsN], 0, Required>,
949 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]950 InstrStage<2, [A9_NPipe], 1>,
951 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]952 [1, 1, 1, 1]>,
953 //
954 // VST1x3
955 InstrItinData<IIC_VST1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
956 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]957 InstrStage<1, [A9_DRegsN], 0, Required>,
958 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]959 InstrStage<3, [A9_NPipe], 1>,
960 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]961 [1, 1, 1, 1, 2]>,
962 //
963 // VST1x4
964 InstrItinData<IIC_VST1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
965 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]966 InstrStage<1, [A9_DRegsN], 0, Required>,
967 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]968 InstrStage<3, [A9_NPipe], 1>,
969 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]970 [1, 1, 1, 1, 2, 2]>,
971 //
972 // VST1u
973 InstrItinData<IIC_VST1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
974 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]975 InstrStage<1, [A9_DRegsN], 0, Required>,
976 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]977 InstrStage<2, [A9_NPipe], 1>,
978 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]979 [2, 1, 1, 1, 1]>,
980 //
981 // VST1x2u
982 InstrItinData<IIC_VST1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
983 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]984 InstrStage<1, [A9_DRegsN], 0, Required>,
985 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]986 InstrStage<2, [A9_NPipe], 1>,
987 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]988 [2, 1, 1, 1, 1, 1]>,
989 //
990 // VST1x3u
991 InstrItinData<IIC_VST1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
992 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]993 InstrStage<1, [A9_DRegsN], 0, Required>,
994 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]995 InstrStage<3, [A9_NPipe], 1>,
996 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]997 [2, 1, 1, 1, 1, 1, 2]>,
998 //
999 // VST1x4u
1000 InstrItinData<IIC_VST1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1001 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1002 InstrStage<1, [A9_DRegsN], 0, Required>,
1003 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1004 InstrStage<3, [A9_NPipe], 1>,
1005 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1006 [2, 1, 1, 1, 1, 1, 2, 2]>,
1007 //
1008 // VST2
1009 InstrItinData<IIC_VST2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1010 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1011 InstrStage<1, [A9_DRegsN], 0, Required>,
1012 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1013 InstrStage<2, [A9_NPipe], 1>,
1014 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1015 [1, 1, 1, 1]>,
1016 //
1017 // VST2x2
1018 InstrItinData<IIC_VST2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1019 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1020 InstrStage<1, [A9_DRegsN], 0, Required>,
1021 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1022 InstrStage<3, [A9_NPipe], 1>,
1023 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1024 [1, 1, 1, 1, 2, 2]>,
1025 //
1026 // VST2u
1027 InstrItinData<IIC_VST2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1028 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1029 InstrStage<1, [A9_DRegsN], 0, Required>,
1030 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1031 InstrStage<2, [A9_NPipe], 1>,
1032 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1033 [2, 1, 1, 1, 1, 1]>,
1034 //
1035 // VST2x2u
1036 InstrItinData<IIC_VST2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1037 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1038 InstrStage<1, [A9_DRegsN], 0, Required>,
1039 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1040 InstrStage<3, [A9_NPipe], 1>,
1041 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1042 [2, 1, 1, 1, 1, 1, 2, 2]>,
1043 //
1044 // VST2ln
1045 InstrItinData<IIC_VST2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1046 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1047 InstrStage<1, [A9_DRegsN], 0, Required>,
1048 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1049 InstrStage<2, [A9_NPipe], 1>,
1050 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1051 [1, 1, 1, 1]>,
1052 //
1053 // VST2lnu
1054 InstrItinData<IIC_VST2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1055 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1056 InstrStage<1, [A9_DRegsN], 0, Required>,
1057 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1058 InstrStage<3, [A9_NPipe], 1>,
1059 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1060 [2, 1, 1, 1, 1, 1]>,
1061 //
1062 // VST3
1063 InstrItinData<IIC_VST3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1064 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1065 InstrStage<1, [A9_DRegsN], 0, Required>,
1066 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1067 InstrStage<3, [A9_NPipe], 1>,
1068 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1069 [1, 1, 1, 1, 2]>,
1070 //
1071 // VST3u
1072 InstrItinData<IIC_VST3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1073 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1074 InstrStage<1, [A9_DRegsN], 0, Required>,
1075 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1076 InstrStage<3, [A9_NPipe], 1>,
1077 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1078 [2, 1, 1, 1, 1, 1, 2]>,
1079 //
1080 // VST3ln
1081 InstrItinData<IIC_VST3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1082 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1083 InstrStage<1, [A9_DRegsN], 0, Required>,
1084 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1085 InstrStage<3, [A9_NPipe], 1>,
1086 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1087 [1, 1, 1, 1, 2]>,
1088 //
1089 // VST3lnu
1090 InstrItinData<IIC_VST3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1091 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1092 InstrStage<1, [A9_DRegsN], 0, Required>,
1093 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1094 InstrStage<3, [A9_NPipe], 1>,
1095 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1096 [2, 1, 1, 1, 1, 1, 2]>,
1097 //
1098 // VST4
1099 InstrItinData<IIC_VST4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1100 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1101 InstrStage<1, [A9_DRegsN], 0, Required>,
1102 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1103 InstrStage<3, [A9_NPipe], 1>,
1104 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1105 [1, 1, 1, 1, 2, 2]>,
1106 //
1107 // VST4u
1108 InstrItinData<IIC_VST4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1109 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1110 InstrStage<1, [A9_DRegsN], 0, Required>,
1111 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1112 InstrStage<3, [A9_NPipe], 1>,
1113 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1114 [2, 1, 1, 1, 1, 1, 2, 2]>,
1115 //
1116 // VST4ln
1117 InstrItinData<IIC_VST4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1118 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1119 InstrStage<1, [A9_DRegsN], 0, Required>,
1120 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1121 InstrStage<3, [A9_NPipe], 1>,
1122 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1123 [1, 1, 1, 1, 2, 2]>,
1124 //
1125 // VST4lnu
1126 InstrItinData<IIC_VST4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1127 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1128 InstrStage<1, [A9_DRegsN], 0, Required>,
1129 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1130 InstrStage<3, [A9_NPipe], 1>,
1131 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1132 [2, 1, 1, 1, 1, 1, 2, 2]>,
1133
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1134 //
1135 // Double-register Integer Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1136 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1137 InstrStage<1, [A9_MUX0], 0>,
1138 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1139 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1140 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1141 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1142 [4, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1143 //
1144 // Quad-register Integer Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1145 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1146 InstrStage<1, [A9_MUX0], 0>,
1147 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1148 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1149 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1150 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1151 [4, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1152 //
1153 // Double-register Integer Q-Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1154 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1155 InstrStage<1, [A9_MUX0], 0>,
1156 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1157 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1158 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1159 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1160 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1161 //
1162 // Quad-register Integer CountQ-Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1163 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1164 InstrStage<1, [A9_MUX0], 0>,
1165 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1166 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1167 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1168 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1169 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1170 //
1171 // Double-register Integer Binary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1172 InstrItinData<IIC_VBINiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1173 InstrStage<1, [A9_MUX0], 0>,
1174 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1175 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1176 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1177 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1178 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1179 //
1180 // Quad-register Integer Binary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1181 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1182 InstrStage<1, [A9_MUX0], 0>,
1183 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1184 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1185 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1186 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1187 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1188 //
1189 // Double-register Integer Subtract
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1190 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1191 InstrStage<1, [A9_MUX0], 0>,
1192 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1193 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1194 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1195 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1196 [3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1197 //
1198 // Quad-register Integer Subtract
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1199 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1200 InstrStage<1, [A9_MUX0], 0>,
1201 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1202 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1203 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1204 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1205 [3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1206 //
1207 // Double-register Integer Shift
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1208 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1209 InstrStage<1, [A9_MUX0], 0>,
1210 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1211 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1212 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1213 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1214 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1215 //
1216 // Quad-register Integer Shift
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1217 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1218 InstrStage<1, [A9_MUX0], 0>,
1219 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1220 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1221 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1222 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1223 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1224 //
1225 // Double-register Integer Shift (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1226 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1227 InstrStage<1, [A9_MUX0], 0>,
1228 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1229 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1230 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1231 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1232 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1233 //
1234 // Quad-register Integer Shift (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1235 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1236 InstrStage<1, [A9_MUX0], 0>,
1237 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1238 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1239 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1240 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1241 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1242 //
1243 // Double-register Integer Binary (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1244 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1245 InstrStage<1, [A9_MUX0], 0>,
1246 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1247 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1248 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1249 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1250 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1251 //
1252 // Quad-register Integer Binary (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1253 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1254 InstrStage<1, [A9_MUX0], 0>,
1255 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1256 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1257 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1258 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1259 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1260 //
1261 // Double-register Integer Subtract (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1262 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1263 InstrStage<1, [A9_MUX0], 0>,
1264 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1265 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1266 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1267 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1268 [4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1269 //
1270 // Quad-register Integer Subtract (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1271 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1272 InstrStage<1, [A9_MUX0], 0>,
1273 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1274 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1275 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1276 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1277 [4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1278
1279 //
1280 // Double-register Integer Count
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1281 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1282 InstrStage<1, [A9_MUX0], 0>,
1283 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1284 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1285 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1286 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1287 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1288 //
1289 // Quad-register Integer Count
1290 // Result written in N3, but that is relative to the last cycle of multicycle,
1291 // so we use 4 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1292 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1293 InstrStage<1, [A9_MUX0], 0>,
1294 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1295 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1296 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1297 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1298 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1299 //
1300 // Double-register Absolute Difference and Accumulate
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1301 InstrItinData<IIC_VABAD, [InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]1302 InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1303 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1304 InstrStage<1, [A9_DRegsN], 0, Required>,
1305 // Extra latency cycles since wbck is 6 cycles
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1306 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1307 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1308 //
1309 // Quad-register Absolute Difference and Accumulate
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1310 InstrItinData<IIC_VABAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1311 InstrStage<1, [A9_MUX0], 0>,
1312 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1313 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1314 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1315 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1316 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1317 //
1318 // Double-register Integer Pair Add Long
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1319 InstrItinData<IIC_VPALiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1320 InstrStage<1, [A9_MUX0], 0>,
1321 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1322 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1323 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1324 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1325 [6, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1326 //
1327 // Quad-register Integer Pair Add Long
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1328 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1329 InstrStage<1, [A9_MUX0], 0>,
1330 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1331 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1332 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1333 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1334 [6, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1335
1336 //
1337 // Double-register Integer Multiply (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1338 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1339 InstrStage<1, [A9_MUX0], 0>,
1340 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1341 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1342 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1343 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1344 [6, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1345 //
1346 // Quad-register Integer Multiply (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1347 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1348 InstrStage<1, [A9_MUX0], 0>,
1349 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1350 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1351 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1352 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1353 [7, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1354
1355 //
1356 // Double-register Integer Multiply (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1357 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1358 InstrStage<1, [A9_MUX0], 0>,
1359 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1360 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1361 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1362 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1363 [7, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1364 //
1365 // Quad-register Integer Multiply (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1366 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1367 InstrStage<1, [A9_MUX0], 0>,
1368 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1369 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1370 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1371 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1372 [9, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1373 //
1374 // Double-register Integer Multiply-Accumulate (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1375 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1376 InstrStage<1, [A9_MUX0], 0>,
1377 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1378 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1379 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1380 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1381 [6, 3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1382 //
1383 // Double-register Integer Multiply-Accumulate (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1384 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1385 InstrStage<1, [A9_MUX0], 0>,
1386 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1387 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1388 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1389 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1390 [7, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1391 //
1392 // Quad-register Integer Multiply-Accumulate (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1393 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1394 InstrStage<1, [A9_MUX0], 0>,
1395 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1396 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1397 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1398 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1399 [7, 3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1400 //
1401 // Quad-register Integer Multiply-Accumulate (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1402 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1403 InstrStage<1, [A9_MUX0], 0>,
1404 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1405 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1406 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1407 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1408 [9, 3, 2, 1]>,
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1409
1410 //
1411 // Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1412 InstrItinData<IIC_VMOV, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1413 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1414 InstrStage<1, [A9_DRegsN], 0, Required>,
1415 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1416 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1417 [1,1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1418 //
1419 // Move Immediate
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1420 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1421 InstrStage<1, [A9_MUX0], 0>,
1422 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1423 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1424 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1425 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1426 [3]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1427 //
1428 // Double-register Permute Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1429 InstrItinData<IIC_VMOVD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1430 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1431 InstrStage<1, [A9_DRegsN], 0, Required>,
1432 // Extra latency cycles since wbck is 6 cycles
1433 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1434 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1435 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1436 //
1437 // Quad-register Permute Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1438 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1439 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1440 InstrStage<1, [A9_DRegsN], 0, Required>,
1441 // Extra latency cycles since wbck is 6 cycles
1442 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1443 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1444 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1445 //
1446 // Integer to Single-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1447 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1448 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1449 InstrStage<1, [A9_DRegsN], 0, Required>,
1450 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1451 InstrStage<1, [A9_NPipe]>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]1452 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1453 //
1454 // Integer to Double-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1455 InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1456 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1457 InstrStage<1, [A9_DRegsN], 0, Required>,
1458 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1459 InstrStage<1, [A9_NPipe]>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]1460 [1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1461 //
1462 // Single-precision to Integer Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1463 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1464 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1465 InstrStage<1, [A9_DRegsN], 0, Required>,
1466 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1467 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1468 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1469 //
1470 // Double-precision to Integer Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1471 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1472 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1473 InstrStage<1, [A9_DRegsN], 0, Required>,
1474 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1475 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1476 [2, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1477 //
1478 // Integer to Lane Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1479 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1480 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1481 InstrStage<1, [A9_DRegsN], 0, Required>,
1482 InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1483 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1484 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1485
1486 //
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1487 // Vector narrow move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1488 InstrItinData<IIC_VMOVN, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1489 InstrStage<1, [A9_MUX0], 0>,
1490 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1491 // Extra latency cycles since wbck is 6 cycles
1492 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1493 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1494 [3, 1]>,
1495 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1496 // Double-register FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1497 InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1498 InstrStage<1, [A9_MUX0], 0>,
1499 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1500 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1501 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1502 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1503 [5, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1504 //
1505 // Quad-register FP Unary
1506 // Result written in N5, but that is relative to the last cycle of multicycle,
1507 // so we use 6 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1508 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1509 InstrStage<1, [A9_MUX0], 0>,
1510 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1511 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1512 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1513 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1514 [6, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1515 //
1516 // Double-register FP Binary
1517 // FIXME: We're using this itin for many instructions and [2, 2] here is too
1518 // optimistic.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1519 InstrItinData<IIC_VBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1520 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1521 InstrStage<1, [A9_DRegsN], 0, Required>,
1522 // Extra latency cycles since wbck is 6 cycles
1523 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1524 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1525 [5, 2, 2]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1526
1527 //
1528 // VPADD, etc.
1529 InstrItinData<IIC_VPBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1530 InstrStage<1, [A9_MUX0], 0>,
1531 InstrStage<1, [A9_DRegsN], 0, Required>,
1532 // Extra latency cycles since wbck is 6 cycles
1533 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1534 InstrStage<1, [A9_NPipe]>],
1535 [5, 1, 1]>,
1536 //
1537 // Double-register FP VMUL
1538 InstrItinData<IIC_VFMULD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1539 InstrStage<1, [A9_MUX0], 0>,
1540 InstrStage<1, [A9_DRegsN], 0, Required>,
1541 // Extra latency cycles since wbck is 6 cycles
1542 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1543 InstrStage<1, [A9_NPipe]>],
1544 [5, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1545 //
1546 // Quad-register FP Binary
1547 // Result written in N5, but that is relative to the last cycle of multicycle,
1548 // so we use 6 for those cases
1549 // FIXME: We're using this itin for many instructions and [2, 2] here is too
1550 // optimistic.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1551 InstrItinData<IIC_VBINQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1552 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1553 InstrStage<1, [A9_DRegsN], 0, Required>,
1554 // Extra latency cycles since wbck is 7 cycles
1555 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1556 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1557 [6, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1558 //
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1559 // Quad-register FP VMUL
1560 InstrItinData<IIC_VFMULQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1561 InstrStage<1, [A9_MUX0], 0>,
1562 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1563 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1564 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1565 InstrStage<1, [A9_NPipe]>],
1566 [6, 2, 1]>,
1567 //
1568 // Double-register FP Multiple-Accumulate
1569 InstrItinData<IIC_VMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1570 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1571 InstrStage<1, [A9_DRegsN], 0, Required>,
1572 // Extra latency cycles since wbck is 7 cycles
1573 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1574 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1575 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1576 //
1577 // Quad-register FP Multiple-Accumulate
1578 // Result written in N9, but that is relative to the last cycle of multicycle,
1579 // so we use 10 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1580 InstrItinData<IIC_VMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1581 InstrStage<1, [A9_MUX0], 0>,
1582 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1583 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1584 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1585 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1586 [8, 4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1587 //
1588 // Double-register Reciprical Step
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1589 InstrItinData<IIC_VRECSD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1590 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1591 InstrStage<1, [A9_DRegsN], 0, Required>,
1592 // Extra latency cycles since wbck is 10 cycles
1593 InstrStage<11, [A9_DRegsVFP], 0, Reserved>,
1594 InstrStage<1, [A9_NPipe]>],
1595 [9, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1596 //
1597 // Quad-register Reciprical Step
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1598 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1599 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1600 InstrStage<1, [A9_DRegsN], 0, Required>,
1601 // Extra latency cycles since wbck is 11 cycles
1602 InstrStage<12, [A9_DRegsVFP], 0, Reserved>,
1603 InstrStage<2, [A9_NPipe]>],
1604 [10, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1605 //
1606 // Double-register Permute
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1607 InstrItinData<IIC_VPERMD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1608 InstrStage<1, [A9_MUX0], 0>,
1609 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1610 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1611 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1612 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1613 [2, 2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1614 //
1615 // Quad-register Permute
1616 // Result written in N2, but that is relative to the last cycle of multicycle,
1617 // so we use 3 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1618 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1619 InstrStage<1, [A9_MUX0], 0>,
1620 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1621 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1622 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1623 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1624 [3, 3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1625 //
1626 // Quad-register Permute (3 cycle issue)
1627 // Result written in N2, but that is relative to the last cycle of multicycle,
1628 // so we use 4 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1629 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1630 InstrStage<1, [A9_MUX0], 0>,
1631 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1632 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1633 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1634 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1635 [4, 4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1636
1637 //
1638 // Double-register VEXT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1639 InstrItinData<IIC_VEXTD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1640 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1641 InstrStage<1, [A9_DRegsN], 0, Required>,
1642 // Extra latency cycles since wbck is 6 cycles
1643 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1644 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1645 [2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1646 //
1647 // Quad-register VEXT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1648 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1649 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1650 InstrStage<1, [A9_DRegsN], 0, Required>,
1651 // Extra latency cycles since wbck is 7 cycles
1652 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1653 InstrStage<2, [A9_NPipe]>],
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1654 [3, 1, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1655 //
1656 // VTB
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1657 InstrItinData<IIC_VTB1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1658 InstrStage<1, [A9_MUX0], 0>,
1659 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1660 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1661 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1662 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1663 [3, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1664 InstrItinData<IIC_VTB2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1665 InstrStage<1, [A9_MUX0], 0>,
1666 InstrStage<2, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1667 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1668 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1669 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1670 [3, 2, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1671 InstrItinData<IIC_VTB3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1672 InstrStage<1, [A9_MUX0], 0>,
1673 InstrStage<2, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1674 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1675 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1676 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1677 [4, 2, 2, 3, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1678 InstrItinData<IIC_VTB4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1679 InstrStage<1, [A9_MUX0], 0>,
1680 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1681 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1682 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1683 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1684 [4, 2, 2, 3, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1685 //
1686 // VTBX
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1687 InstrItinData<IIC_VTBX1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1688 InstrStage<1, [A9_MUX0], 0>,
1689 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1690 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1691 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1692 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1693 [3, 1, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1694 InstrItinData<IIC_VTBX2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1695 InstrStage<1, [A9_MUX0], 0>,
1696 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1697 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1698 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1699 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1700 [3, 1, 2, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1701 InstrItinData<IIC_VTBX3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1702 InstrStage<1, [A9_MUX0], 0>,
1703 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1704 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1705 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1706 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1707 [4, 1, 2, 2, 3, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1708 InstrItinData<IIC_VTBX4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1709 InstrStage<1, [A9_MUX0], 0>,
1710 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1711 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1712 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1713 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1714 [4, 1, 2, 2, 3, 3, 1]>
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1715]>;