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gerrit-public.fairphone.software / toolchain / llvm-project / dda8015434c41fcad81c49dee581666b05c40a08 / . / llvm / lib / Target / AMDGPU / AMDGPULegalizerInfo.h
blob: 4b6a971a4fd84461ea6792971cba640faa1c5cfd [file] [log] [blame]
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]1//===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +0000[diff] [blame]3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the Machinelegalizer class for
10/// AMDGPU.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16
17#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
Matt Arsenaulte2c86cc2019-07-01 18:45:36 +0000[diff] [blame]18#include "AMDGPUArgumentUsageInfo.h"
Matt Arsenault77ac4002019-10-01 01:06:43 +0000[diff] [blame]19#include "SIInstrInfo.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]20
21namespace llvm {
22
Matt Arsenaultc3fe46b2018-03-08 16:24:16 +0000[diff] [blame]23class GCNTargetMachine;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]24class LLVMContext;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]25class GCNSubtarget;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]26
27/// This class provides the information for the target register banks.
28class AMDGPULegalizerInfo : public LegalizerInfo {
Matt Arsenault9e8e8c62019-07-01 18:49:01 +0000[diff] [blame]29 const GCNSubtarget &ST;
30
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]31public:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]32 AMDGPULegalizerInfo(const GCNSubtarget &ST,
Matt Arsenaultc3fe46b2018-03-08 16:24:16 +0000[diff] [blame]33 const GCNTargetMachine &TM);
Matt Arsenaulta8b43392019-02-08 02:40:47 +0000[diff] [blame]34
35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]36 MachineIRBuilder &B,
Matt Arsenaulta8b43392019-02-08 02:40:47 +0000[diff] [blame]37 GISelChangeObserver &Observer) const override;
38
Matt Arsenault1178dc32019-06-28 01:16:46 +0000[diff] [blame]39 Register getSegmentAperture(unsigned AddrSpace,
Matt Arsenaulta8b43392019-02-08 02:40:47 +0000[diff] [blame]40 MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]41 MachineIRBuilder &B) const;
Matt Arsenaulta8b43392019-02-08 02:40:47 +0000[diff] [blame]42
43 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]44 MachineIRBuilder &B) const;
Matt Arsenault6aafc5e2019-05-17 12:19:57 +0000[diff] [blame]45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]46 MachineIRBuilder &B) const;
Matt Arsenaulta510b572019-05-17 12:20:05 +0000[diff] [blame]47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]48 MachineIRBuilder &B) const;
Matt Arsenault6aebcd52019-05-17 12:20:01 +0000[diff] [blame]49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]50 MachineIRBuilder &B) const;
Matt Arsenault2f292202019-05-17 23:05:18 +0000[diff] [blame]51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]52 MachineIRBuilder &B, bool Signed) const;
Matt Arsenault6ce1b4f2019-07-10 16:31:19 +0000[diff] [blame]53 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]54 MachineIRBuilder &B) const;
Matt Arsenaultb0e04c02019-07-15 19:40:59 +0000[diff] [blame]55 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]56 MachineIRBuilder &B) const;
Matt Arsenault6ed315f2019-07-15 19:43:04 +0000[diff] [blame]57 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]58 MachineIRBuilder &B) const;
Matt Arsenaultcbd17822019-08-29 20:06:48 +0000[diff] [blame]59 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]60 MachineIRBuilder &B) const;
Matt Arsenaulte15770a2019-07-01 18:40:23 +0000[diff] [blame]61
Matt Arsenault77ac4002019-10-01 01:06:43 +0000[diff] [blame]62 bool buildPCRelGlobalAddress(
63 Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
64 unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
65
Matt Arsenault64ecca92019-09-09 17:13:44 +0000[diff] [blame]66 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]67 MachineIRBuilder &B) const;
Matt Arsenaultad6a8b832019-09-10 16:42:31 +0000[diff] [blame]68 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
69 MachineIRBuilder &B,
70 GISelChangeObserver &Observer) const;
Matt Arsenault64ecca92019-09-09 17:13:44 +0000[diff] [blame]71
Matt Arsenault4d339182019-09-13 00:44:35 +0000[diff] [blame]72 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
73 MachineIRBuilder &B) const;
74
Matt Arsenault171cf532019-10-08 10:04:41 -0700[diff] [blame]75 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
76 MachineIRBuilder &B) const;
77
Matt Arsenaulte2c86cc2019-07-01 18:45:36 +0000[diff] [blame]78 Register getLiveInRegister(MachineRegisterInfo &MRI,
79 Register Reg, LLT Ty) const;
80
81 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
82 const ArgDescriptor *Arg) const;
83 bool legalizePreloadedArgIntrin(
84 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
85 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
86
Austin Kerbow97263fa2019-10-21 22:18:26 +0000[diff] [blame]87 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
88 MachineIRBuilder &B) const;
Austin Kerbowc35b3582019-10-22 17:39:26 -0700[diff] [blame]89 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
90 MachineIRBuilder &B) const;
Austin Kerbow2b88b342019-10-29 09:55:49 -0700[diff] [blame]91 bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
92 MachineIRBuilder &B) const;
Austin Kerbow97263fa2019-10-21 22:18:26 +0000[diff] [blame]93 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
94 MachineIRBuilder &B) const;
95 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
96 MachineIRBuilder &B) const;
Austin Kerbowc99f62e2019-07-30 18:49:16 +0000[diff] [blame]97
Matt Arsenault9e8e8c62019-07-01 18:49:01 +0000[diff] [blame]98 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
99 MachineIRBuilder &B) const;
Matt Arsenaultf581d572019-09-05 02:20:39 +0000[diff] [blame]100 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
101 MachineIRBuilder &B, unsigned AddrSpace) const;
Matt Arsenault3ecab8e2019-09-19 16:26:14 +0000[diff] [blame]102
103 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
104 Register Reg) const;
105 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
106 MachineIRBuilder &B, bool IsFormat) const;
Matt Arsenaulte15770a2019-07-01 18:40:23 +0000[diff] [blame]107 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
Austin Kerbow06c8cb02019-09-09 23:06:13 +0000[diff] [blame]108 MachineIRBuilder &B) const override;
Matt Arsenaulte15770a2019-07-01 18:40:23 +0000[diff] [blame]109
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]110};
111} // End llvm namespace.
112#endif