blob: 242f05d3bc46d4fc784d04af77f2255dbf6b19db [file] [log] [blame]
Tom Stellard49f8bfd2015-01-06 18:00:21 +00001; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s
2; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +00003
4declare i32 @llvm.SI.tid() nounwind readnone
Matt Arsenault2aed6ca2015-12-19 01:46:41 +00005declare void @llvm.AMDGPU.barrier.local() nounwind convergent
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +00006
7; The required pointer calculations for the alloca'd actually requires
8; an add and won't be folded into the addressing, which fails with a
9; 64-bit pointer add. This should work since private pointers should
10; be 32-bits.
11
Tom Stellard79243d92014-10-01 17:15:17 +000012; SI-LABEL: {{^}}test_private_array_ptr_calc:
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +000013
Tom Stellardb02094e2014-07-21 15:45:01 +000014; FIXME: We end up with zero argument for ADD, because
15; SIRegisterInfo::eliminateFrameIndex() blindly replaces the frame index
16; with the appropriate offset. We should fold this into the store.
Matt Arsenaulte4d0c142015-08-29 07:16:50 +000017; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 0, v{{[0-9]+}}
Tom Stellard326d6ec2014-11-05 14:50:53 +000018; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}]
Tom Stellard880a80a2014-06-17 16:53:14 +000019;
20; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
21; alloca to a vector. It currently fails because it does not know how
22; to interpret:
Matt Arsenaultde420812016-02-02 21:16:12 +000023; getelementptr inbounds [4 x i32], [4 x i32]* %alloca, i32 1, i32 %b
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +000024
Matt Arsenaulte4d0c142015-08-29 07:16:50 +000025; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 16
Tom Stellard326d6ec2014-11-05 14:50:53 +000026; SI-PROMOTE: ds_write_b32 [[PTRREG]]
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +000027define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
28 %alloca = alloca [4 x i32], i32 4, align 16
29 %tid = call i32 @llvm.SI.tid() readnone
Matt Arsenaultde420812016-02-02 21:16:12 +000030 %a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid
31 %b_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inB, i32 %tid
David Blaikiea79ac142015-02-27 21:17:42 +000032 %a = load i32, i32 addrspace(1)* %a_ptr
33 %b = load i32, i32 addrspace(1)* %b_ptr
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +000034 %result = add i32 %a, %b
Matt Arsenaultde420812016-02-02 21:16:12 +000035 %alloca_ptr = getelementptr inbounds [4 x i32], [4 x i32]* %alloca, i32 1, i32 %b
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +000036 store i32 %result, i32* %alloca_ptr, align 4
37 ; Dummy call
Matt Arsenault2aed6ca2015-12-19 01:46:41 +000038 call void @llvm.AMDGPU.barrier.local() nounwind convergent
David Blaikiea79ac142015-02-27 21:17:42 +000039 %reload = load i32, i32* %alloca_ptr, align 4
Matt Arsenaultde420812016-02-02 21:16:12 +000040 %out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
Matt Arsenaulta98cd6a2013-12-19 05:32:55 +000041 store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
42 ret void
43}
44