| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 1 | //===-- DSInstructions.td - DS Instruction Defintions ---------------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> : |
| 11 | InstSI <outs, ins, "", pattern>, |
| 12 | SIMCInstr <opName, SIEncodingFamily.NONE> { |
| 13 | |
| 14 | let SubtargetPredicate = isGCN; |
| 15 | |
| 16 | let LGKM_CNT = 1; |
| 17 | let DS = 1; |
| Matt Arsenault | 10c17ca | 2016-10-06 10:13:23 +0000 | [diff] [blame] | 18 | let Size = 8; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 19 | let UseNamedOperandTable = 1; |
| 20 | let Uses = [M0, EXEC]; |
| 21 | |
| 22 | // Most instruction load and store data, so set this as the default. |
| 23 | let mayLoad = 1; |
| 24 | let mayStore = 1; |
| 25 | |
| 26 | let hasSideEffects = 0; |
| 27 | let SchedRW = [WriteLDS]; |
| 28 | |
| 29 | let isPseudo = 1; |
| 30 | let isCodeGenOnly = 1; |
| 31 | |
| 32 | let AsmMatchConverter = "cvtDS"; |
| 33 | |
| 34 | string Mnemonic = opName; |
| 35 | string AsmOperands = asmOps; |
| 36 | |
| 37 | // Well these bits a kind of hack because it would be more natural |
| 38 | // to test "outs" and "ins" dags for the presence of particular operands |
| 39 | bits<1> has_vdst = 1; |
| 40 | bits<1> has_addr = 1; |
| 41 | bits<1> has_data0 = 1; |
| 42 | bits<1> has_data1 = 1; |
| 43 | |
| 44 | bits<1> has_offset = 1; // has "offset" that should be split to offset0,1 |
| 45 | bits<1> has_offset0 = 1; |
| 46 | bits<1> has_offset1 = 1; |
| 47 | |
| 48 | bits<1> has_gds = 1; |
| 49 | bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value |
| 50 | } |
| 51 | |
| 52 | class DS_Real <DS_Pseudo ds> : |
| 53 | InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>, |
| 54 | Enc64 { |
| 55 | |
| 56 | let isPseudo = 0; |
| 57 | let isCodeGenOnly = 0; |
| 58 | |
| 59 | // copy relevant pseudo op flags |
| 60 | let SubtargetPredicate = ds.SubtargetPredicate; |
| 61 | let AsmMatchConverter = ds.AsmMatchConverter; |
| 62 | |
| 63 | // encoding fields |
| 64 | bits<8> vdst; |
| 65 | bits<1> gds; |
| 66 | bits<8> addr; |
| 67 | bits<8> data0; |
| 68 | bits<8> data1; |
| 69 | bits<8> offset0; |
| 70 | bits<8> offset1; |
| 71 | |
| 72 | bits<16> offset; |
| 73 | let offset0 = !if(ds.has_offset, offset{7-0}, ?); |
| 74 | let offset1 = !if(ds.has_offset, offset{15-8}, ?); |
| 75 | } |
| 76 | |
| 77 | |
| 78 | // DS Pseudo instructions |
| 79 | |
| 80 | class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32> |
| 81 | : DS_Pseudo<opName, |
| 82 | (outs), |
| 83 | (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), |
| 84 | "$addr, $data0$offset$gds">, |
| 85 | AtomicNoRet<opName, 0> { |
| 86 | |
| 87 | let has_data1 = 0; |
| 88 | let has_vdst = 0; |
| 89 | } |
| 90 | |
| 91 | class DS_1A_Off8_NORET<string opName> : DS_Pseudo<opName, |
| 92 | (outs), |
| 93 | (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds), |
| 94 | "$addr $offset0$offset1$gds"> { |
| 95 | |
| 96 | let has_data0 = 0; |
| 97 | let has_data1 = 0; |
| 98 | let has_vdst = 0; |
| 99 | let has_offset = 0; |
| 100 | let AsmMatchConverter = "cvtDSOffset01"; |
| 101 | } |
| 102 | |
| Matt Arsenault | f3dd863 | 2016-11-01 00:55:14 +0000 | [diff] [blame] | 103 | class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32> |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 104 | : DS_Pseudo<opName, |
| 105 | (outs), |
| 106 | (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds), |
| 107 | "$addr, $data0, $data1"#"$offset"#"$gds">, |
| 108 | AtomicNoRet<opName, 0> { |
| 109 | |
| 110 | let has_vdst = 0; |
| 111 | } |
| 112 | |
| 113 | class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32> |
| 114 | : DS_Pseudo<opName, |
| 115 | (outs), |
| 116 | (ins VGPR_32:$addr, rc:$data0, rc:$data1, |
| 117 | offset0:$offset0, offset1:$offset1, gds:$gds), |
| 118 | "$addr, $data0, $data1$offset0$offset1$gds"> { |
| 119 | |
| 120 | let has_vdst = 0; |
| 121 | let has_offset = 0; |
| 122 | let AsmMatchConverter = "cvtDSOffset01"; |
| 123 | } |
| 124 | |
| 125 | class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32> |
| 126 | : DS_Pseudo<opName, |
| 127 | (outs rc:$vdst), |
| 128 | (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), |
| 129 | "$vdst, $addr, $data0$offset$gds"> { |
| 130 | |
| 131 | let hasPostISelHook = 1; |
| 132 | let has_data1 = 0; |
| 133 | } |
| 134 | |
| 135 | class DS_1A2D_RET<string opName, |
| Matt Arsenault | f3dd863 | 2016-11-01 00:55:14 +0000 | [diff] [blame] | 136 | RegisterClass rc = VGPR_32, |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 137 | RegisterClass src = rc> |
| 138 | : DS_Pseudo<opName, |
| 139 | (outs rc:$vdst), |
| 140 | (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds), |
| 141 | "$vdst, $addr, $data0, $data1$offset$gds"> { |
| 142 | |
| 143 | let hasPostISelHook = 1; |
| 144 | } |
| 145 | |
| 146 | class DS_1A_RET<string opName, RegisterClass rc = VGPR_32> |
| 147 | : DS_Pseudo<opName, |
| 148 | (outs rc:$vdst), |
| Matt Arsenault | f3dd863 | 2016-11-01 00:55:14 +0000 | [diff] [blame] | 149 | (ins VGPR_32:$addr, offset:$offset, gds:$gds), |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 150 | "$vdst, $addr$offset$gds"> { |
| 151 | |
| 152 | let has_data0 = 0; |
| 153 | let has_data1 = 0; |
| 154 | } |
| 155 | |
| 156 | class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32> |
| 157 | : DS_Pseudo<opName, |
| 158 | (outs rc:$vdst), |
| 159 | (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds), |
| 160 | "$vdst, $addr$offset0$offset1$gds"> { |
| 161 | |
| 162 | let has_offset = 0; |
| 163 | let has_data0 = 0; |
| 164 | let has_data1 = 0; |
| 165 | let AsmMatchConverter = "cvtDSOffset01"; |
| 166 | } |
| 167 | |
| 168 | class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName, |
| 169 | (outs VGPR_32:$vdst), |
| 170 | (ins VGPR_32:$addr, offset:$offset), |
| 171 | "$vdst, $addr$offset gds"> { |
| 172 | |
| 173 | let has_data0 = 0; |
| 174 | let has_data1 = 0; |
| 175 | let has_gds = 0; |
| 176 | let gdsValue = 1; |
| Artem Tamazov | 43b6156 | 2017-02-03 12:47:30 +0000 | [diff] [blame] | 177 | let AsmMatchConverter = "cvtDSGds"; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | class DS_0A_RET <string opName> : DS_Pseudo<opName, |
| 181 | (outs VGPR_32:$vdst), |
| 182 | (ins offset:$offset, gds:$gds), |
| 183 | "$vdst$offset$gds"> { |
| 184 | |
| 185 | let mayLoad = 1; |
| 186 | let mayStore = 1; |
| 187 | |
| 188 | let has_addr = 0; |
| 189 | let has_data0 = 0; |
| 190 | let has_data1 = 0; |
| 191 | } |
| 192 | |
| 193 | class DS_1A <string opName> : DS_Pseudo<opName, |
| 194 | (outs), |
| 195 | (ins VGPR_32:$addr, offset:$offset, gds:$gds), |
| 196 | "$addr$offset$gds"> { |
| 197 | |
| 198 | let mayLoad = 1; |
| 199 | let mayStore = 1; |
| 200 | |
| 201 | let has_vdst = 0; |
| 202 | let has_data0 = 0; |
| 203 | let has_data1 = 0; |
| 204 | } |
| 205 | |
| 206 | class DS_1A_GDS <string opName> : DS_Pseudo<opName, |
| 207 | (outs), |
| 208 | (ins VGPR_32:$addr), |
| 209 | "$addr gds"> { |
| 210 | |
| Matt Arsenault | f3dd863 | 2016-11-01 00:55:14 +0000 | [diff] [blame] | 211 | let has_vdst = 0; |
| 212 | let has_data0 = 0; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 213 | let has_data1 = 0; |
| 214 | let has_offset = 0; |
| 215 | let has_offset0 = 0; |
| 216 | let has_offset1 = 0; |
| 217 | |
| Matt Arsenault | f3dd863 | 2016-11-01 00:55:14 +0000 | [diff] [blame] | 218 | let has_gds = 0; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 219 | let gdsValue = 1; |
| 220 | } |
| 221 | |
| 222 | class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag> |
| 223 | : DS_Pseudo<opName, |
| 224 | (outs VGPR_32:$vdst), |
| 225 | (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset), |
| 226 | "$vdst, $addr, $data0$offset", |
| 227 | [(set i32:$vdst, |
| 228 | (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > { |
| 229 | |
| 230 | let mayLoad = 0; |
| 231 | let mayStore = 0; |
| 232 | let isConvergent = 1; |
| 233 | |
| 234 | let has_data1 = 0; |
| 235 | let has_gds = 0; |
| 236 | } |
| 237 | |
| 238 | def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">; |
| 239 | def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">; |
| 240 | def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">; |
| 241 | def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">; |
| 242 | def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">; |
| 243 | def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">; |
| 244 | def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">; |
| 245 | def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">; |
| 246 | def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">; |
| 247 | def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">; |
| 248 | def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">; |
| 249 | def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">; |
| Artem Tamazov | 2e217b8 | 2016-09-21 16:35:44 +0000 | [diff] [blame] | 250 | def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">; |
| Artem Tamazov | 751985a | 2016-10-21 14:49:22 +0000 | [diff] [blame] | 251 | def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">; |
| 252 | def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 253 | |
| 254 | let mayLoad = 0 in { |
| 255 | def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">; |
| 256 | def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">; |
| 257 | def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">; |
| 258 | def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">; |
| 259 | def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">; |
| 260 | } |
| 261 | |
| 262 | def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">; |
| 263 | def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">; |
| 264 | def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 265 | |
| 266 | def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>; |
| 267 | def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>; |
| 268 | def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>; |
| 269 | def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>; |
| 270 | def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>; |
| 271 | def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>; |
| 272 | def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>; |
| 273 | def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>; |
| 274 | def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>; |
| 275 | def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>; |
| 276 | def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>; |
| 277 | def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>; |
| 278 | def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>; |
| 279 | let mayLoad = 0 in { |
| 280 | def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>; |
| 281 | def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>; |
| 282 | def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>; |
| 283 | } |
| 284 | def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>; |
| 285 | def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>; |
| 286 | def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>; |
| 287 | def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>; |
| 288 | |
| 289 | def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">, |
| 290 | AtomicNoRet<"ds_add_u32", 1>; |
| Artem Tamazov | 2e217b8 | 2016-09-21 16:35:44 +0000 | [diff] [blame] | 291 | def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">, |
| 292 | AtomicNoRet<"ds_add_f32", 1>; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 293 | def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">, |
| 294 | AtomicNoRet<"ds_sub_u32", 1>; |
| 295 | def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">, |
| 296 | AtomicNoRet<"ds_rsub_u32", 1>; |
| 297 | def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">, |
| 298 | AtomicNoRet<"ds_inc_u32", 1>; |
| 299 | def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">, |
| 300 | AtomicNoRet<"ds_dec_u32", 1>; |
| 301 | def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">, |
| 302 | AtomicNoRet<"ds_min_i32", 1>; |
| 303 | def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">, |
| 304 | AtomicNoRet<"ds_max_i32", 1>; |
| 305 | def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">, |
| 306 | AtomicNoRet<"ds_min_u32", 1>; |
| 307 | def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">, |
| 308 | AtomicNoRet<"ds_max_u32", 1>; |
| 309 | def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">, |
| 310 | AtomicNoRet<"ds_and_b32", 1>; |
| 311 | def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">, |
| 312 | AtomicNoRet<"ds_or_b32", 1>; |
| 313 | def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">, |
| 314 | AtomicNoRet<"ds_xor_b32", 1>; |
| 315 | def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">, |
| 316 | AtomicNoRet<"ds_mskor_b32", 1>; |
| 317 | def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">, |
| 318 | AtomicNoRet<"ds_cmpst_b32", 1>; |
| 319 | def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">, |
| 320 | AtomicNoRet<"ds_cmpst_f32", 1>; |
| Artem Tamazov | 751985a | 2016-10-21 14:49:22 +0000 | [diff] [blame] | 321 | def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">, |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 322 | AtomicNoRet<"ds_min_f32", 1>; |
| Artem Tamazov | 751985a | 2016-10-21 14:49:22 +0000 | [diff] [blame] | 323 | def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">, |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 324 | AtomicNoRet<"ds_max_f32", 1>; |
| 325 | |
| 326 | def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">, |
| 327 | AtomicNoRet<"", 1>; |
| 328 | def DS_WRXCHG2_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>, |
| 329 | AtomicNoRet<"", 1>; |
| 330 | def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>, |
| 331 | AtomicNoRet<"", 1>; |
| 332 | |
| 333 | def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>, |
| 334 | AtomicNoRet<"ds_add_u64", 1>; |
| 335 | def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>, |
| 336 | AtomicNoRet<"ds_sub_u64", 1>; |
| 337 | def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>, |
| 338 | AtomicNoRet<"ds_rsub_u64", 1>; |
| 339 | def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>, |
| 340 | AtomicNoRet<"ds_inc_u64", 1>; |
| 341 | def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>, |
| 342 | AtomicNoRet<"ds_dec_u64", 1>; |
| 343 | def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>, |
| 344 | AtomicNoRet<"ds_min_i64", 1>; |
| 345 | def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>, |
| 346 | AtomicNoRet<"ds_max_i64", 1>; |
| 347 | def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>, |
| 348 | AtomicNoRet<"ds_min_u64", 1>; |
| 349 | def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>, |
| 350 | AtomicNoRet<"ds_max_u64", 1>; |
| 351 | def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>, |
| 352 | AtomicNoRet<"ds_and_b64", 1>; |
| 353 | def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>, |
| 354 | AtomicNoRet<"ds_or_b64", 1>; |
| 355 | def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>, |
| 356 | AtomicNoRet<"ds_xor_b64", 1>; |
| 357 | def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>, |
| 358 | AtomicNoRet<"ds_mskor_b64", 1>; |
| 359 | def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>, |
| 360 | AtomicNoRet<"ds_cmpst_b64", 1>; |
| 361 | def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>, |
| 362 | AtomicNoRet<"ds_cmpst_f64", 1>; |
| 363 | def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>, |
| 364 | AtomicNoRet<"ds_min_f64", 1>; |
| 365 | def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>, |
| 366 | AtomicNoRet<"ds_max_f64", 1>; |
| 367 | |
| 368 | def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>, |
| 369 | AtomicNoRet<"ds_wrxchg_b64", 1>; |
| 370 | def DS_WRXCHG2_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>, |
| 371 | AtomicNoRet<"ds_wrxchg2_b64", 1>; |
| 372 | def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>, |
| 373 | AtomicNoRet<"ds_wrxchg2st64_b64", 1>; |
| 374 | |
| 375 | def DS_GWS_INIT : DS_1A_GDS<"ds_gws_init">; |
| 376 | def DS_GWS_SEMA_V : DS_1A_GDS<"ds_gws_sema_v">; |
| 377 | def DS_GWS_SEMA_BR : DS_1A_GDS<"ds_gws_sema_br">; |
| 378 | def DS_GWS_SEMA_P : DS_1A_GDS<"ds_gws_sema_p">; |
| 379 | def DS_GWS_BARRIER : DS_1A_GDS<"ds_gws_barrier">; |
| 380 | |
| 381 | def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">; |
| 382 | def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">; |
| 383 | def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">; |
| 384 | def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">; |
| 385 | def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">; |
| 386 | def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">; |
| 387 | def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">; |
| 388 | def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">; |
| 389 | def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">; |
| 390 | def DS_AND_SRC2_B32 : DS_1A<"ds_and_src_b32">; |
| 391 | def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">; |
| 392 | def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">; |
| 393 | def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">; |
| 394 | def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">; |
| 395 | |
| 396 | def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">; |
| 397 | def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">; |
| 398 | def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">; |
| 399 | def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">; |
| 400 | def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">; |
| 401 | def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">; |
| 402 | def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">; |
| 403 | def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">; |
| 404 | def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">; |
| 405 | def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">; |
| 406 | def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">; |
| 407 | def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">; |
| 408 | def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">; |
| 409 | def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">; |
| 410 | |
| 411 | def DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET<"ds_write_src2_b32">; |
| 412 | def DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET<"ds_write_src2_b64">; |
| 413 | |
| 414 | let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in { |
| 415 | def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">; |
| 416 | } |
| 417 | |
| 418 | let mayStore = 0 in { |
| 419 | def DS_READ_I8 : DS_1A_RET<"ds_read_i8">; |
| 420 | def DS_READ_U8 : DS_1A_RET<"ds_read_u8">; |
| 421 | def DS_READ_I16 : DS_1A_RET<"ds_read_i16">; |
| 422 | def DS_READ_U16 : DS_1A_RET<"ds_read_u16">; |
| 423 | def DS_READ_B32 : DS_1A_RET<"ds_read_b32">; |
| 424 | def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>; |
| 425 | |
| 426 | def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>; |
| 427 | def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>; |
| 428 | |
| 429 | def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>; |
| 430 | def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>; |
| 431 | } |
| 432 | |
| 433 | let SubtargetPredicate = isSICI in { |
| 434 | def DS_CONSUME : DS_0A_RET<"ds_consume">; |
| 435 | def DS_APPEND : DS_0A_RET<"ds_append">; |
| 436 | def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">; |
| 437 | } |
| 438 | |
| 439 | //===----------------------------------------------------------------------===// |
| 440 | // Instruction definitions for CI and newer. |
| 441 | //===----------------------------------------------------------------------===// |
| 442 | // Remaining instructions: |
| 443 | // DS_NOP |
| 444 | // DS_GWS_SEMA_RELEASE_ALL |
| 445 | // DS_WRAP_RTN_B32 |
| 446 | // DS_CNDXCHG32_RTN_B64 |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 447 | // DS_CONDXCHG32_RTN_B128 |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 448 | |
| 449 | let SubtargetPredicate = isCIVI in { |
| 450 | |
| 451 | def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">, |
| 452 | AtomicNoRet<"ds_wrap_f32", 1>; |
| 453 | |
| Matt Arsenault | dedc544 | 2017-02-28 20:15:43 +0000 | [diff] [blame^] | 454 | let mayStore = 0 in { |
| 455 | def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>; |
| 456 | def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>; |
| 457 | } // End mayStore = 0 |
| 458 | |
| 459 | let mayLoad = 0 in { |
| 460 | def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>; |
| 461 | def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>; |
| 462 | } // End mayLoad = 0 |
| 463 | |
| 464 | |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 465 | } // let SubtargetPredicate = isCIVI |
| 466 | |
| 467 | //===----------------------------------------------------------------------===// |
| 468 | // Instruction definitions for VI and newer. |
| 469 | //===----------------------------------------------------------------------===// |
| 470 | |
| 471 | let SubtargetPredicate = isVI in { |
| 472 | |
| 473 | let Uses = [EXEC] in { |
| 474 | def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32", |
| 475 | int_amdgcn_ds_permute>; |
| 476 | def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32", |
| 477 | int_amdgcn_ds_bpermute>; |
| 478 | } |
| 479 | |
| 480 | } // let SubtargetPredicate = isVI |
| 481 | |
| 482 | //===----------------------------------------------------------------------===// |
| 483 | // DS Patterns |
| 484 | //===----------------------------------------------------------------------===// |
| 485 | |
| 486 | let Predicates = [isGCN] in { |
| 487 | |
| 488 | def : Pat < |
| 489 | (int_amdgcn_ds_swizzle i32:$src, imm:$offset16), |
| 490 | (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0)) |
| 491 | >; |
| 492 | |
| 493 | class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat < |
| 494 | (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), |
| 495 | (inst $ptr, (as_i16imm $offset), (i1 0)) |
| 496 | >; |
| 497 | |
| 498 | def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>; |
| 499 | def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>; |
| Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 500 | def : DSReadPat <DS_READ_I8, i16, si_sextload_local_i8>; |
| 501 | def : DSReadPat <DS_READ_U8, i16, si_az_extload_local_i8>; |
| 502 | def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 503 | def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>; |
| 504 | def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>; |
| Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 505 | def : DSReadPat <DS_READ_U16, i16, si_load_local>; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 506 | def : DSReadPat <DS_READ_B32, i32, si_load_local>; |
| 507 | |
| 508 | let AddedComplexity = 100 in { |
| 509 | |
| 510 | def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>; |
| 511 | |
| 512 | } // End AddedComplexity = 100 |
| 513 | |
| 514 | def : Pat < |
| 515 | (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, |
| 516 | i8:$offset1))), |
| 517 | (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0)) |
| 518 | >; |
| 519 | |
| 520 | class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat < |
| 521 | (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)), |
| 522 | (inst $ptr, $value, (as_i16imm $offset), (i1 0)) |
| 523 | >; |
| 524 | |
| 525 | def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>; |
| 526 | def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>; |
| Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 527 | def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>; |
| 528 | def : DSWritePat <DS_WRITE_B16, i16, si_store_local>; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 529 | def : DSWritePat <DS_WRITE_B32, i32, si_store_local>; |
| 530 | |
| 531 | let AddedComplexity = 100 in { |
| 532 | |
| 533 | def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>; |
| 534 | } // End AddedComplexity = 100 |
| 535 | |
| 536 | def : Pat < |
| 537 | (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, |
| 538 | i8:$offset1)), |
| Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 539 | (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)), |
| 540 | (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1, |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 541 | (i1 0)) |
| 542 | >; |
| 543 | |
| 544 | class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat < |
| 545 | (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), |
| 546 | (inst $ptr, $value, (as_i16imm $offset), (i1 0)) |
| 547 | >; |
| 548 | |
| 549 | class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat < |
| 550 | (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap), |
| 551 | (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0)) |
| 552 | >; |
| 553 | |
| 554 | |
| 555 | // 32-bit atomics. |
| 556 | def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>; |
| 557 | def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>; |
| 558 | def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>; |
| 559 | def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>; |
| 560 | def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>; |
| 561 | def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>; |
| 562 | def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>; |
| 563 | def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>; |
| 564 | def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>; |
| 565 | def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>; |
| 566 | def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>; |
| 567 | def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>; |
| 568 | def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>; |
| 569 | |
| 570 | // 64-bit atomics. |
| 571 | def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>; |
| 572 | def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>; |
| 573 | def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>; |
| 574 | def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>; |
| 575 | def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>; |
| 576 | def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>; |
| 577 | def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>; |
| 578 | def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>; |
| 579 | def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>; |
| 580 | def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>; |
| 581 | def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>; |
| 582 | def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>; |
| 583 | |
| 584 | def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>; |
| 585 | |
| 586 | } // let Predicates = [isGCN] |
| 587 | |
| 588 | //===----------------------------------------------------------------------===// |
| 589 | // Real instructions |
| 590 | //===----------------------------------------------------------------------===// |
| 591 | |
| 592 | //===----------------------------------------------------------------------===// |
| 593 | // SIInstructions.td |
| 594 | //===----------------------------------------------------------------------===// |
| 595 | |
| 596 | class DS_Real_si <bits<8> op, DS_Pseudo ds> : |
| 597 | DS_Real <ds>, |
| 598 | SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> { |
| 599 | let AssemblerPredicates=[isSICI]; |
| 600 | let DecoderNamespace="SICI"; |
| 601 | |
| 602 | // encoding |
| 603 | let Inst{7-0} = !if(ds.has_offset0, offset0, 0); |
| 604 | let Inst{15-8} = !if(ds.has_offset1, offset1, 0); |
| 605 | let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue); |
| 606 | let Inst{25-18} = op; |
| 607 | let Inst{31-26} = 0x36; // ds prefix |
| 608 | let Inst{39-32} = !if(ds.has_addr, addr, 0); |
| 609 | let Inst{47-40} = !if(ds.has_data0, data0, 0); |
| 610 | let Inst{55-48} = !if(ds.has_data1, data1, 0); |
| 611 | let Inst{63-56} = !if(ds.has_vdst, vdst, 0); |
| 612 | } |
| 613 | |
| 614 | def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>; |
| 615 | def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>; |
| 616 | def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>; |
| 617 | def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>; |
| 618 | def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>; |
| 619 | def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>; |
| 620 | def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>; |
| 621 | def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>; |
| 622 | def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>; |
| 623 | def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>; |
| 624 | def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>; |
| 625 | def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>; |
| 626 | def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>; |
| 627 | def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>; |
| 628 | def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>; |
| 629 | def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>; |
| 630 | def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>; |
| 631 | def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>; |
| 632 | def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>; |
| 633 | def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>; |
| 634 | def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>; |
| 635 | def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>; |
| 636 | def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>; |
| 637 | def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>; |
| 638 | def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>; |
| 639 | def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>; |
| 640 | def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>; |
| 641 | def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>; |
| 642 | def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>; |
| 643 | def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>; |
| 644 | def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>; |
| 645 | def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>; |
| 646 | def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>; |
| 647 | def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>; |
| 648 | def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>; |
| 649 | def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>; |
| 650 | def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>; |
| 651 | def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>; |
| 652 | def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>; |
| 653 | def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>; |
| 654 | def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>; |
| 655 | def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>; |
| 656 | def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>; |
| 657 | def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>; |
| 658 | def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>; |
| 659 | def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>; |
| 660 | def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>; |
| 661 | |
| 662 | // FIXME: this instruction is actually CI/VI |
| 663 | def DS_WRAP_RTN_F32_si : DS_Real_si<0x34, DS_WRAP_RTN_F32>; |
| 664 | |
| 665 | def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>; |
| 666 | def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>; |
| 667 | def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>; |
| 668 | def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>; |
| 669 | def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>; |
| 670 | def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>; |
| 671 | def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>; |
| 672 | def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>; |
| 673 | def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>; |
| 674 | def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>; |
| 675 | def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>; |
| 676 | def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>; |
| 677 | def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>; |
| 678 | def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>; |
| 679 | def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>; |
| 680 | def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>; |
| 681 | def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>; |
| 682 | def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>; |
| 683 | def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>; |
| 684 | def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>; |
| 685 | def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>; |
| 686 | def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>; |
| 687 | def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>; |
| 688 | def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>; |
| 689 | def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>; |
| 690 | def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>; |
| 691 | def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>; |
| 692 | def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>; |
| 693 | def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>; |
| 694 | def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>; |
| 695 | def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>; |
| 696 | |
| 697 | def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>; |
| 698 | def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>; |
| 699 | def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>; |
| 700 | def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>; |
| 701 | def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>; |
| 702 | def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>; |
| 703 | def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>; |
| 704 | def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>; |
| 705 | def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>; |
| 706 | def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>; |
| 707 | def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>; |
| 708 | def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>; |
| 709 | def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>; |
| 710 | def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>; |
| 711 | def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>; |
| 712 | def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>; |
| 713 | def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>; |
| 714 | def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>; |
| 715 | def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>; |
| 716 | def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>; |
| 717 | |
| 718 | def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>; |
| 719 | def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>; |
| 720 | def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>; |
| 721 | |
| 722 | def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>; |
| 723 | def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>; |
| 724 | def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>; |
| 725 | def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>; |
| 726 | def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>; |
| 727 | def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>; |
| 728 | def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>; |
| 729 | def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>; |
| 730 | def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>; |
| 731 | def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>; |
| 732 | def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>; |
| 733 | def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>; |
| 734 | def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>; |
| 735 | |
| 736 | def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>; |
| 737 | def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>; |
| 738 | |
| 739 | def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>; |
| 740 | def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>; |
| 741 | def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>; |
| 742 | def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>; |
| 743 | def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>; |
| 744 | def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>; |
| 745 | def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>; |
| 746 | def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>; |
| 747 | def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>; |
| 748 | def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>; |
| 749 | def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>; |
| 750 | def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>; |
| 751 | def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>; |
| 752 | |
| 753 | def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>; |
| 754 | def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>; |
| Matt Arsenault | dedc544 | 2017-02-28 20:15:43 +0000 | [diff] [blame^] | 755 | def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>; |
| 756 | def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>; |
| 757 | def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>; |
| 758 | def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 759 | |
| 760 | //===----------------------------------------------------------------------===// |
| 761 | // VIInstructions.td |
| 762 | //===----------------------------------------------------------------------===// |
| 763 | |
| 764 | class DS_Real_vi <bits<8> op, DS_Pseudo ds> : |
| 765 | DS_Real <ds>, |
| 766 | SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> { |
| 767 | let AssemblerPredicates = [isVI]; |
| 768 | let DecoderNamespace="VI"; |
| 769 | |
| Matt Arsenault | f3dd863 | 2016-11-01 00:55:14 +0000 | [diff] [blame] | 770 | // encoding |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 771 | let Inst{7-0} = !if(ds.has_offset0, offset0, 0); |
| 772 | let Inst{15-8} = !if(ds.has_offset1, offset1, 0); |
| 773 | let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue); |
| 774 | let Inst{24-17} = op; |
| 775 | let Inst{31-26} = 0x36; // ds prefix |
| 776 | let Inst{39-32} = !if(ds.has_addr, addr, 0); |
| 777 | let Inst{47-40} = !if(ds.has_data0, data0, 0); |
| 778 | let Inst{55-48} = !if(ds.has_data1, data1, 0); |
| 779 | let Inst{63-56} = !if(ds.has_vdst, vdst, 0); |
| 780 | } |
| 781 | |
| 782 | def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>; |
| 783 | def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>; |
| 784 | def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>; |
| 785 | def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>; |
| 786 | def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>; |
| 787 | def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>; |
| 788 | def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>; |
| 789 | def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>; |
| 790 | def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>; |
| 791 | def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>; |
| 792 | def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>; |
| 793 | def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>; |
| 794 | def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>; |
| 795 | def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>; |
| 796 | def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>; |
| 797 | def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>; |
| 798 | def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>; |
| 799 | def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>; |
| 800 | def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>; |
| 801 | def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>; |
| Artem Tamazov | 2e217b8 | 2016-09-21 16:35:44 +0000 | [diff] [blame] | 802 | def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 803 | def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>; |
| 804 | def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>; |
| 805 | def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>; |
| 806 | def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>; |
| 807 | def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>; |
| 808 | def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>; |
| 809 | def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>; |
| 810 | def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>; |
| 811 | def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>; |
| 812 | def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>; |
| 813 | def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>; |
| 814 | def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>; |
| 815 | def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>; |
| 816 | def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>; |
| 817 | def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>; |
| 818 | def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>; |
| 819 | def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>; |
| 820 | def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>; |
| 821 | def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>; |
| 822 | def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>; |
| 823 | def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>; |
| 824 | def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>; |
| 825 | def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>; |
| 826 | def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>; |
| 827 | def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>; |
| 828 | def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>; |
| 829 | def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>; |
| 830 | def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>; |
| Artem Tamazov | 2e217b8 | 2016-09-21 16:35:44 +0000 | [diff] [blame] | 831 | def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>; |
| Valery Pykhtin | 902db31 | 2016-08-01 14:21:30 +0000 | [diff] [blame] | 832 | def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>; |
| 833 | def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>; |
| 834 | def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>; |
| 835 | def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>; |
| 836 | def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>; |
| 837 | def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>; |
| 838 | def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>; |
| 839 | def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>; |
| 840 | def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>; |
| 841 | def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>; |
| 842 | |
| 843 | def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>; |
| 844 | def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>; |
| 845 | def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>; |
| 846 | def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>; |
| 847 | def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>; |
| 848 | def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>; |
| 849 | def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>; |
| 850 | def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>; |
| 851 | def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>; |
| 852 | def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>; |
| 853 | def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>; |
| 854 | def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>; |
| 855 | def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>; |
| 856 | def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>; |
| 857 | def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>; |
| 858 | def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>; |
| 859 | def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>; |
| 860 | def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>; |
| 861 | def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>; |
| 862 | def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>; |
| 863 | |
| 864 | def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>; |
| 865 | def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>; |
| 866 | def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>; |
| 867 | def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>; |
| 868 | def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>; |
| 869 | def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>; |
| 870 | def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>; |
| 871 | def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>; |
| 872 | def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>; |
| 873 | def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>; |
| 874 | def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>; |
| 875 | def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>; |
| 876 | def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>; |
| 877 | def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>; |
| 878 | def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>; |
| 879 | def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>; |
| 880 | def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>; |
| 881 | def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>; |
| 882 | def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>; |
| 883 | def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>; |
| 884 | |
| 885 | def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>; |
| 886 | def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>; |
| 887 | def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>; |
| 888 | |
| 889 | def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>; |
| 890 | def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>; |
| 891 | def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>; |
| 892 | def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>; |
| 893 | def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>; |
| 894 | def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>; |
| 895 | def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>; |
| 896 | def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>; |
| 897 | def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>; |
| 898 | def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>; |
| 899 | def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>; |
| 900 | def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>; |
| 901 | def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>; |
| 902 | def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>; |
| 903 | def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>; |
| 904 | def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>; |
| 905 | def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>; |
| 906 | def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>; |
| 907 | def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>; |
| 908 | def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>; |
| 909 | def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>; |
| 910 | def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>; |
| 911 | def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>; |
| 912 | def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>; |
| 913 | def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>; |
| 914 | def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>; |
| 915 | def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>; |
| 916 | def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>; |
| 917 | def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>; |
| 918 | def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>; |
| Matt Arsenault | dedc544 | 2017-02-28 20:15:43 +0000 | [diff] [blame^] | 919 | def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>; |
| 920 | def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>; |
| 921 | def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>; |
| 922 | def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>; |