| Simon Pilgrim | 96855ec | 2018-04-22 14:43:12 +0000 | [diff] [blame] | 1 | # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 2 | # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=SANDY |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 3 | |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 4 | # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=ivybridge -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=IVY |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 5 | |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 6 | # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=HASWELL |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 7 | |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 8 | # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDWELL |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 9 | |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 10 | # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 11 | |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 12 | # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 13 | |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 14 | # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 15 | |
| 16 | vaddps %xmm0, %xmm0, %xmm1 |
| 17 | vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| 18 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 19 | # ALL: Iterations: 1 |
| 20 | # ALL-NEXT: Instructions: 2 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 21 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 22 | # BDWELL-NEXT: Total Cycles: 10 |
| 23 | # BDWELL-NEXT: Dispatch Width: 4 |
| 24 | # BDWELL-NEXT: IPC: 0.20 |
| 25 | # BDWELL-NEXT: Block RThroughput: 2.0 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 26 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 27 | # BTVER2-NEXT: Total Cycles: 11 |
| 28 | # BTVER2-NEXT: Dispatch Width: 2 |
| 29 | # BTVER2-NEXT: IPC: 0.18 |
| 30 | # BTVER2-NEXT: Block RThroughput: 2.0 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 31 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 32 | # HASWELL-NEXT: Total Cycles: 11 |
| 33 | # HASWELL-NEXT: Dispatch Width: 4 |
| 34 | # HASWELL-NEXT: IPC: 0.18 |
| 35 | # HASWELL-NEXT: Block RThroughput: 2.0 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 36 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 37 | # IVY-NEXT: Total Cycles: 11 |
| 38 | # IVY-NEXT: Dispatch Width: 4 |
| 39 | # IVY-NEXT: IPC: 0.18 |
| 40 | # IVY-NEXT: Block RThroughput: 1.0 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 41 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 42 | # SANDY-NEXT: Total Cycles: 11 |
| 43 | # SANDY-NEXT: Dispatch Width: 4 |
| 44 | # SANDY-NEXT: IPC: 0.18 |
| 45 | # SANDY-NEXT: Block RThroughput: 1.0 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 46 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 47 | # SKYLAKE-NEXT: Total Cycles: 11 |
| 48 | # SKYLAKE-NEXT: Dispatch Width: 6 |
| 49 | # SKYLAKE-NEXT: IPC: 0.18 |
| 50 | # SKYLAKE-NEXT: Block RThroughput: 0.7 |
| Andrea Di Biagio | 0104362 | 2018-03-30 13:38:37 +0000 | [diff] [blame] | 51 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 52 | # ZNVER1-NEXT: Total Cycles: 11 |
| 53 | # ZNVER1-NEXT: Dispatch Width: 4 |
| 54 | # ZNVER1-NEXT: IPC: 0.18 |
| 55 | # ZNVER1-NEXT: Block RThroughput: 1.0 |
| 56 | |
| 57 | # BTVER2: Timeline view: |
| 58 | # BTVER2-NEXT: 0 |
| 59 | # BTVER2-NEXT: Index 0123456789 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 60 | |
| 61 | # HASWELL: Timeline view: |
| 62 | # HASWELL-NEXT: 0 |
| 63 | # HASWELL-NEXT: Index 0123456789 |
| 64 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 65 | # IVY: Timeline view: |
| 66 | # IVY-NEXT: 0 |
| 67 | # IVY-NEXT: Index 0123456789 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 68 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 69 | # SANDY: Timeline view: |
| 70 | # SANDY-NEXT: 0 |
| 71 | # SANDY-NEXT: Index 0123456789 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 72 | |
| 73 | # SKYLAKE: Timeline view: |
| 74 | # SKYLAKE-NEXT: 0 |
| 75 | # SKYLAKE-NEXT: Index 0123456789 |
| 76 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 77 | # ZNVER1: Timeline view: |
| 78 | # ZNVER1-NEXT: 0 |
| 79 | # ZNVER1-NEXT: Index 0123456789 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 80 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 81 | # BDWELL: Timeline view: |
| 82 | # BDWELL-NEXT: Index 0123456789 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 83 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 84 | # BTVER2: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 |
| 85 | # BTVER2-NEXT: [0,1] .DeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 86 | |
| 87 | # HASWELL: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 |
| 88 | # HASWELL-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| 89 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 90 | # IVY: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 |
| 91 | # IVY-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 92 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 93 | # SANDY: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 |
| 94 | # SANDY-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 95 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 96 | # ZNVER1: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 |
| 97 | # ZNVER1-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 98 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 99 | # BDWELL: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 |
| 100 | # BDWELL-NEXT: [0,1] DeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 101 | |
| 102 | # SKYLAKE: [0,0] DeeeeER . vaddps %xmm0, %xmm0, %xmm1 |
| 103 | # SKYLAKE-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| 104 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 105 | # ALL: Average Wait times (based on the timeline view): |
| 106 | # ALL-NEXT: [0]: Executions |
| 107 | # ALL-NEXT: [1]: Average time spent waiting in a scheduler's queue |
| 108 | # ALL-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready |
| 109 | # ALL-NEXT: [3]: Average time elapsed from WB until retire stage |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 110 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 111 | # ALL: [0] [1] [2] [3] |
| 112 | # ALL-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 113 | |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 114 | # BDWELL-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| 115 | # BTVER2-NEXT: 1. 1 1.0 1.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 116 | # HASWELL-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 117 | # IVY-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| 118 | # SANDY-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Andrea Di Biagio | cb1ed40 | 2018-05-21 17:11:56 +0000 | [diff] [blame] | 119 | # SKYLAKE-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
| Greg Bedwell | e790f6f | 2018-05-24 16:36:44 +0000 | [diff] [blame] | 120 | # ZNVER1-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |