blob: 66b50f8728e13100646614f3eff83d6c48b5b8a4 [file] [log] [blame]
Alex Bradbury24d9b132016-11-01 23:40:28 +00001set(LLVM_TARGET_DEFINITIONS RISCV.td)
2
3tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
4tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
Alex Bradbury6b2cca72016-11-01 23:47:30 +00005tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
Alex Bradbury89718422017-10-19 21:37:38 +00006tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
Alex Bradbury1a427292017-08-08 14:32:35 +00007tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
Alex Bradbury2fee9ea2017-08-15 13:08:29 +00008tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
Alex Bradbury89718422017-10-19 21:37:38 +00009tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
Alex Bradbury8ab4a962017-09-17 14:36:28 +000010tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
11tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
Alex Bradbury24d9b132016-11-01 23:40:28 +000012
13add_public_tablegen_target(RISCVCommonTableGen)
14
Alex Bradburyb2e54722016-11-01 17:27:54 +000015add_llvm_target(RISCVCodeGen
Alex Bradbury89718422017-10-19 21:37:38 +000016 RISCVAsmPrinter.cpp
17 RISCVFrameLowering.cpp
18 RISCVInstrInfo.cpp
19 RISCVISelDAGToDAG.cpp
20 RISCVISelLowering.cpp
21 RISCVMCInstLower.cpp
22 RISCVRegisterInfo.cpp
23 RISCVSubtarget.cpp
Alex Bradburyb2e54722016-11-01 17:27:54 +000024 RISCVTargetMachine.cpp
25 )
26
Alex Bradbury1a427292017-08-08 14:32:35 +000027add_subdirectory(AsmParser)
Alex Bradbury8ab4a962017-09-17 14:36:28 +000028add_subdirectory(Disassembler)
Alex Bradbury2fee9ea2017-08-15 13:08:29 +000029add_subdirectory(InstPrinter)
Alex Bradbury6b2cca72016-11-01 23:47:30 +000030add_subdirectory(MCTargetDesc)
Alex Bradbury2fee9ea2017-08-15 13:08:29 +000031add_subdirectory(TargetInfo)