Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / e85b06d65f695c576df1e529ee37cb15e6902401 / . / llvm / test / CodeGen / AMDGPU / atomic_load_add.ll
blob: 6b18fe0200d64afc2ac02c3d13b4c088b1289023 [file] [log] [blame]
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
3; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
4; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=R600,FUNC %s
Tom Stellard13c68ef2013-09-05 18:38:09 +0000[diff] [blame]5
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]6; FUNC-LABEL: {{^}}atomic_add_local:
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]7; SICIVI: s_mov_b32 m0
8; GFX9-NOT: m0
Matt Arsenault72574102014-06-11 18:08:34 +0000[diff] [blame]9; R600: LDS_ADD *
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]10; GCN: ds_add_u32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]11define amdgpu_kernel void @atomic_add_local(i32 addrspace(3)* %local) {
Matt Arsenault72574102014-06-11 18:08:34 +0000[diff] [blame]12 %unused = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst
Tom Stellard13c68ef2013-09-05 18:38:09 +0000[diff] [blame]13 ret void
14}
15
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]16; FUNC-LABEL: {{^}}atomic_add_local_const_offset:
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]17; SICIVI: s_mov_b32 m0
18; GFX9-NOT: m0
19
Matt Arsenault72574102014-06-11 18:08:34 +0000[diff] [blame]20; R600: LDS_ADD *
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]21; GCN: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]22define amdgpu_kernel void @atomic_add_local_const_offset(i32 addrspace(3)* %local) {
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]23 %gep = getelementptr i32, i32 addrspace(3)* %local, i32 4
Matt Arsenault72574102014-06-11 18:08:34 +0000[diff] [blame]24 %val = atomicrmw volatile add i32 addrspace(3)* %gep, i32 5 seq_cst
25 ret void
26}
27
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]28; FUNC-LABEL: {{^}}atomic_add_ret_local:
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]29; SICIVI: s_mov_b32 m0
30; GFX9-NOT: m0
31
Matt Arsenault72574102014-06-11 18:08:34 +0000[diff] [blame]32; R600: LDS_ADD_RET *
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]33; GCN: ds_add_rtn_u32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]34define amdgpu_kernel void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
Matt Arsenault72574102014-06-11 18:08:34 +0000[diff] [blame]35 %val = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst
36 store i32 %val, i32 addrspace(1)* %out
37 ret void
38}
39
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]40; FUNC-LABEL: {{^}}atomic_add_ret_local_const_offset:
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]41; SICIVI: s_mov_b32 m0
42; GFX9-NOT: m0
43
Matt Arsenault72574102014-06-11 18:08:34 +0000[diff] [blame]44; R600: LDS_ADD_RET *
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000[diff] [blame]45; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]46define amdgpu_kernel void @atomic_add_ret_local_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]47 %gep = getelementptr i32, i32 addrspace(3)* %local, i32 5
Matt Arsenault72574102014-06-11 18:08:34 +0000[diff] [blame]48 %val = atomicrmw volatile add i32 addrspace(3)* %gep, i32 5 seq_cst
49 store i32 %val, i32 addrspace(1)* %out
Tom Stellard13c68ef2013-09-05 18:38:09 +0000[diff] [blame]50 ret void
51}