blob: 4aa817f7a481469022859d307a75dd3d05046710 [file] [log] [blame]
Oliver Stannard8331aae2016-08-08 15:28:31 +00001; RUN: llc -relocation-model=static -mtriple=armv7a--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM_RO_ABS --check-prefix=ARM_RW_ABS
2; RUN: llc -relocation-model=ropi -mtriple=armv7a--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM_RO_PC --check-prefix=ARM_RW_ABS
3; RUN: llc -relocation-model=rwpi -mtriple=armv7a--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM_RO_ABS --check-prefix=ARM_RW_SB
4; RUN: llc -relocation-model=ropi-rwpi -mtriple=armv7a--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM_RO_PC --check-prefix=ARM_RW_SB
5
6; RUN: llc -relocation-model=static -mtriple=thumbv7m--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB2_RO_ABS --check-prefix=THUMB2_RW_ABS
7; RUN: llc -relocation-model=ropi -mtriple=thumbv7m--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB2_RO_PC --check-prefix=THUMB2_RW_ABS
8; RUN: llc -relocation-model=rwpi -mtriple=thumbv7m--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB2_RO_ABS --check-prefix=THUMB2_RW_SB
9; RUN: llc -relocation-model=ropi-rwpi -mtriple=thumbv7m--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB2_RO_PC --check-prefix=THUMB2_RW_SB
10
11; RUN: llc -relocation-model=static -mtriple=thumbv6m--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB1_RO_ABS --check-prefix=THUMB1_RW_ABS
12; RUN: llc -relocation-model=ropi -mtriple=thumbv6m--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB1_RO_PC --check-prefix=THUMB1_RW_ABS
13; RUN: llc -relocation-model=rwpi -mtriple=thumbv6m--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB1_RO_ABS --check-prefix=THUMB1_RW_SB
14; RUN: llc -relocation-model=ropi-rwpi -mtriple=thumbv6m--none-eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB1_RO_PC --check-prefix=THUMB1_RW_SB
15
Christof Doumad3ed8382017-02-07 13:07:12 +000016; RUN: llc -relocation-model=rwpi -mtriple=armv7a--none-eabi -mattr=no-movt < %s | FileCheck %s --check-prefix=CHECK --check-prefix=NO_MOVT_ARM_RO_ABS --check-prefix=NO_MOVT_ARM_RW_SB
17; RUN: llc -relocation-model=ropi-rwpi -mtriple=armv7a--none-eabi -mattr=no-movt < %s | FileCheck %s --check-prefix=CHECK --check-prefix=NO_MOVT_ARM_RO_PC --check-prefix=NO_MOVT_ARM_RW_SB
18
19; RUN: llc -relocation-model=rwpi -mtriple=thumbv7m--none-eabi -mattr=no-movt < %s | FileCheck %s --check-prefix=CHECK --check-prefix=NO_MOVT_THUMB2_RO_ABS --check-prefix=NO_MOVT_THUMB2_RW_SB
20; RUN: llc -relocation-model=ropi-rwpi -mtriple=thumbv7m--none-eabi -mattr=no-movt < %s | FileCheck %s --check-prefix=CHECK --check-prefix=NO_MOVT_THUMB2_RO_PC --check-prefix=NO_MOVT_THUMB2_RW_SB
21
Oliver Stannard8331aae2016-08-08 15:28:31 +000022target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
23
24@a = external global i32, align 4
25@b = external constant i32, align 4
26
27define i32 @read() {
28entry:
29 %0 = load i32, i32* @a, align 4
30 ret i32 %0
31; CHECK-LABEL: read:
32
33; ARM_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
34; ARM_RW_ABS: movt r[[REG]], :upper16:a
35; ARM_RW_ABS: ldr r0, [r[[REG]]]
36
Christof Doumad3ed8382017-02-07 13:07:12 +000037; ARM_RW_SB: movw r[[REG:[0-9]]], :lower16:a(sbrel)
38; ARM_RW_SB: movt r[[REG]], :upper16:a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +000039; ARM_RW_SB: ldr r0, [r9, r[[REG]]]
40
Christof Doumad3ed8382017-02-07 13:07:12 +000041; NO_MOVT_ARM_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
42; NO_MOVT_ARM_RW_SB: ldr r0, [r9, r[[REG]]]
43
Oliver Stannard8331aae2016-08-08 15:28:31 +000044; THUMB2_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
45; THUMB2_RW_ABS: movt r[[REG]], :upper16:a
46; THUMB2_RW_ABS: ldr r0, [r[[REG]]]
47
Christof Doumad3ed8382017-02-07 13:07:12 +000048; THUMB2_RW_SB: movw r[[REG:[0-9]]], :lower16:a(sbrel)
49; THUMB2_RW_SB: movt r[[REG]], :upper16:a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +000050; THUMB2_RW_SB: ldr.w r0, [r9, r[[REG]]]
51
Christof Doumad3ed8382017-02-07 13:07:12 +000052; NO_MOVT_THUMB2_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
53; NO_MOVT_THUMB2_RW_SB: ldr.w r0, [r9, r[[REG]]]
54
Oliver Stannard8331aae2016-08-08 15:28:31 +000055; THUMB1_RW_ABS: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
56; THUMB1_RW_ABS: ldr r0, [r[[REG]]]
57
58; THUMB1_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
59; THUMB1_RW_SB: mov r[[REG_SB:[0-9]+]], r9
60; THUMB1_RW_SB: ldr r0, [r[[REG_SB]], r[[REG]]]
61
62; CHECK: {{(bx lr|pop)}}
63
Christof Doumad3ed8382017-02-07 13:07:12 +000064; NO_MOVT_ARM_RW_SB: [[LCPI]]
65; NO_MOVT_ARM_RW_SB: .long a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +000066
Christof Doumad3ed8382017-02-07 13:07:12 +000067; NO_MOVT_THUMB2_RW_SB: [[LCPI]]
68; NO_MOVT_THUMB2_RW_SB: .long a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +000069
70; THUMB1_RW_ABS: [[LCPI]]
71; THUMB1_RW_ABS-NEXT: .long a
72
73; THUMB1_RW_SB: [[LCPI]]
74; THUMB1_RW_SB: .long a(sbrel)
75}
76
77define void @write(i32 %v) {
78entry:
79 store i32 %v, i32* @a, align 4
80 ret void
81; CHECK-LABEL: write:
82
83; ARM_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
84; ARM_RW_ABS: movt r[[REG]], :upper16:a
85; ARM_RW_ABS: str r0, [r[[REG:[0-9]]]]
86
Christof Doumad3ed8382017-02-07 13:07:12 +000087; ARM_RW_SB: movw r[[REG:[0-9]]], :lower16:a
88; ARM_RW_SB: movt r[[REG]], :upper16:a
89; ARM_RW_SB: str r0, [r9, r[[REG:[0-9]]]]
90
91; NO_MOVT_ARM_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
92; NO_MOVT_ARM_RW_SB: str r0, [r9, r[[REG]]]
Oliver Stannard8331aae2016-08-08 15:28:31 +000093
94; THUMB2_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
95; THUMB2_RW_ABS: movt r[[REG]], :upper16:a
96; THUMB2_RW_ABS: str r0, [r[[REG]]]
97
Christof Doumad3ed8382017-02-07 13:07:12 +000098; THUMB2_RW_SB: movw r[[REG:[0-9]]], :lower16:a(sbrel)
99; THUMB2_RW_SB: movt r[[REG]], :upper16:a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +0000100; THUMB2_RW_SB: str.w r0, [r9, r[[REG]]]
101
Christof Doumad3ed8382017-02-07 13:07:12 +0000102; NO_MOVT_THUMB2_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
103; NO_MOVT_THUMB2_RW_SB: str.w r0, [r9, r[[REG]]]
104
Oliver Stannard8331aae2016-08-08 15:28:31 +0000105; THUMB1_RW_ABS: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
106; THUMB1_RW_ABS: str r0, [r[[REG]]]
107
108; THUMB1_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
109; THUMB1_RW_SB: mov r[[REG_SB:[0-9]+]], r9
110; THUMB1_RW_SB: str r0, [r[[REG_SB]], r[[REG]]]
111
112; CHECK: {{(bx lr|pop)}}
113
Christof Doumad3ed8382017-02-07 13:07:12 +0000114; NO_MOVT_ARM_RW_SB: [[LCPI]]
115; NO_MOVT_ARM_RW_SB: .long a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +0000116
Christof Doumad3ed8382017-02-07 13:07:12 +0000117; NO_MOVT_THUMB2_RW_SB: [[LCPI]]
118; NO_MOVT_THUMB2_RW_SB: .long a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +0000119
120; THUMB1_RW_ABS: [[LCPI]]
121; THUMB1_RW_ABS-NEXT: .long a
122
123; THUMB1_RW_SB: [[LCPI]]
124; THUMB1_RW_SB: .long a(sbrel)
125}
126
127define i32 @read_const() {
128entry:
129 %0 = load i32, i32* @b, align 4
130 ret i32 %0
131; CHECK-LABEL: read_const:
132
133; ARM_RO_ABS: movw r[[reg:[0-9]]], :lower16:b
134; ARM_RO_ABS: movt r[[reg]], :upper16:b
135; ARM_RO_ABS: ldr r0, [r[[reg]]]
136
Christof Doumad3ed8382017-02-07 13:07:12 +0000137; NO_MOVT_ARM_RO_ABS: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
138; NO_MOVT_ARM_RO_ABS: ldr r0, [r[[REG]]]
139
Oliver Stannard8331aae2016-08-08 15:28:31 +0000140; ARM_RO_PC: movw r[[REG:[0-9]]], :lower16:(b-([[LPC:.LPC[0-9]+_[0-9]+]]+8))
141; ARM_RO_PC: movt r[[REG]], :upper16:(b-([[LPC]]+8))
142; ARM_RO_PC: [[LPC]]:
143; ARM_RO_PC-NEXT: ldr r0, [pc, r[[REG]]]
144
Christof Doumad3ed8382017-02-07 13:07:12 +0000145; NO_MOVT_ARM_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
146; NO_MOVT_ARM_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
147; NO_MOVT_ARM_RO_PC: ldr r0, [pc, r[[REG]]]
148
Oliver Stannard8331aae2016-08-08 15:28:31 +0000149; THUMB2_RO_ABS: movw r[[REG:[0-9]]], :lower16:b
150; THUMB2_RO_ABS: movt r[[REG]], :upper16:b
151; THUMB2_RO_ABS: ldr r0, [r[[REG]]]
152
Christof Doumad3ed8382017-02-07 13:07:12 +0000153; NO_MOVT_THUMB2_RO_ABS: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
154; NO_MOVT_THUMB2_RO_ABS: ldr r0, [r[[REG]]]
155
Oliver Stannard8331aae2016-08-08 15:28:31 +0000156; THUMB2_RO_PC: movw r[[REG:[0-9]]], :lower16:(b-([[LPC:.LPC[0-9]+_[0-9]+]]+4))
157; THUMB2_RO_PC: movt r[[REG]], :upper16:(b-([[LPC]]+4))
158; THUMB2_RO_PC: [[LPC]]:
159; THUMB2_RO_PC-NEXT: add r[[REG]], pc
160; THUMB2_RO_PC: ldr r0, [r[[REG]]]
161
Christof Doumad3ed8382017-02-07 13:07:12 +0000162; NO_MOVT_THUMB2_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
163; NO_MOVT_THUMB2_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
164; NO_MOVT_THUMB2_RO_PC-NEXT: add r[[REG]], pc
165; NO_MOVT_THUMB2_RO_PC: ldr r0, [r[[REG]]]
166
167
Oliver Stannard8331aae2016-08-08 15:28:31 +0000168; THUMB1_RO_ABS: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
169; THUMB1_RO_ABS: ldr r0, [r[[REG]]]
170
171; THUMB1_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
172; THUMB1_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
173; THUMB1_RO_PC-NEXT: add r[[REG]], pc
174; THUMB1_RO_PC: ldr r0, [r[[REG]]]
175
176; CHECK: {{(bx lr|pop)}}
177
Christof Doumad3ed8382017-02-07 13:07:12 +0000178; NO_MOVT_ARM_RO_ABS: [[LCPI]]
179; NO_MOVT_ARM_RO_ABS-NEXT: .long b
180
181; NO_MOVT_THUMB2_RO_ABS: [[LCPI]]
182; NO_MOVT_THUMB2_RO_ABS-NEXT: .long b
183
Oliver Stannard8331aae2016-08-08 15:28:31 +0000184; THUMB1_RO_ABS: [[LCPI]]
185; THUMB1_RO_ABS-NEXT: .long b
186
Christof Doumad3ed8382017-02-07 13:07:12 +0000187; NO_MOVT_ARM_RO_PC: [[LCPI]]
188; NO_MOVT_ARM_RO_PC-NEXT: .long b-([[LPC]]+8)
189
190; NO_MOVT_THUMB2_RO_PC: [[LCPI]]
191; NO_MOVT_THUMB2_RO_PC-NEXT: .long b-([[LPC]]+4)
192
Oliver Stannard8331aae2016-08-08 15:28:31 +0000193; THUMB1_RO_PC: [[LCPI]]
194; THUMB1_RO_PC-NEXT: .long b-([[LPC]]+4)
195}
196
197define i32* @take_addr() {
198entry:
199 ret i32* @a
200; CHECK-LABEL: take_addr:
201
202; ARM_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
203; ARM_RW_ABS: movt r[[REG]], :upper16:a
204
Christof Doumad3ed8382017-02-07 13:07:12 +0000205; ARM_RW_SB: movw r[[REG:[0-9]]], :lower16:a(sbrel)
206; ARM_RW_SB: movt r[[REG]], :upper16:a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +0000207; ARM_RW_SB: add r0, r9, r[[REG]]
208
Christof Doumad3ed8382017-02-07 13:07:12 +0000209; NO_MOVT_ARM_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
210; NO_MOVT_ARM_RW_SB: add r0, r9, r[[REG]]
211
Oliver Stannard8331aae2016-08-08 15:28:31 +0000212; THUMB2_RW_ABS: movw r[[REG:[0-9]]], :lower16:a
213; THUMB2_RW_ABS: movt r[[REG]], :upper16:a
214
Christof Doumad3ed8382017-02-07 13:07:12 +0000215; THUMB2_RW_SB: movw r[[REG:[0-9]]], :lower16:a(sbrel)
216; THUMB2_RW_SB: movt r[[REG]], :upper16:a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +0000217; THUMB2_RW_SB: add r0, r9
218
Christof Doumad3ed8382017-02-07 13:07:12 +0000219; NO_MOVT_THUMB2_RW_SB: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
220; NO_MOVT_THUMB2_RW_SB: add r0, r9
221
Oliver Stannard8331aae2016-08-08 15:28:31 +0000222; THUMB1_RW_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
223
224; THUMB1_RW_SB: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
225; THUMB1_RW_SB: mov r[[REG_SB:[0-9]+]], r9
226; THUMB1_RW_SB: adds r[[REG]], r[[REG_SB]], r[[REG]]
227
228; CHECK: {{(bx lr|pop)}}
229
Christof Doumad3ed8382017-02-07 13:07:12 +0000230; NO_MOVT_ARM_RW_SB: [[LCPI]]
231; NO_MOVT_ARM_RW_SB: .long a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +0000232
Christof Doumad3ed8382017-02-07 13:07:12 +0000233; NO_MOVT_THUMB2_RW_SB: [[LCPI]]
234; NO_MOVT_THUMB2_RW_SB: .long a(sbrel)
Oliver Stannard8331aae2016-08-08 15:28:31 +0000235
236; THUMB1_RW_ABS: [[LCPI]]
237; THUMB1_RW_ABS-NEXT: .long a
238
239; THUMB1_RW_SB: [[LCPI]]
240; THUMB1_RW_SB: .long a(sbrel)
241}
242
243define i32* @take_addr_const() {
244entry:
245 ret i32* @b
246; CHECK-LABEL: take_addr_const:
247
248; ARM_RO_ABS: movw r[[REG:[0-9]]], :lower16:b
249; ARM_RO_ABS: movt r[[REG]], :upper16:b
250
Christof Doumad3ed8382017-02-07 13:07:12 +0000251; NO_MOVT_ARM_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
252
Oliver Stannard8331aae2016-08-08 15:28:31 +0000253; ARM_RO_PC: movw r[[REG:[0-9]]], :lower16:(b-([[LPC:.LPC[0-9]+_[0-9]+]]+8))
254; ARM_RO_PC: movt r[[REG]], :upper16:(b-([[LPC]]+8))
255; ARM_RO_PC: [[LPC]]:
256; ARM_RO_PC-NEXT: add r0, pc, r[[REG:[0-9]]]
257
Christof Doumad3ed8382017-02-07 13:07:12 +0000258; NO_MOVT_ARM_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
259; NO_MOVT_ARM_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
260; NO_MOVT_ARM_RO_PC-NEXT: add r0, pc, r[[REG]]
261
Oliver Stannard8331aae2016-08-08 15:28:31 +0000262; THUMB2_RO_ABS: movw r[[REG:[0-9]]], :lower16:b
263; THUMB2_RO_ABS: movt r[[REG]], :upper16:b
264
Christof Doumad3ed8382017-02-07 13:07:12 +0000265; NO_MOVT_THUMB2_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
266
Oliver Stannard8331aae2016-08-08 15:28:31 +0000267; THUMB2_RO_PC: movw r0, :lower16:(b-([[LPC:.LPC[0-9]+_[0-9]+]]+4))
268; THUMB2_RO_PC: movt r0, :upper16:(b-([[LPC]]+4))
269; THUMB2_RO_PC: [[LPC]]:
270; THUMB2_RO_PC-NEXT: add r0, pc
271
Christof Doumad3ed8382017-02-07 13:07:12 +0000272; NO_MOVT_THUMB2_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
273; NO_MOVT_THUMB2_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
274; NO_MOVT_THUMB2_RO_PC-NEXT: add r[[REG]], pc
275
Oliver Stannard8331aae2016-08-08 15:28:31 +0000276; THUMB1_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
277
278; THUMB1_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
279; THUMB1_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
280; THUMB1_RO_PC-NEXT: add r[[REG]], pc
281
282; CHECK: {{(bx lr|pop)}}
283
Christof Doumad3ed8382017-02-07 13:07:12 +0000284; NO_MOVT_ARM_RO_ABS: [[LCPI]]
285; NO_MOVT_ARM_RO_ABS-NEXT: .long b
286
287; NO_MOVT_THUMB2_RO_ABS: [[LCPI]]
288; NO_MOVT_THUMB2_RO_ABS-NEXT: .long b
289
Oliver Stannard8331aae2016-08-08 15:28:31 +0000290; THUMB1_RO_ABS: [[LCPI]]
291; THUMB1_RO_ABS-NEXT: .long b
292
Christof Doumad3ed8382017-02-07 13:07:12 +0000293; NO_MOVT_ARM_RO_PC: [[LCPI]]
294; NO_MOVT_ARM_RO_PC-NEXT: .long b-([[LPC]]+8)
295
296; NO_MOVT_THUMB2_RO_PC: [[LCPI]]
297; NO_MOVT_THUMB2_RO_PC-NEXT: .long b-([[LPC]]+4)
298
Oliver Stannard8331aae2016-08-08 15:28:31 +0000299; THUMB1_RO_PC: [[LCPI]]
300; THUMB1_RO_PC-NEXT: .long b-([[LPC]]+4)
301}
302
303define i8* @take_addr_func() {
304entry:
305 ret i8* bitcast (i8* ()* @take_addr_func to i8*)
306; CHECK-LABEL: take_addr_func:
307
308; ARM_RO_ABS: movw r[[REG:[0-9]]], :lower16:take_addr_func
309; ARM_RO_ABS: movt r[[REG]], :upper16:take_addr_func
310
Christof Doumad3ed8382017-02-07 13:07:12 +0000311; NO_MOVT_ARM_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
312
Oliver Stannard8331aae2016-08-08 15:28:31 +0000313; ARM_RO_PC: movw r[[REG:[0-9]]], :lower16:(take_addr_func-([[LPC:.LPC[0-9]+_[0-9]+]]+8))
314; ARM_RO_PC: movt r[[REG]], :upper16:(take_addr_func-([[LPC]]+8))
315; ARM_RO_PC: [[LPC]]:
316; ARM_RO_PC-NEXT: add r0, pc, r[[REG:[0-9]]]
317
Christof Doumad3ed8382017-02-07 13:07:12 +0000318; NO_MOVT_ARM_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
319; NO_MOVT_ARM_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
320; NO_MOVT_ARM_RO_PC-NEXT: add r0, pc, r[[REG]]
321
Oliver Stannard8331aae2016-08-08 15:28:31 +0000322; THUMB2_RO_ABS: movw r[[REG:[0-9]]], :lower16:take_addr_func
323; THUMB2_RO_ABS: movt r[[REG]], :upper16:take_addr_func
324
Christof Doumad3ed8382017-02-07 13:07:12 +0000325; NO_MOVT_THUMB2_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
326
Oliver Stannard8331aae2016-08-08 15:28:31 +0000327; THUMB2_RO_PC: movw r0, :lower16:(take_addr_func-([[LPC:.LPC[0-9]+_[0-9]+]]+4))
328; THUMB2_RO_PC: movt r0, :upper16:(take_addr_func-([[LPC]]+4))
329; THUMB2_RO_PC: [[LPC]]:
330; THUMB2_RO_PC-NEXT: add r0, pc
331
Christof Doumad3ed8382017-02-07 13:07:12 +0000332; NO_MOVT_THUMB2_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
333; NO_MOVT_THUMB2_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
334; NO_MOVT_THUMB2_RO_PC-NEXT: add r[[REG]], pc
335
Oliver Stannard8331aae2016-08-08 15:28:31 +0000336; THUMB1_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
337
338; THUMB1_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
339; THUMB1_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
340; THUMB1_RO_PC-NEXT: add r[[REG]], pc
341
342; CHECK: {{(bx lr|pop)}}
343
Christof Doumad3ed8382017-02-07 13:07:12 +0000344; NO_MOVT_ARM_RO_ABS: [[LCPI]]
345; NO_MOVT_ARM_RO_ABS-NEXT: .long take_addr_func
346
347; NO_MOVT_THUMB2_RO_ABS: [[LCPI]]
348; NO_MOVT_THUMB2_RO_ABS-NEXT: .long take_addr_func
349
Oliver Stannard8331aae2016-08-08 15:28:31 +0000350; THUMB1_RO_ABS: [[LCPI]]
351; THUMB1_RO_ABS-NEXT: .long take_addr_func
352
Christof Doumad3ed8382017-02-07 13:07:12 +0000353; NO_MOVT_ARM_RO_PC: [[LCPI]]
354; NO_MOVT_ARM_RO_PC-NEXT: .long take_addr_func-([[LPC]]+8)
355
356; NO_MOVT_THUMB2_RO_PC: [[LCPI]]
357; NO_MOVT_THUMB2_RO_PC-NEXT: .long take_addr_func-([[LPC]]+4)
358
Oliver Stannard8331aae2016-08-08 15:28:31 +0000359; THUMB1_RO_PC: [[LCPI]]
360; THUMB1_RO_PC-NEXT: .long take_addr_func-([[LPC]]+4)
361}
362
363define i8* @block_addr() {
364entry:
365 br label %lab1
366
367lab1:
368 ret i8* blockaddress(@block_addr, %lab1)
369
370; CHECK-LABEL: block_addr:
371
372; ARM_RO_ABS: [[LTMP:.Ltmp[0-9]+]]:
373; ARM_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
374
375; ARM_RO_PC: [[LTMP:.Ltmp[0-9]+]]:
376; ARM_RO_PC: ldr r[[REG:[0-9]]], [[LCPI:.LCPI[0-9]+_[0-9]+]]
377; ARM_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
378; ARM_RO_PC: add r0, pc, r[[REG]]
379
380; THUMB2_RO_ABS: [[LTMP:.Ltmp[0-9]+]]:
381; THUMB2_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
382
383; THUMB2_RO_PC: [[LTMP:.Ltmp[0-9]+]]:
384; THUMB2_RO_PC: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
385; THUMB2_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
386; THUMB2_RO_PC: add r0, pc
387
388; THUMB1_RO_ABS: [[LTMP:.Ltmp[0-9]+]]:
389; THUMB1_RO_ABS: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
390
391; THUMB1_RO_PC: [[LTMP:.Ltmp[0-9]+]]:
392; THUMB1_RO_PC: ldr r0, [[LCPI:.LCPI[0-9]+_[0-9]+]]
393; THUMB1_RO_PC: [[LPC:.LPC[0-9]+_[0-9]+]]:
394; THUMB1_RO_PC: add r0, pc
395
396; CHECK: bx lr
397
398; ARM_RO_ABS: [[LCPI]]
399; ARM_RO_ABS-NEXT: .long [[LTMP]]
400
401; ARM_RO_PC: [[LCPI]]
402; ARM_RO_PC-NEXT: .long [[LTMP]]-([[LPC]]+8)
403
404; THUMB2_RO_ABS: [[LCPI]]
405; THUMB2_RO_ABS-NEXT: .long [[LTMP]]
406
407; THUMB2_RO_PC: [[LCPI]]
408; THUMB2_RO_PC-NEXT: .long [[LTMP]]-([[LPC]]+4)
409
410; THUMB1_RO_ABS: [[LCPI]]
411; THUMB1_RO_ABS-NEXT: .long [[LTMP]]
412
413; THUMB1_RO_PC: [[LCPI]]
414; THUMB1_RO_PC-NEXT: .long [[LTMP]]-([[LPC]]+4)
415}