| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Test that the DAG combiner doesn't assert because it attempts to replace |
| 5 | ; the chain of a post-increment store based upon alias information. The code |
| 6 | ; in DAGCombiner is unable to convert indexed stores. |
| 7 | |
| 8 | ; Function Attrs: nounwind |
| 9 | define void @f0(i32 %a0, i8* %a1, i8* %a2) #0 { |
| 10 | b0: |
| 11 | switch i32 %a0, label %b5 [ |
| 12 | i32 67830273, label %b1 |
| 13 | i32 67502595, label %b3 |
| 14 | ] |
| 15 | |
| 16 | b1: ; preds = %b0 |
| 17 | br i1 undef, label %b2, label %b5 |
| 18 | |
| 19 | b2: ; preds = %b1 |
| 20 | br label %b5 |
| 21 | |
| 22 | b3: ; preds = %b0 |
| 23 | br i1 undef, label %b4, label %b5 |
| 24 | |
| 25 | b4: ; preds = %b3 |
| 26 | %v0 = bitcast i8* %a2 to i32* |
| 27 | store i32 0, i32* %v0, align 1, !tbaa !0 |
| 28 | %v1 = getelementptr inbounds i8, i8* %a1, i32 4 |
| 29 | %v2 = bitcast i8* %v1 to i32* |
| 30 | %v3 = load i32, i32* %v2, align 4, !tbaa !5 |
| 31 | %v4 = getelementptr inbounds i8, i8* %a2, i32 4 |
| 32 | %v5 = bitcast i8* %v4 to i32* |
| 33 | store i32 %v3, i32* %v5, align 1, !tbaa !5 |
| 34 | br label %b5 |
| 35 | |
| 36 | b5: ; preds = %b4, %b3, %b2, %b1, %b0 |
| 37 | ret void |
| 38 | } |
| 39 | |
| 40 | attributes #0 = { nounwind "target-cpu"="hexagonv55" } |
| 41 | |
| 42 | !0 = !{!1, !2, i64 0} |
| 43 | !1 = !{!"", !2, i64 0, !2, i64 4} |
| 44 | !2 = !{!"long", !3, i64 0} |
| 45 | !3 = !{!"omnipotent char", !4, i64 0} |
| 46 | !4 = !{!"Simple C/C++ TBAA"} |
| 47 | !5 = !{!1, !2, i64 4} |