| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -O2 -march=hexagon < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Test that the final instruction ordering code does not result in infinite |
| 5 | ; recursion (a segmentation fault). The problem is that the order heuristics |
| 6 | ; did not properly take into account the stage in which an instruction is |
| 7 | ; scheduled. |
| 8 | |
| 9 | %0 = type { %1, %4, %9, %28 } |
| 10 | %1 = type { i8, [32 x %2] } |
| 11 | %2 = type { i8, %3, i8, i8, i16, i8, [20 x i16], [20 x i16] } |
| 12 | %3 = type { i16, i8 } |
| 13 | %4 = type { i8, [64 x %5], [64 x %5*] } |
| 14 | %5 = type { i8, i8, i8*, %6 } |
| 15 | %6 = type { %7 } |
| 16 | %7 = type { i8*, %3, i8, i8, i8, i8, i16, i8, i8, i8, i16, i32, i8, [3 x i8], [3 x i16], i16, i8, i16, i8, %8, i16, i8, i16 } |
| 17 | %8 = type { i8, i8 } |
| 18 | %9 = type { i8, i8, %10*, i8, [8 x %7*], i8, i8, i8, i8, i8, %7*, i8, %7*, i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, i32, i32, i32, i32, i32, i32, i32, i8, i8, i16, i8, void (i8)*, i8, i8, i8, i8, i8, i8 } |
| 19 | %10 = type { i8, i8, i8, i8, i8, %11, %12, %13, %14 } |
| 20 | %11 = type { i8, i16, i16 } |
| 21 | %12 = type { i8, i16, i8* } |
| 22 | %13 = type { i8, i16 } |
| 23 | %14 = type { %15, %20, %25 } |
| 24 | %15 = type { i8, i8, %16, i8, [18 x %17] } |
| 25 | %16 = type { i8, i16, i16 } |
| 26 | %17 = type { i8, i8, [10 x %3], [10 x i16], [10 x i16], [10 x i8], %18* } |
| 27 | %18 = type { %19, i16, i16, %19, i16 } |
| 28 | %19 = type { i16, i16, i16, i8 } |
| 29 | %20 = type { i8, i8, %21 } |
| 30 | %21 = type { i8*, %22, %23 } |
| 31 | %22 = type { %3, i8, i8, i16, i16, i16, i8, i16 } |
| 32 | %23 = type { [2 x %24], [4 x i8] } |
| 33 | %24 = type { i8, %3, i16, i16, i16, i16, %18* } |
| 34 | %25 = type { i8, i8, [8 x %26] } |
| 35 | %26 = type { i8*, %27, %24 } |
| 36 | %27 = type { %3, i8, i16, i16, i16 } |
| 37 | %28 = type { [2 x %29], [2 x i16], i8, i8*, i16, i8, i8, %31*, %32*, %33*, %33*, [3 x %34*], i8, [2 x i8], i8, i8, [2 x i8], [2 x i8], [3 x i8] } |
| 38 | %29 = type <{ %30, i8, [1000 x i8] }> |
| 39 | %30 = type { i16, i16, [2 x i32] } |
| 40 | %31 = type <{ i8, i8, i16, i8 }> |
| 41 | %32 = type <{ i16, i16, i8, i16 }> |
| 42 | %33 = type <{ i8, i8, i16, i16, i16, i8, i16, i16 }> |
| 43 | %34 = type <{ i8, i8, i16, i16, i8, i16, i8, i8, i32, i16, i16, i16 }> |
| 44 | |
| 45 | @g0 = external global [2 x %0], align 8 |
| 46 | |
| 47 | ; Function Attrs: nounwind ssp |
| 48 | define void @f0() #0 { |
| 49 | b0: |
| 50 | br label %b1 |
| 51 | |
| 52 | b1: ; preds = %b1, %b0 |
| 53 | %v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ] |
| 54 | %v1 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 undef, i32 1, i32 1, i32 %v0 |
| 55 | %v2 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 undef, i32 1, i32 2, i32 %v0 |
| 56 | store %5* %v1, %5** %v2, align 4 |
| 57 | %v3 = getelementptr inbounds [2 x %0], [2 x %0]* @g0, i32 0, i32 undef, i32 1, i32 1, i32 %v0, i32 3 |
| 58 | %v4 = bitcast %6* %v3 to %5** |
| 59 | store %5* %v1, %5** %v4, align 4 |
| 60 | %v5 = add nuw nsw i32 %v0, 1 |
| 61 | %v6 = icmp eq i32 %v5, 64 |
| 62 | br i1 %v6, label %b2, label %b1 |
| 63 | |
| 64 | b2: ; preds = %b1 |
| 65 | ret void |
| 66 | } |
| 67 | |
| 68 | attributes #0 = { nounwind ssp "target-cpu"="hexagonv55" } |