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gerrit-public.fairphone.software / toolchain / llvm-project / e85b06d65f695c576df1e529ee37cb15e6902401 / . / llvm / test / CodeGen / Mips / selgek.ll
blob: 9d9df743db9b97f9d903362d1240e9bee9b1fbbb [file] [log] [blame]
Daniel Sanders8008de52015-10-15 14:34:23 +0000[diff] [blame]1; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]2
3@t = global i32 10, align 4
4@f = global i32 199, align 4
5@a = global i32 2, align 4
6@b = global i32 1000, align 4
7@c = global i32 2, align 4
8@z1 = common global i32 0, align 4
9@z2 = common global i32 0, align 4
10@z3 = common global i32 0, align 4
11@z4 = common global i32 0, align 4
12@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
13
14define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
15entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]16 %0 = load i32, i32* @a, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]17 %cmp = icmp sge i32 %0, 1000
18 br i1 %cmp, label %cond.true, label %cond.false
19
20cond.true: ; preds = %entry
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]21 %1 = load i32, i32* @f, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]22 br label %cond.end
23
24cond.false: ; preds = %entry
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]25 %2 = load i32, i32* @t, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]26 br label %cond.end
27
28cond.end: ; preds = %cond.false, %cond.true
29 %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
30 store i32 %cond, i32* @z1, align 4
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]31 %3 = load i32, i32* @b, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]32 %cmp1 = icmp sge i32 %3, 1
33 br i1 %cmp1, label %cond.true2, label %cond.false3
34
35cond.true2: ; preds = %cond.end
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]36 %4 = load i32, i32* @t, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]37 br label %cond.end4
38
39cond.false3: ; preds = %cond.end
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]40 %5 = load i32, i32* @f, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]41 br label %cond.end4
42
43cond.end4: ; preds = %cond.false3, %cond.true2
44 %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
45 store i32 %cond5, i32* @z2, align 4
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]46 %6 = load i32, i32* @c, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]47 %cmp6 = icmp sge i32 %6, 2
48 br i1 %cmp6, label %cond.true7, label %cond.false8
49
50cond.true7: ; preds = %cond.end4
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]51 %7 = load i32, i32* @t, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]52 br label %cond.end9
53
54cond.false8: ; preds = %cond.end4
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]55 %8 = load i32, i32* @f, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]56 br label %cond.end9
57
58cond.end9: ; preds = %cond.false8, %cond.true7
59 %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
60 store i32 %cond10, i32* @z3, align 4
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]61 %9 = load i32, i32* @a, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]62 %cmp11 = icmp sge i32 %9, 2
63 br i1 %cmp11, label %cond.true12, label %cond.false13
64
65cond.true12: ; preds = %cond.end9
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]66 %10 = load i32, i32* @t, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]67 br label %cond.end14
68
69cond.false13: ; preds = %cond.end9
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]70 %11 = load i32, i32* @f, align 4
Reed Kotler3e457f52013-02-19 03:56:57 +0000[diff] [blame]71 br label %cond.end14
72
73cond.end14: ; preds = %cond.false13, %cond.true12
74 %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ]
75 store i32 %cond15, i32* @z4, align 4
76 ret void
77}
78
79attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" }
80attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" }
81
82; 16: slti ${{[0-9]+}}, 1000
83; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
84
85; 16: slti ${{[0-9]+}}, 1 # 16 bit inst
86; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
87
88; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
89; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
90
91; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
92; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
Reed Kotler4416cda2013-02-22 05:10:51 +0000[diff] [blame]93
94