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gerrit-public.fairphone.software / toolchain / llvm-project / e85b06d65f695c576df1e529ee37cb15e6902401 / . / llvm / test / CodeGen / PowerPC / andc.ll
blob: 9bfbda2bbd715ace0c7dca47280c4de5c179e3ba [file] [log] [blame]
Sanjay Patelc9d36f12017-04-19 14:58:09 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
Sanjay Patel748b0652016-04-13 23:23:30 +0000[diff] [blame]3
Sanjay Patel748b0652016-04-13 23:23:30 +0000[diff] [blame]4define i1 @and_cmp1(i32 %x, i32 %y) {
5; CHECK-LABEL: and_cmp1:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]6; CHECK: # %bb.0:
Sanjay Patelc9d36f12017-04-19 14:58:09 +0000[diff] [blame]7; CHECK-NEXT: andc 3, 4, 3
8; CHECK-NEXT: cntlzw 3, 3
9; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
10; CHECK-NEXT: blr
Sanjay Patel748b0652016-04-13 23:23:30 +0000[diff] [blame]11 %and = and i32 %x, %y
12 %cmp = icmp eq i32 %and, %y
13 ret i1 %cmp
14}
15
16define i1 @and_cmp_const(i32 %x) {
17; CHECK-LABEL: and_cmp_const:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]18; CHECK: # %bb.0:
Sanjay Patelc9d36f12017-04-19 14:58:09 +0000[diff] [blame]19; CHECK-NEXT: li 4, 43
20; CHECK-NEXT: andc 3, 4, 3
21; CHECK-NEXT: cntlzw 3, 3
22; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
23; CHECK-NEXT: blr
Sanjay Patel748b0652016-04-13 23:23:30 +0000[diff] [blame]24 %and = and i32 %x, 43
25 %cmp = icmp eq i32 %and, 43
26 ret i1 %cmp
27}
28
Hal Finkel5ef4b032016-09-02 02:58:25 +0000[diff] [blame]29define i1 @foo(i32 %i) {
30; CHECK-LABEL: foo:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]31; CHECK: # %bb.0:
Sanjay Patelc9d36f12017-04-19 14:58:09 +0000[diff] [blame]32; CHECK-NEXT: lis 4, 4660
33; CHECK-NEXT: ori 4, 4, 22136
34; CHECK-NEXT: andc 3, 4, 3
35; CHECK-NEXT: cntlzw 3, 3
36; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
37; CHECK-NEXT: blr
Hal Finkel5ef4b032016-09-02 02:58:25 +0000[diff] [blame]38 %and = and i32 %i, 305419896
39 %cmp = icmp eq i32 %and, 305419896
40 ret i1 %cmp
41}
42
Sanjay Patelc9d36f12017-04-19 14:58:09 +0000[diff] [blame]43define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) {
44; CHECK-LABEL: hidden_not_v4i32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]45; CHECK: # %bb.0:
Sanjay Patelae382bb2017-04-19 21:23:09 +0000[diff] [blame]46; CHECK-NEXT: vspltisw 3, 6
47; CHECK-NEXT: xxlandc 34, 35, 34
Sanjay Patelc9d36f12017-04-19 14:58:09 +0000[diff] [blame]48; CHECK-NEXT: blr
49 %xor = xor <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>
50 %and = and <4 x i32> %xor, <i32 6, i32 6, i32 6, i32 6>
51 ret <4 x i32> %and
52}
53