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gerrit-public.fairphone.software / toolchain / llvm-project / e85b06d65f695c576df1e529ee37cb15e6902401 / . / llvm / test / CodeGen / SystemZ / cond-store-08.ll
blob: 4c2b005968e8820ec6102228f1fad511c119454c [file] [log] [blame]
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]1; Test STOCGs that are presented as selects.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
4
5declare void @foo(i64 *)
6
7; Test with the loaded value first.
8define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
9; CHECK-LABEL: f1:
10; CHECK: clfi %r4, 42
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]11; CHECK: stocghe %r3, 0(%r2)
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]12; CHECK: br %r14
13 %cond = icmp ult i32 %limit, 42
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]14 %orig = load i64 , i64 *%ptr
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]15 %res = select i1 %cond, i64 %orig, i64 %alt
16 store i64 %res, i64 *%ptr
17 ret void
18}
19
20; ...and with the loaded value second
21define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
22; CHECK-LABEL: f2:
23; CHECK: clfi %r4, 42
24; CHECK: stocgl %r3, 0(%r2)
25; CHECK: br %r14
26 %cond = icmp ult i32 %limit, 42
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]27 %orig = load i64 , i64 *%ptr
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]28 %res = select i1 %cond, i64 %alt, i64 %orig
29 store i64 %res, i64 *%ptr
30 ret void
31}
32
33; Check the high end of the aligned STOCG range.
34define void @f3(i64 *%base, i64 %alt, i32 %limit) {
35; CHECK-LABEL: f3:
36; CHECK: clfi %r4, 42
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]37; CHECK: stocghe %r3, 524280(%r2)
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]38; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]39 %ptr = getelementptr i64, i64 *%base, i64 65535
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]40 %cond = icmp ult i32 %limit, 42
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]41 %orig = load i64 , i64 *%ptr
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]42 %res = select i1 %cond, i64 %orig, i64 %alt
43 store i64 %res, i64 *%ptr
44 ret void
45}
46
47; Check the next doubleword up. Other sequences besides this one would be OK.
48define void @f4(i64 *%base, i64 %alt, i32 %limit) {
49; CHECK-LABEL: f4:
50; CHECK: agfi %r2, 524288
51; CHECK: clfi %r4, 42
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]52; CHECK: stocghe %r3, 0(%r2)
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]53; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]54 %ptr = getelementptr i64, i64 *%base, i64 65536
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]55 %cond = icmp ult i32 %limit, 42
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]56 %orig = load i64 , i64 *%ptr
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]57 %res = select i1 %cond, i64 %orig, i64 %alt
58 store i64 %res, i64 *%ptr
59 ret void
60}
61
62; Check the low end of the STOCG range.
63define void @f5(i64 *%base, i64 %alt, i32 %limit) {
64; CHECK-LABEL: f5:
65; CHECK: clfi %r4, 42
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]66; CHECK: stocghe %r3, -524288(%r2)
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]67; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]68 %ptr = getelementptr i64, i64 *%base, i64 -65536
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]69 %cond = icmp ult i32 %limit, 42
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]70 %orig = load i64 , i64 *%ptr
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]71 %res = select i1 %cond, i64 %orig, i64 %alt
72 store i64 %res, i64 *%ptr
73 ret void
74}
75
76; Check the next doubleword down, with the same comments as f4.
77define void @f6(i64 *%base, i64 %alt, i32 %limit) {
78; CHECK-LABEL: f6:
79; CHECK: agfi %r2, -524296
80; CHECK: clfi %r4, 42
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]81; CHECK: stocghe %r3, 0(%r2)
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]82; CHECK: br %r14
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]83 %ptr = getelementptr i64, i64 *%base, i64 -65537
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]84 %cond = icmp ult i32 %limit, 42
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]85 %orig = load i64 , i64 *%ptr
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]86 %res = select i1 %cond, i64 %orig, i64 %alt
87 store i64 %res, i64 *%ptr
88 ret void
89}
90
91; Try a frame index base.
92define void @f7(i64 %alt, i32 %limit) {
93; CHECK-LABEL: f7:
94; CHECK: brasl %r14, foo@PLT
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]95; CHECK: stocghe {{%r[0-9]+}}, {{[0-9]+}}(%r15)
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]96; CHECK: brasl %r14, foo@PLT
97; CHECK: br %r14
98 %ptr = alloca i64
99 call void @foo(i64 *%ptr)
100 %cond = icmp ult i32 %limit, 42
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]101 %orig = load i64 , i64 *%ptr
Richard Sandiforda68e6f52013-07-25 08:57:02 +0000[diff] [blame]102 %res = select i1 %cond, i64 %orig, i64 %alt
103 store i64 %res, i64 *%ptr
104 call void @foo(i64 *%ptr)
105 ret void
106}
107
108; Test that conditionally-executed stores do not use STOC, since STOC
109; is allowed to trap even when the condition is false.
110define void @f8(i64 %a, i64 %b, i64 *%dest) {
111; CHECK-LABEL: f8:
112; CHECK-NOT: stocg %r3, 0(%r4)
113; CHECK: br %r14
114entry:
115 %cmp = icmp ule i64 %a, %b
116 br i1 %cmp, label %store, label %exit
117
118store:
119 store i64 %b, i64 *%dest
120 br label %exit
121
122exit:
123 ret void
124}