blob: 2e7dab6cb56827c96eb5619cbae18ddff5fc1e5e [file] [log] [blame]
Tom Stellardcb97e3a2013-04-15 17:51:35 +00001//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000011#ifndef LLVM_LIB_TARGET_R600_SIDEFINES_H
12#define LLVM_LIB_TARGET_R600_SIDEFINES_H
Tom Stellardcb97e3a2013-04-15 17:51:35 +000013
Tom Stellard16a9a202013-08-14 23:24:17 +000014namespace SIInstrFlags {
Matt Arsenaulte2fabd32014-07-29 18:51:56 +000015// This needs to be kept in sync with the field bits in InstSI.
Tom Stellard16a9a202013-08-14 23:24:17 +000016enum {
Michel Danzer20680b12013-08-16 16:19:24 +000017 MIMG = 1 << 3,
Tom Stellard93fabce2013-10-10 17:11:55 +000018 SMRD = 1 << 4,
19 VOP1 = 1 << 5,
20 VOP2 = 1 << 6,
21 VOP3 = 1 << 7,
Tom Stellard82166022013-11-13 23:36:37 +000022 VOPC = 1 << 8,
Matt Arsenaulte2fabd32014-07-29 18:51:56 +000023 SALU = 1 << 9,
24 MUBUF = 1 << 10,
Matt Arsenault3f981402014-09-15 15:41:53 +000025 MTBUF = 1 << 11,
26 FLAT = 1 << 12
Tom Stellard16a9a202013-08-14 23:24:17 +000027};
28}
29
Matt Arsenault9783e002014-09-29 15:50:26 +000030namespace SIInstrFlags {
31 enum Flags {
32 // First 4 bits are the instruction encoding
33 VM_CNT = 1 << 0,
34 EXP_CNT = 1 << 1,
35 LGKM_CNT = 1 << 2
36 };
37}
38
39namespace SISrcMods {
40 enum {
41 NEG = 1 << 0,
42 ABS = 1 << 1
43 };
44}
45
Matt Arsenault97069782014-09-30 19:49:48 +000046namespace SIOutMods {
47 enum {
48 NONE = 0,
49 MUL2 = 1,
50 MUL4 = 2,
51 DIV2 = 3
52 };
53}
54
Tom Stellardcb97e3a2013-04-15 17:51:35 +000055#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
Michel Danzer49812b52013-07-10 16:37:07 +000056#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
57#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
Tom Stellardcb97e3a2013-04-15 17:51:35 +000058#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
59#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
60#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
61#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
62#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
Michel Danzer49812b52013-07-10 16:37:07 +000063#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
Tom Stellardb02094e2014-07-21 15:45:01 +000064#define S_00B02C_SCRATCH_EN(x) (((x) & 0x1) << 0)
Michel Danzer49812b52013-07-10 16:37:07 +000065#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
Tom Stellardcb97e3a2013-04-15 17:51:35 +000066#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
67
Matt Arsenault0989d512014-06-26 17:22:30 +000068
69#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
70#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
71#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
72#define C_00B848_VGPRS 0xFFFFFFC0
73#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
74#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
75#define C_00B848_SGPRS 0xFFFFFC3F
76#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
77#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
78#define C_00B848_PRIORITY 0xFFFFF3FF
79#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
80#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
81#define C_00B848_FLOAT_MODE 0xFFF00FFF
82#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
83#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
84#define C_00B848_PRIV 0xFFEFFFFF
85#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
86#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
87#define C_00B848_DX10_CLAMP 0xFFDFFFFF
88#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
89#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
90#define C_00B848_DEBUG_MODE 0xFFBFFFFF
91#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
92#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
93#define C_00B848_IEEE_MODE 0xFF7FFFFF
94
95
96// Helpers for setting FLOAT_MODE
97#define FP_ROUND_ROUND_TO_NEAREST 0
98#define FP_ROUND_ROUND_TO_INF 1
99#define FP_ROUND_ROUND_TO_NEGINF 2
100#define FP_ROUND_ROUND_TO_ZERO 3
101
102// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
103// precision.
104#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
105#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
106
107#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
108#define FP_DENORM_FLUSH_OUT 1
109#define FP_DENORM_FLUSH_IN 2
110#define FP_DENORM_FLUSH_NONE 3
111
112
113// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
114// precision.
115#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
116#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
117
Tom Stellardb02094e2014-07-21 15:45:01 +0000118#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
119#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
120
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000121#endif