blob: ffa3c22fd8302167d9b56b675010744509275ec7 [file] [log] [blame]
Matthias Braune2d2ce92017-08-01 22:20:41 +00001; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SAFE %s
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +00002; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX -check-prefix=CHECK-VSX-SAFE %s
Matthias Braune2d2ce92017-08-01 22:20:41 +00003; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast -enable-unsafe-fp-math -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK -check-prefix=CHECK-UNSAFE %s
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +00004; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -enable-unsafe-fp-math -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX -check-prefix=CHECK-UNSAFE-VSX %s
Olivier Sallenave04515322015-01-07 20:54:17 +00005
6define double @test_FMADD_ASSOC1(double %A, double %B, double %C,
7 double %D, double %E) {
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +00008 %F = fmul double %A, %B ; <double> [#uses=1]
9 %G = fmul double %C, %D ; <double> [#uses=1]
10 %H = fadd double %F, %G ; <double> [#uses=1]
11 %I = fadd double %H, %E ; <double> [#uses=1]
12 ret double %I
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +000013; CHECK-SAFE-LABEL: test_FMADD_ASSOC1:
14; CHECK-SAFE: fmul
15; CHECK-SAFE-NEXT: fmadd
16; CHECK-SAFE-NEXT: fadd
17; CHECK-SAFE-NEXT: blr
Olivier Sallenave04515322015-01-07 20:54:17 +000018
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +000019; CHECK-UNSAFE-LABEL: test_FMADD_ASSOC1:
20; CHECK-UNSAFE: fmadd
21; CHECK-UNSAFE-NEXT: fmadd
22; CHECK-UNSAFE-NEXT: blr
23
24; CHECK-VSX-SAFE-LABEL: test_FMADD_ASSOC1:
25; CHECK-VSX-SAFE: xsmuldp
26; CHECK-VSX-SAFE-NEXT: xsmaddadp
27; CHECK-VSX-SAFE-NEXT: xsadddp
28; CHECK-VSX-SAFE-NEXT: blr
29
30; CHECK-VSX-UNSAFE-LABEL: test_FMADD_ASSOC1:
31; CHECK-VSX-UNSAFE: xsmaddmdp
32; CHECK-VSX-UNSAFE-NEXT: xsmaddadp
33; CHECK-VSX-UNSAFE-NEXT: fmr
34; CHECK-VSX-UNSAFE-NEXT: blr
Olivier Sallenave04515322015-01-07 20:54:17 +000035}
36
37define double @test_FMADD_ASSOC2(double %A, double %B, double %C,
38 double %D, double %E) {
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +000039 %F = fmul double %A, %B ; <double> [#uses=1]
40 %G = fmul double %C, %D ; <double> [#uses=1]
41 %H = fadd double %F, %G ; <double> [#uses=1]
42 %I = fadd double %E, %H ; <double> [#uses=1]
43 ret double %I
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +000044; CHECK-SAFE-LABEL: test_FMADD_ASSOC2:
45; CHECK-SAFE: fmul
46; CHECK-SAFE-NEXT: fmadd
47; CHECK-SAFE-NEXT: fadd
48; CHECK-SAFE-NEXT: blr
Olivier Sallenave04515322015-01-07 20:54:17 +000049
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +000050; CHECK-UNSAFE-LABEL: test_FMADD_ASSOC2:
51; CHECK-UNSAFE: fmadd
52; CHECK-UNSAFE-NEXT: fmadd
53; CHECK-UNSAFE-NEXT: blr
54
55; CHECK-VSX-SAFE-LABEL: test_FMADD_ASSOC2:
56; CHECK-VSX-SAFE: xsmuldp
57; CHECK-VSX-SAFE-NEXT: xsmaddadp
58; CHECK-VSX-SAFE-NEXT: xsadddp
59; CHECK-VSX-SAFE-NEXT: blr
60
61; CHECK-VSX-UNSAFE-LABEL: test_FMADD_ASSOC2:
62; CHECK-VSX-UNSAFE: xsmaddmdp
63; CHECK-VSX-UNSAFE-NEXT: xsmaddadp
64; CHECK-VSX-UNSAFE-NEXT: fmr
65; CHECK-VSX-UNSAFE-NEXT: blr
Olivier Sallenave04515322015-01-07 20:54:17 +000066}
67
68define double @test_FMSUB_ASSOC1(double %A, double %B, double %C,
69 double %D, double %E) {
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +000070 %F = fmul double %A, %B ; <double> [#uses=1]
71 %G = fmul double %C, %D ; <double> [#uses=1]
72 %H = fadd double %F, %G ; <double> [#uses=1]
73 %I = fsub double %H, %E ; <double> [#uses=1]
74 ret double %I
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +000075; CHECK-SAFE-LABEL: test_FMSUB_ASSOC1:
76; CHECK-SAFE: fmul
77; CHECK-SAFE-NEXT: fmadd
78; CHECK-SAFE-NEXT: fsub
79; CHECK-SAFE-NEXT: blr
Olivier Sallenave04515322015-01-07 20:54:17 +000080
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +000081; CHECK-UNSAFE-LABEL: test_FMSUB_ASSOC1:
82; CHECK-UNSAFE: fmsub
83; CHECK-UNSAFE-NEXT: fmadd
84; CHECK-UNSAFE-NEXT: blr
85
86; CHECK-SAFE-VSX-LABEL: test_FMSUB_ASSOC1:
87; CHECK-SAFE-VSX: xsmuldp
88; CHECK-SAFE-VSX-NEXT: xsmaddadp
89; CHECK-SAFE-VSX-NEXT: xssubdp
90; CHECK-SAFE-VSX-NEXT: blr
91
92; CHECK-UNSAFE-VSX-LABEL: test_FMSUB_ASSOC1:
93; CHECK-UNSAFE-VSX: xsmsubmdp
94; CHECK-UNSAFE-VSX-NEXT: xsmaddadp
95; CHECK-UNSAFE-VSX-NEXT: fmr
96; CHECK-UNSAFE-VSX-NEXT: blr
Olivier Sallenave04515322015-01-07 20:54:17 +000097}
98
99define double @test_FMSUB_ASSOC2(double %A, double %B, double %C,
100 double %D, double %E) {
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +0000101 %F = fmul double %A, %B ; <double> [#uses=1]
102 %G = fmul double %C, %D ; <double> [#uses=1]
103 %H = fadd double %F, %G ; <double> [#uses=1]
104 %I = fsub double %E, %H ; <double> [#uses=1]
105 ret double %I
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +0000106; CHECK-SAFE-LABEL: test_FMSUB_ASSOC2:
107; CHECK-SAFE: fmul
108; CHECK-SAFE-NEXT: fmadd
109; CHECK-SAFE-NEXT: fsub
110; CHECK-SAFE-NEXT: blr
Olivier Sallenave04515322015-01-07 20:54:17 +0000111
Nicolai Haehnle8813d5d2017-01-31 14:35:37 +0000112; CHECK-UNSAFE-LABEL: test_FMSUB_ASSOC2:
113; CHECK-UNSAFE: fnmsub
114; CHECK-UNSAFE-NEXT: fnmsub
115; CHECK-UNSAFE-NEXT: blr
116
117; CHECK-SAFE-VSX-LABEL: test_FMSUB_ASSOC2:
118; CHECK-SAFE-VSX: xsmuldp
119; CHECK-SAFE-VSX-NEXT: xsmaddadp
120; CHECK-SAFE-VSX-NEXT: xssubdp
121; CHECK-SAFE-VSX-NEXT: blr
122
123; CHECK-UNSAFE-VSX-LABEL: test_FMSUB_ASSOC2:
124; CHECK-UNSAFE-VSX: xsnmsubmdp
125; CHECK-UNSAFE-VSX-NEXT: xsnmsubadp
126; CHECK-UNSAFE-VSX-NEXT: fmr
127; CHECK-UNSAFE-VSX-NEXT: blr
Olivier Sallenave04515322015-01-07 20:54:17 +0000128}
129
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +0000130define double @test_FMADD_ASSOC_EXT1(float %A, float %B, double %C,
131 double %D, double %E) {
132 %F = fmul float %A, %B ; <float> [#uses=1]
133 %G = fpext float %F to double ; <double> [#uses=1]
134 %H = fmul double %C, %D ; <double> [#uses=1]
135 %I = fadd double %H, %G ; <double> [#uses=1]
136 %J = fadd double %I, %E ; <double> [#uses=1]
137 ret double %J
138; CHECK-LABEL: test_FMADD_ASSOC_EXT1:
139; CHECK: fmadd
140; CHECK-NEXT: fmadd
141; CHECK-NEXT: blr
142
143; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT1:
144; CHECK-VSX: xsmaddmdp
145; CHECK-VSX-NEXT: xsmaddadp
146; CHECK-VSX-NEXT: blr
147}
148
149define double @test_FMADD_ASSOC_EXT2(float %A, float %B, float %C,
150 float %D, double %E) {
151 %F = fmul float %A, %B ; <float> [#uses=1]
152 %G = fmul float %C, %D ; <float> [#uses=1]
153 %H = fadd float %F, %G ; <float> [#uses=1]
154 %I = fpext float %H to double ; <double> [#uses=1]
155 %J = fadd double %I, %E ; <double> [#uses=1]
156 ret double %J
157; CHECK-LABEL: test_FMADD_ASSOC_EXT2:
158; CHECK: fmadd
159; CHECK-NEXT: fmadd
160; CHECK-NEXT: blr
161
162; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT2:
163; CHECK-VSX: xsmaddmdp
164; CHECK-VSX-NEXT: xsmaddadp
165; CHECK-VSX-NEXT: fmr
166; CHECK-VSX-NEXT: blr
167}
168
169define double @test_FMADD_ASSOC_EXT3(float %A, float %B, double %C,
170 double %D, double %E) {
171 %F = fmul float %A, %B ; <float> [#uses=1]
172 %G = fpext float %F to double ; <double> [#uses=1]
173 %H = fmul double %C, %D ; <double> [#uses=1]
174 %I = fadd double %H, %G ; <double> [#uses=1]
175 %J = fadd double %E, %I ; <double> [#uses=1]
176 ret double %J
177; CHECK-LABEL: test_FMADD_ASSOC_EXT3:
178; CHECK: fmadd
179; CHECK-NEXT: fmadd
180; CHECK-NEXT: blr
181
182; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT3:
183; CHECK-VSX: xsmaddmdp
184; CHECK-VSX-NEXT: xsmaddadp
185; CHECK-VSX-NEXT: blr
186}
187
188define double @test_FMADD_ASSOC_EXT4(float %A, float %B, float %C,
189 float %D, double %E) {
190 %F = fmul float %A, %B ; <float> [#uses=1]
191 %G = fmul float %C, %D ; <float> [#uses=1]
192 %H = fadd float %F, %G ; <float> [#uses=1]
193 %I = fpext float %H to double ; <double> [#uses=1]
194 %J = fadd double %E, %I ; <double> [#uses=1]
195 ret double %J
196; CHECK-LABEL: test_FMADD_ASSOC_EXT4:
197; CHECK: fmadd
198; CHECK-NEXT: fmadd
199; CHECK-NEXT: blr
200
201; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT4:
202; CHECK-VSX: xsmaddmdp
203; CHECK-VSX-NEXT: xsmaddadp
204; CHECK-VSX-NEXT: fmr
205; CHECK-VSX-NEXT: blr
206}
207
208define double @test_FMSUB_ASSOC_EXT1(float %A, float %B, double %C,
209 double %D, double %E) {
210 %F = fmul float %A, %B ; <float> [#uses=1]
211 %G = fpext float %F to double ; <double> [#uses=1]
212 %H = fmul double %C, %D ; <double> [#uses=1]
213 %I = fadd double %H, %G ; <double> [#uses=1]
214 %J = fsub double %I, %E ; <double> [#uses=1]
215 ret double %J
216; CHECK-LABEL: test_FMSUB_ASSOC_EXT1:
217; CHECK: fmsub
218; CHECK-NEXT: fmadd
219; CHECK-NEXT: blr
220
221; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT1:
222; CHECK-VSX: xsmsubmdp
223; CHECK-VSX-NEXT: xsmaddadp
224; CHECK-VSX-NEXT: blr
225}
226
227define double @test_FMSUB_ASSOC_EXT2(float %A, float %B, float %C,
228 float %D, double %E) {
229 %F = fmul float %A, %B ; <float> [#uses=1]
230 %G = fmul float %C, %D ; <float> [#uses=1]
231 %H = fadd float %F, %G ; <float> [#uses=1]
232 %I = fpext float %H to double ; <double> [#uses=1]
233 %J = fsub double %I, %E ; <double> [#uses=1]
234 ret double %J
235; CHECK-LABEL: test_FMSUB_ASSOC_EXT2:
236; CHECK: fmsub
237; CHECK-NEXT: fmadd
238; CHECK-NEXT: blr
239
240; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT2:
241; CHECK-VSX: xsmsubmdp
242; CHECK-VSX-NEXT: xsmaddadp
243; CHECK-VSX-NEXT: fmr
244; CHECK-VSX-NEXT: blr
245}
246
247define double @test_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,
248 double %D, double %E) {
249 %F = fmul float %A, %B ; <float> [#uses=1]
250 %G = fpext float %F to double ; <double> [#uses=1]
251 %H = fmul double %C, %D ; <double> [#uses=1]
252 %I = fadd double %H, %G ; <double> [#uses=1]
253 %J = fsub double %E, %I ; <double> [#uses=1]
254 ret double %J
255; CHECK-LABEL: test_FMSUB_ASSOC_EXT3:
256; CHECK: fnmsub
257; CHECK-NEXT: fnmsub
258; CHECK-NEXT: blr
259
260; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT3:
261; CHECK-VSX: xsnmsubmdp
262; CHECK-VSX-NEXT: xsnmsubadp
263; CHECK-VSX-NEXT: fmr
264; CHECK-VSX-NEXT: blr
265}
266
267define double @test_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,
268 float %D, double %E) {
269 %F = fmul float %A, %B ; <float> [#uses=1]
270 %G = fmul float %C, %D ; <float> [#uses=1]
271 %H = fadd float %F, %G ; <float> [#uses=1]
272 %I = fpext float %H to double ; <double> [#uses=1]
273 %J = fsub double %E, %I ; <double> [#uses=1]
274 ret double %J
275; CHECK-LABEL: test_FMSUB_ASSOC_EXT4:
276; CHECK: fnmsub
277; CHECK-NEXT: fnmsub
278; CHECK-NEXT: blr
279
280; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT4:
281; CHECK-VSX: xsnmsubmdp
282; CHECK-VSX-NEXT: xsnmsubadp
283; CHECK-VSX-NEXT: fmr
284; CHECK-VSX-NEXT: blr
285}