blob: 502e541bafc19c7eaa3afce7e50ff2f31cb724e5 [file] [log] [blame]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +00001; Test spilling of FPRs.
2;
Ulrich Weigand49506d72015-05-05 19:28:34 +00003; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
Ulrich Weigand9e3577f2013-05-06 16:17:29 +00004
5; We need to save and restore 8 of the 16 FPRs and allocate an additional
6; 4-byte spill slot, rounded to 8 bytes. The frame size should be exactly
7; 160 + 8 * 8 = 232.
8define void @f1(float *%ptr) {
Stephen Lind24ab202013-07-14 06:24:09 +00009; CHECK-LABEL: f1:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000010; CHECK: aghi %r15, -232
11; CHECK: std %f8, 224(%r15)
12; CHECK: std %f9, 216(%r15)
13; CHECK: std %f10, 208(%r15)
14; CHECK: std %f11, 200(%r15)
15; CHECK: std %f12, 192(%r15)
16; CHECK: std %f13, 184(%r15)
17; CHECK: std %f14, 176(%r15)
18; CHECK: std %f15, 168(%r15)
19; CHECK-NOT: 160(%r15)
20; CHECK: ste [[REGISTER:%f[0-9]+]], 164(%r15)
21; CHECK-NOT: 160(%r15)
22; CHECK: le [[REGISTER]], 164(%r15)
23; CHECK-NOT: 160(%r15)
24; CHECK: ld %f8, 224(%r15)
25; CHECK: ld %f9, 216(%r15)
26; CHECK: ld %f10, 208(%r15)
27; CHECK: ld %f11, 200(%r15)
28; CHECK: ld %f12, 192(%r15)
29; CHECK: ld %f13, 184(%r15)
30; CHECK: ld %f14, 176(%r15)
31; CHECK: ld %f15, 168(%r15)
32; CHECK: aghi %r15, 232
33; CHECK: br %r14
David Blaikiea79ac142015-02-27 21:17:42 +000034 %l0 = load volatile float , float *%ptr
35 %l1 = load volatile float , float *%ptr
36 %l2 = load volatile float , float *%ptr
37 %l3 = load volatile float , float *%ptr
38 %l4 = load volatile float , float *%ptr
39 %l5 = load volatile float , float *%ptr
40 %l6 = load volatile float , float *%ptr
41 %l7 = load volatile float , float *%ptr
42 %l8 = load volatile float , float *%ptr
43 %l9 = load volatile float , float *%ptr
44 %l10 = load volatile float , float *%ptr
45 %l11 = load volatile float , float *%ptr
46 %l12 = load volatile float , float *%ptr
47 %l13 = load volatile float , float *%ptr
48 %l14 = load volatile float , float *%ptr
49 %l15 = load volatile float , float *%ptr
50 %lx = load volatile float , float *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000051 store volatile float %lx, float *%ptr
52 store volatile float %l15, float *%ptr
53 store volatile float %l14, float *%ptr
54 store volatile float %l13, float *%ptr
55 store volatile float %l12, float *%ptr
56 store volatile float %l11, float *%ptr
57 store volatile float %l10, float *%ptr
58 store volatile float %l9, float *%ptr
59 store volatile float %l8, float *%ptr
60 store volatile float %l7, float *%ptr
61 store volatile float %l6, float *%ptr
62 store volatile float %l5, float *%ptr
63 store volatile float %l4, float *%ptr
64 store volatile float %l3, float *%ptr
65 store volatile float %l2, float *%ptr
66 store volatile float %l1, float *%ptr
67 store volatile float %l0, float *%ptr
68 ret void
69}
70
71; Same for doubles, except that the full spill slot is used.
72define void @f2(double *%ptr) {
Stephen Lind24ab202013-07-14 06:24:09 +000073; CHECK-LABEL: f2:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000074; CHECK: aghi %r15, -232
75; CHECK: std %f8, 224(%r15)
76; CHECK: std %f9, 216(%r15)
77; CHECK: std %f10, 208(%r15)
78; CHECK: std %f11, 200(%r15)
79; CHECK: std %f12, 192(%r15)
80; CHECK: std %f13, 184(%r15)
81; CHECK: std %f14, 176(%r15)
82; CHECK: std %f15, 168(%r15)
83; CHECK: std [[REGISTER:%f[0-9]+]], 160(%r15)
84; CHECK: ld [[REGISTER]], 160(%r15)
85; CHECK: ld %f8, 224(%r15)
86; CHECK: ld %f9, 216(%r15)
87; CHECK: ld %f10, 208(%r15)
88; CHECK: ld %f11, 200(%r15)
89; CHECK: ld %f12, 192(%r15)
90; CHECK: ld %f13, 184(%r15)
91; CHECK: ld %f14, 176(%r15)
92; CHECK: ld %f15, 168(%r15)
93; CHECK: aghi %r15, 232
94; CHECK: br %r14
David Blaikiea79ac142015-02-27 21:17:42 +000095 %l0 = load volatile double , double *%ptr
96 %l1 = load volatile double , double *%ptr
97 %l2 = load volatile double , double *%ptr
98 %l3 = load volatile double , double *%ptr
99 %l4 = load volatile double , double *%ptr
100 %l5 = load volatile double , double *%ptr
101 %l6 = load volatile double , double *%ptr
102 %l7 = load volatile double , double *%ptr
103 %l8 = load volatile double , double *%ptr
104 %l9 = load volatile double , double *%ptr
105 %l10 = load volatile double , double *%ptr
106 %l11 = load volatile double , double *%ptr
107 %l12 = load volatile double , double *%ptr
108 %l13 = load volatile double , double *%ptr
109 %l14 = load volatile double , double *%ptr
110 %l15 = load volatile double , double *%ptr
111 %lx = load volatile double , double *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000112 store volatile double %lx, double *%ptr
113 store volatile double %l15, double *%ptr
114 store volatile double %l14, double *%ptr
115 store volatile double %l13, double *%ptr
116 store volatile double %l12, double *%ptr
117 store volatile double %l11, double *%ptr
118 store volatile double %l10, double *%ptr
119 store volatile double %l9, double *%ptr
120 store volatile double %l8, double *%ptr
121 store volatile double %l7, double *%ptr
122 store volatile double %l6, double *%ptr
123 store volatile double %l5, double *%ptr
124 store volatile double %l4, double *%ptr
125 store volatile double %l3, double *%ptr
126 store volatile double %l2, double *%ptr
127 store volatile double %l1, double *%ptr
128 store volatile double %l0, double *%ptr
129 ret void
130}
131
132; The long double case needs a 16-byte spill slot.
133define void @f3(fp128 *%ptr) {
Stephen Lind24ab202013-07-14 06:24:09 +0000134; CHECK-LABEL: f3:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000135; CHECK: aghi %r15, -240
136; CHECK: std %f8, 232(%r15)
137; CHECK: std %f9, 224(%r15)
138; CHECK: std %f10, 216(%r15)
139; CHECK: std %f11, 208(%r15)
140; CHECK: std %f12, 200(%r15)
141; CHECK: std %f13, 192(%r15)
142; CHECK: std %f14, 184(%r15)
143; CHECK: std %f15, 176(%r15)
144; CHECK: std [[REGISTER1:%f[0-9]+]], 160(%r15)
145; CHECK: std [[REGISTER2:%f[0-9]+]], 168(%r15)
146; CHECK: ld [[REGISTER1]], 160(%r15)
147; CHECK: ld [[REGISTER2]], 168(%r15)
148; CHECK: ld %f8, 232(%r15)
149; CHECK: ld %f9, 224(%r15)
150; CHECK: ld %f10, 216(%r15)
151; CHECK: ld %f11, 208(%r15)
152; CHECK: ld %f12, 200(%r15)
153; CHECK: ld %f13, 192(%r15)
154; CHECK: ld %f14, 184(%r15)
155; CHECK: ld %f15, 176(%r15)
156; CHECK: aghi %r15, 240
157; CHECK: br %r14
David Blaikiea79ac142015-02-27 21:17:42 +0000158 %l0 = load volatile fp128 , fp128 *%ptr
159 %l1 = load volatile fp128 , fp128 *%ptr
160 %l4 = load volatile fp128 , fp128 *%ptr
161 %l5 = load volatile fp128 , fp128 *%ptr
162 %l8 = load volatile fp128 , fp128 *%ptr
163 %l9 = load volatile fp128 , fp128 *%ptr
164 %l12 = load volatile fp128 , fp128 *%ptr
165 %l13 = load volatile fp128 , fp128 *%ptr
166 %lx = load volatile fp128 , fp128 *%ptr
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000167 store volatile fp128 %lx, fp128 *%ptr
168 store volatile fp128 %l13, fp128 *%ptr
169 store volatile fp128 %l12, fp128 *%ptr
170 store volatile fp128 %l9, fp128 *%ptr
171 store volatile fp128 %l8, fp128 *%ptr
172 store volatile fp128 %l5, fp128 *%ptr
173 store volatile fp128 %l4, fp128 *%ptr
174 store volatile fp128 %l1, fp128 *%ptr
175 store volatile fp128 %l0, fp128 *%ptr
176 ret void
177}