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gerrit-public.fairphone.software / toolchain / llvm-project / e93c63d468d36e67cb15d183ecc6b8216c87c138 / . / llvm / test / CodeGen / SystemZ / int-cmp-43.ll
blob: 700db89435b6670c4793636935f05531009de028 [file] [log] [blame]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]1; Test 64-bit comparisons in which the second operand is a PC-relative
2; variable.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5
6@g = global i64 1
Richard Sandiford46af5a22013-05-30 09:45:42 +0000[diff] [blame]7@h = global i64 1, align 4, section "foo"
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]8
9; Check signed comparisons.
10define i64 @f1(i64 %src1) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]11; CHECK-LABEL: f1:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]12; CHECK: cgrl %r2, g
Ulrich Weigand2eb027d2016-04-07 16:11:44 +0000[diff] [blame]13; CHECK-NEXT: blr %r14
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]14; CHECK: br %r14
15entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]16 %src2 = load i64 , i64 *@g
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]17 %cond = icmp slt i64 %src1, %src2
18 br i1 %cond, label %exit, label %mulb
19mulb:
20 %mul = mul i64 %src1, %src1
21 br label %exit
22exit:
23 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
24 ret i64 %res
25}
26
27; Check unsigned comparisons.
28define i64 @f2(i64 %src1) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]29; CHECK-LABEL: f2:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]30; CHECK: clgrl %r2, g
Ulrich Weigand2eb027d2016-04-07 16:11:44 +0000[diff] [blame]31; CHECK-NEXT: blr %r14
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]32; CHECK: br %r14
33entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]34 %src2 = load i64 , i64 *@g
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]35 %cond = icmp ult i64 %src1, %src2
36 br i1 %cond, label %exit, label %mulb
37mulb:
38 %mul = mul i64 %src1, %src1
39 br label %exit
40exit:
41 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
42 ret i64 %res
43}
44
45; Check equality, which can use CRL or CLRL.
46define i64 @f3(i64 %src1) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]47; CHECK-LABEL: f3:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]48; CHECK: c{{l?}}grl %r2, g
Ulrich Weigand2eb027d2016-04-07 16:11:44 +0000[diff] [blame]49; CHECK-NEXT: ber %r14
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]50; CHECK: br %r14
51entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]52 %src2 = load i64 , i64 *@g
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]53 %cond = icmp eq i64 %src1, %src2
54 br i1 %cond, label %exit, label %mulb
55mulb:
56 %mul = mul i64 %src1, %src1
57 br label %exit
58exit:
59 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
60 ret i64 %res
61}
62
63; ...likewise inequality.
64define i64 @f4(i64 %src1) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]65; CHECK-LABEL: f4:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]66; CHECK: c{{l?}}grl %r2, g
Ulrich Weigand2eb027d2016-04-07 16:11:44 +0000[diff] [blame]67; CHECK-NEXT: blhr %r14
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]68; CHECK: br %r14
69entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]70 %src2 = load i64 , i64 *@g
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]71 %cond = icmp ne i64 %src1, %src2
72 br i1 %cond, label %exit, label %mulb
73mulb:
74 %mul = mul i64 %src1, %src1
75 br label %exit
76exit:
77 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
78 ret i64 %res
79}
Richard Sandiford46af5a22013-05-30 09:45:42 +0000[diff] [blame]80
81; Repeat f1 with an unaligned address.
82define i64 @f5(i64 %src1) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]83; CHECK-LABEL: f5:
Richard Sandiford46af5a22013-05-30 09:45:42 +0000[diff] [blame]84; CHECK: larl [[REG:%r[0-5]]], h
85; CHECK: cg %r2, 0([[REG]])
Ulrich Weigand2eb027d2016-04-07 16:11:44 +0000[diff] [blame]86; CHECK-NEXT: blr %r14
Richard Sandiford46af5a22013-05-30 09:45:42 +0000[diff] [blame]87; CHECK: br %r14
88entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]89 %src2 = load i64 , i64 *@h, align 4
Richard Sandiford46af5a22013-05-30 09:45:42 +0000[diff] [blame]90 %cond = icmp slt i64 %src1, %src2
91 br i1 %cond, label %exit, label %mulb
92mulb:
93 %mul = mul i64 %src1, %src1
94 br label %exit
95exit:
96 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
97 ret i64 %res
98}
Richard Sandiford24e597b2013-08-23 11:27:19 +0000[diff] [blame]99
100; Check the comparison can be reversed if that allows CGRL to be used.
101define i64 @f6(i64 %src2) {
102; CHECK-LABEL: f6:
103; CHECK: cgrl %r2, g
Ulrich Weigand2eb027d2016-04-07 16:11:44 +0000[diff] [blame]104; CHECK-NEXT: bhr %r14
Richard Sandiford24e597b2013-08-23 11:27:19 +0000[diff] [blame]105; CHECK: br %r14
106entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]107 %src1 = load i64 , i64 *@g
Richard Sandiford24e597b2013-08-23 11:27:19 +0000[diff] [blame]108 %cond = icmp slt i64 %src1, %src2
109 br i1 %cond, label %exit, label %mulb
110mulb:
111 %mul = mul i64 %src2, %src2
112 br label %exit
113exit:
114 %res = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
115 ret i64 %res
116}