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Simon Pilgrim5b2fd592017-02-06 18:57:51 +00001; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Simon Pilgrimfea153f2017-05-06 19:11:59 +00002; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512F
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512VL
Simon Pilgrim5b2fd592017-02-06 18:57:51 +00005
Simon Pilgrim5b2fd592017-02-06 18:57:51 +00006; fold (abs c1) -> c2
7define <4 x i32> @combine_v4i32_abs_constant() {
8; CHECK-LABEL: combine_v4i32_abs_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00009; CHECK: # %bb.0:
Simon Pilgrimcf2da962017-03-14 21:26:58 +000010; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [0,1,3,2147483648]
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000011; CHECK-NEXT: retq
12 %1 = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> <i32 0, i32 -1, i32 3, i32 -2147483648>)
13 ret <4 x i32> %1
14}
15
16define <16 x i16> @combine_v16i16_abs_constant() {
17; CHECK-LABEL: combine_v16i16_abs_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000018; CHECK: # %bb.0:
Simon Pilgrimcf2da962017-03-14 21:26:58 +000019; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = [0,1,1,3,3,7,7,255,255,4096,4096,32767,32767,32768,32768,0]
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000020; CHECK-NEXT: retq
21 %1 = call <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16> <i16 0, i16 1, i16 -1, i16 3, i16 -3, i16 7, i16 -7, i16 255, i16 -255, i16 4096, i16 -4096, i16 32767, i16 -32767, i16 -32768, i16 32768, i16 65536>)
22 ret <16 x i16> %1
23}
24
25; fold (abs (abs x)) -> (abs x)
Simon Pilgrimd0649f92017-10-19 14:59:26 +000026define i32 @combine_i32_abs_abs(i32 %a) {
27; CHECK-LABEL: combine_i32_abs_abs:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000028; CHECK: # %bb.0:
Simon Pilgrimfdd63d12017-10-19 15:02:24 +000029; CHECK-NEXT: movl %edi, %eax
Simon Pilgrimd0649f92017-10-19 14:59:26 +000030; CHECK-NEXT: negl %eax
Simon Pilgrimfdd63d12017-10-19 15:02:24 +000031; CHECK-NEXT: cmovll %edi, %eax
Simon Pilgrimd0649f92017-10-19 14:59:26 +000032; CHECK-NEXT: retq
33 %n1 = sub i32 zeroinitializer, %a
34 %b1 = icmp slt i32 %a, zeroinitializer
35 %a1 = select i1 %b1, i32 %n1, i32 %a
36 %n2 = sub i32 zeroinitializer, %a1
37 %b2 = icmp sgt i32 %a1, zeroinitializer
38 %a2 = select i1 %b2, i32 %a1, i32 %n2
39 ret i32 %a2
40}
41
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000042define <8 x i16> @combine_v8i16_abs_abs(<8 x i16> %a) {
43; CHECK-LABEL: combine_v8i16_abs_abs:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000044; CHECK: # %bb.0:
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000045; CHECK-NEXT: vpabsw %xmm0, %xmm0
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000046; CHECK-NEXT: retq
Simon Pilgrimb4a9eea2017-02-07 13:15:09 +000047 %a1 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a)
Simon Pilgrim2c154472017-05-06 13:44:42 +000048 %s2 = ashr <8 x i16> %a1, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
49 %a2 = add <8 x i16> %a1, %s2
50 %x2 = xor <8 x i16> %a2, %s2
51 ret <8 x i16> %x2
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000052}
53
54define <32 x i8> @combine_v32i8_abs_abs(<32 x i8> %a) {
55; CHECK-LABEL: combine_v32i8_abs_abs:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000056; CHECK: # %bb.0:
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000057; CHECK-NEXT: vpabsb %ymm0, %ymm0
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000058; CHECK-NEXT: retq
Simon Pilgrimb4a9eea2017-02-07 13:15:09 +000059 %n1 = sub <32 x i8> zeroinitializer, %a
60 %b1 = icmp slt <32 x i8> %a, zeroinitializer
61 %a1 = select <32 x i1> %b1, <32 x i8> %n1, <32 x i8> %a
62 %a2 = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a1)
63 ret <32 x i8> %a2
64}
65
66define <4 x i64> @combine_v4i64_abs_abs(<4 x i64> %a) {
Simon Pilgrimfea153f2017-05-06 19:11:59 +000067; AVX2-LABEL: combine_v4i64_abs_abs:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000068; AVX2: # %bb.0:
Dinar Temirbulatovaead31a2017-07-27 17:47:01 +000069; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
Simon Pilgrimca3a63a2017-05-09 13:14:40 +000070; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
71; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
72; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0
73; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm1
Simon Pilgrimfea153f2017-05-06 19:11:59 +000074; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
75; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
76; AVX2-NEXT: retq
77;
78; AVX512F-LABEL: combine_v4i64_abs_abs:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000079; AVX512F: # %bb.0:
Francis Visoiu Mistriha8a83d12017-12-07 10:40:31 +000080; AVX512F-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
Simon Pilgrimfea153f2017-05-06 19:11:59 +000081; AVX512F-NEXT: vpabsq %zmm0, %zmm0
Francis Visoiu Mistriha8a83d12017-12-07 10:40:31 +000082; AVX512F-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
Simon Pilgrimfea153f2017-05-06 19:11:59 +000083; AVX512F-NEXT: retq
84;
85; AVX512VL-LABEL: combine_v4i64_abs_abs:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000086; AVX512VL: # %bb.0:
Simon Pilgrimfea153f2017-05-06 19:11:59 +000087; AVX512VL-NEXT: vpabsq %ymm0, %ymm0
88; AVX512VL-NEXT: retq
Simon Pilgrimb4a9eea2017-02-07 13:15:09 +000089 %n1 = sub <4 x i64> zeroinitializer, %a
90 %b1 = icmp slt <4 x i64> %a, zeroinitializer
91 %a1 = select <4 x i1> %b1, <4 x i64> %n1, <4 x i64> %a
92 %n2 = sub <4 x i64> zeroinitializer, %a1
93 %b2 = icmp sgt <4 x i64> %a1, zeroinitializer
94 %a2 = select <4 x i1> %b2, <4 x i64> %a1, <4 x i64> %n2
95 ret <4 x i64> %a2
Simon Pilgrim5b2fd592017-02-06 18:57:51 +000096}
97
98; fold (abs x) -> x iff not-negative
99define <16 x i8> @combine_v16i8_abs_constant(<16 x i8> %a) {
Uriel Korach5d5da5f2017-09-13 09:02:36 +0000100; AVX2-LABEL: combine_v16i8_abs_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000101; AVX2: # %bb.0:
Uriel Korach5d5da5f2017-09-13 09:02:36 +0000102; AVX2-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
103; AVX2-NEXT: retq
104;
105; AVX512F-LABEL: combine_v16i8_abs_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000106; AVX512F: # %bb.0:
Uriel Korach5d5da5f2017-09-13 09:02:36 +0000107; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
108; AVX512F-NEXT: retq
109;
110; AVX512VL-LABEL: combine_v16i8_abs_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000111; AVX512VL: # %bb.0:
Uriel Korach5d5da5f2017-09-13 09:02:36 +0000112; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
113; AVX512VL-NEXT: retq
Simon Pilgrim5b2fd592017-02-06 18:57:51 +0000114 %1 = insertelement <16 x i8> undef, i8 15, i32 0
115 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer
116 %3 = and <16 x i8> %a, %2
117 %4 = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %3)
118 ret <16 x i8> %4
119}
120
121define <8 x i32> @combine_v8i32_abs_pos(<8 x i32> %a) {
122; CHECK-LABEL: combine_v8i32_abs_pos:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000123; CHECK: # %bb.0:
Simon Pilgrim5b2fd592017-02-06 18:57:51 +0000124; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0
Simon Pilgrim5b2fd592017-02-06 18:57:51 +0000125; CHECK-NEXT: retq
126 %1 = lshr <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
127 %2 = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %1)
128 ret <8 x i32> %2
129}
130
131declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
132declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
133declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
134
135declare <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8>) nounwind readnone
136declare <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32>) nounwind readnone
137declare <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16>) nounwind readnone