Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 1 | //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 10 | #include "Hexagon.h" |
| 11 | #include "HexagonFixupKinds.h" |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 12 | #include "HexagonMCTargetDesc.h" |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 13 | #include "MCTargetDesc/HexagonBaseInfo.h" |
| 14 | #include "MCTargetDesc/HexagonMCInstrInfo.h" |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 15 | #include "llvm/MC/MCAsmBackend.h" |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 16 | #include "llvm/MC/MCAssembler.h" |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 17 | #include "llvm/MC/MCELFObjectWriter.h" |
Colin LeMahieu | a675077 | 2015-06-03 17:34:16 +0000 | [diff] [blame] | 18 | #include "llvm/MC/MCFixupKindInfo.h" |
Colin LeMahieu | be8c453 | 2015-06-05 16:00:11 +0000 | [diff] [blame] | 19 | #include "llvm/MC/MCInstrInfo.h" |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 20 | #include "llvm/Support/Debug.h" |
Colin LeMahieu | a675077 | 2015-06-03 17:34:16 +0000 | [diff] [blame] | 21 | #include "llvm/Support/TargetRegistry.h" |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 22 | |
| 23 | using namespace llvm; |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 24 | using namespace Hexagon; |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 25 | |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 26 | #define DEBUG_TYPE "hexagon-asm-backend" |
| 27 | |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 28 | namespace { |
| 29 | |
| 30 | class HexagonAsmBackend : public MCAsmBackend { |
Colin LeMahieu | a675077 | 2015-06-03 17:34:16 +0000 | [diff] [blame] | 31 | uint8_t OSABI; |
| 32 | StringRef CPU; |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 33 | mutable uint64_t relaxedCnt; |
| 34 | std::unique_ptr <MCInstrInfo> MCII; |
| 35 | std::unique_ptr <MCInst *> RelaxTarget; |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 36 | public: |
Colin LeMahieu | a675077 | 2015-06-03 17:34:16 +0000 | [diff] [blame] | 37 | HexagonAsmBackend(Target const &T, uint8_t OSABI, StringRef CPU) : |
| 38 | OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *){} |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 39 | |
Colin LeMahieu | a675077 | 2015-06-03 17:34:16 +0000 | [diff] [blame] | 40 | MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { |
| 41 | return createHexagonELFObjectWriter(OS, OSABI, CPU); |
| 42 | } |
| 43 | |
| 44 | unsigned getNumFixupKinds() const override { |
| 45 | return Hexagon::NumTargetFixupKinds; |
| 46 | } |
| 47 | |
| 48 | const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { |
| 49 | const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = { |
| 50 | // This table *must* be in same the order of fixup_* kinds in |
| 51 | // HexagonFixupKinds.h. |
| 52 | // |
| 53 | // namei offset bits flags |
| 54 | {"fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 55 | {"fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 56 | {"fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 57 | {"fixup_Hexagon_LO16", 0, 32, 0}, |
| 58 | {"fixup_Hexagon_HI16", 0, 32, 0}, |
| 59 | {"fixup_Hexagon_32", 0, 32, 0}, |
| 60 | {"fixup_Hexagon_16", 0, 32, 0}, |
| 61 | {"fixup_Hexagon_8", 0, 32, 0}, |
| 62 | {"fixup_Hexagon_GPREL16_0", 0, 32, 0}, |
| 63 | {"fixup_Hexagon_GPREL16_1", 0, 32, 0}, |
| 64 | {"fixup_Hexagon_GPREL16_2", 0, 32, 0}, |
| 65 | {"fixup_Hexagon_GPREL16_3", 0, 32, 0}, |
| 66 | {"fixup_Hexagon_HL16", 0, 32, 0}, |
| 67 | {"fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 68 | {"fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 69 | {"fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 70 | {"fixup_Hexagon_32_6_X", 0, 32, 0}, |
| 71 | {"fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 72 | {"fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 73 | {"fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 74 | {"fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 75 | {"fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 76 | {"fixup_Hexagon_16_X", 0, 32, 0}, |
| 77 | {"fixup_Hexagon_12_X", 0, 32, 0}, |
| 78 | {"fixup_Hexagon_11_X", 0, 32, 0}, |
| 79 | {"fixup_Hexagon_10_X", 0, 32, 0}, |
| 80 | {"fixup_Hexagon_9_X", 0, 32, 0}, |
| 81 | {"fixup_Hexagon_8_X", 0, 32, 0}, |
| 82 | {"fixup_Hexagon_7_X", 0, 32, 0}, |
| 83 | {"fixup_Hexagon_6_X", 0, 32, 0}, |
| 84 | {"fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 85 | {"fixup_Hexagon_COPY", 0, 32, 0}, |
| 86 | {"fixup_Hexagon_GLOB_DAT", 0, 32, 0}, |
| 87 | {"fixup_Hexagon_JMP_SLOT", 0, 32, 0}, |
| 88 | {"fixup_Hexagon_RELATIVE", 0, 32, 0}, |
| 89 | {"fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 90 | {"fixup_Hexagon_GOTREL_LO16", 0, 32, 0}, |
| 91 | {"fixup_Hexagon_GOTREL_HI16", 0, 32, 0}, |
| 92 | {"fixup_Hexagon_GOTREL_32", 0, 32, 0}, |
| 93 | {"fixup_Hexagon_GOT_LO16", 0, 32, 0}, |
| 94 | {"fixup_Hexagon_GOT_HI16", 0, 32, 0}, |
| 95 | {"fixup_Hexagon_GOT_32", 0, 32, 0}, |
| 96 | {"fixup_Hexagon_GOT_16", 0, 32, 0}, |
| 97 | {"fixup_Hexagon_DTPMOD_32", 0, 32, 0}, |
| 98 | {"fixup_Hexagon_DTPREL_LO16", 0, 32, 0}, |
| 99 | {"fixup_Hexagon_DTPREL_HI16", 0, 32, 0}, |
| 100 | {"fixup_Hexagon_DTPREL_32", 0, 32, 0}, |
| 101 | {"fixup_Hexagon_DTPREL_16", 0, 32, 0}, |
| 102 | {"fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 103 | {"fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 104 | {"fixup_Hexagon_GD_GOT_LO16", 0, 32, 0}, |
| 105 | {"fixup_Hexagon_GD_GOT_HI16", 0, 32, 0}, |
| 106 | {"fixup_Hexagon_GD_GOT_32", 0, 32, 0}, |
| 107 | {"fixup_Hexagon_GD_GOT_16", 0, 32, 0}, |
| 108 | {"fixup_Hexagon_LD_GOT_LO16", 0, 32, 0}, |
| 109 | {"fixup_Hexagon_LD_GOT_HI16", 0, 32, 0}, |
| 110 | {"fixup_Hexagon_LD_GOT_32", 0, 32, 0}, |
| 111 | {"fixup_Hexagon_LD_GOT_16", 0, 32, 0}, |
| 112 | {"fixup_Hexagon_IE_LO16", 0, 32, 0}, |
| 113 | {"fixup_Hexagon_IE_HI16", 0, 32, 0}, |
| 114 | {"fixup_Hexagon_IE_32", 0, 32, 0}, |
| 115 | {"fixup_Hexagon_IE_16", 0, 32, 0}, |
| 116 | {"fixup_Hexagon_IE_GOT_LO16", 0, 32, 0}, |
| 117 | {"fixup_Hexagon_IE_GOT_HI16", 0, 32, 0}, |
| 118 | {"fixup_Hexagon_IE_GOT_32", 0, 32, 0}, |
| 119 | {"fixup_Hexagon_IE_GOT_16", 0, 32, 0}, |
| 120 | {"fixup_Hexagon_TPREL_LO16", 0, 32, 0}, |
| 121 | {"fixup_Hexagon_TPREL_HI16", 0, 32, 0}, |
| 122 | {"fixup_Hexagon_TPREL_32", 0, 32, 0}, |
| 123 | {"fixup_Hexagon_TPREL_16", 0, 32, 0}, |
| 124 | {"fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, |
| 125 | {"fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0}, |
| 126 | {"fixup_Hexagon_GOTREL_16_X", 0, 32, 0}, |
| 127 | {"fixup_Hexagon_GOTREL_11_X", 0, 32, 0}, |
| 128 | {"fixup_Hexagon_GOT_32_6_X", 0, 32, 0}, |
| 129 | {"fixup_Hexagon_GOT_16_X", 0, 32, 0}, |
| 130 | {"fixup_Hexagon_GOT_11_X", 0, 32, 0}, |
| 131 | {"fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0}, |
| 132 | {"fixup_Hexagon_DTPREL_16_X", 0, 32, 0}, |
| 133 | {"fixup_Hexagon_DTPREL_11_X", 0, 32, 0}, |
| 134 | {"fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0}, |
| 135 | {"fixup_Hexagon_GD_GOT_16_X", 0, 32, 0}, |
| 136 | {"fixup_Hexagon_GD_GOT_11_X", 0, 32, 0}, |
| 137 | {"fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0}, |
| 138 | {"fixup_Hexagon_LD_GOT_16_X", 0, 32, 0}, |
| 139 | {"fixup_Hexagon_LD_GOT_11_X", 0, 32, 0}, |
| 140 | {"fixup_Hexagon_IE_32_6_X", 0, 32, 0}, |
| 141 | {"fixup_Hexagon_IE_16_X", 0, 32, 0}, |
| 142 | {"fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0}, |
| 143 | {"fixup_Hexagon_IE_GOT_16_X", 0, 32, 0}, |
| 144 | {"fixup_Hexagon_IE_GOT_11_X", 0, 32, 0}, |
| 145 | {"fixup_Hexagon_TPREL_32_6_X", 0, 32, 0}, |
| 146 | {"fixup_Hexagon_TPREL_16_X", 0, 32, 0}, |
| 147 | {"fixup_Hexagon_TPREL_11_X", 0, 32, 0}}; |
| 148 | |
| 149 | if (Kind < FirstTargetFixupKind) { |
| 150 | return MCAsmBackend::getFixupKindInfo(Kind); |
| 151 | } |
| 152 | |
| 153 | assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && |
| 154 | "Invalid kind!"); |
| 155 | return Infos[Kind - FirstTargetFixupKind]; |
| 156 | } |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 157 | |
| 158 | void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/, |
| 159 | unsigned /*DataSize*/, uint64_t /*Value*/, |
| 160 | bool /*IsPCRel*/) const override { |
| 161 | return; |
| 162 | } |
| 163 | |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 164 | bool isInstRelaxable(MCInst const &HMI) const { |
| 165 | const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 166 | bool Relaxable = false; |
| 167 | // Branches and loop-setup insns are handled as necessary by relaxation. |
| 168 | if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || |
| 169 | (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV && |
| 170 | MCID.isBranch()) || |
| 171 | (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && |
| 172 | HMI.getOpcode() != Hexagon::C4_addipc)) |
| 173 | if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) |
| 174 | Relaxable = true; |
| 175 | |
| 176 | return Relaxable; |
| 177 | } |
| 178 | |
| 179 | /// MayNeedRelaxation - Check whether the given instruction may need |
| 180 | /// relaxation. |
| 181 | /// |
| 182 | /// \param Inst - The instruction to test. |
Colin LeMahieu | b510fb3 | 2015-05-30 20:03:07 +0000 | [diff] [blame] | 183 | bool mayNeedRelaxation(MCInst const &Inst) const override { |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 184 | assert(HexagonMCInstrInfo::isBundle(Inst)); |
| 185 | bool PreviousIsExtender = false; |
| 186 | for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) { |
| 187 | auto const &Inst = *I.getInst(); |
| 188 | if (!PreviousIsExtender) { |
| 189 | if (isInstRelaxable(Inst)) |
| 190 | return true; |
| 191 | } |
| 192 | PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst); |
| 193 | } |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 194 | return false; |
| 195 | } |
| 196 | |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 197 | /// fixupNeedsRelaxation - Target specific predicate for whether a given |
| 198 | /// fixup requires the associated instruction to be relaxed. |
| 199 | bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, |
| 200 | uint64_t Value, |
| 201 | const MCRelaxableFragment *DF, |
Colin LeMahieu | b510fb3 | 2015-05-30 20:03:07 +0000 | [diff] [blame] | 202 | const MCAsmLayout &Layout) const override { |
Colin LeMahieu | 86f218e | 2015-05-30 18:55:47 +0000 | [diff] [blame] | 203 | MCInst const &MCB = DF->getInst(); |
| 204 | assert(HexagonMCInstrInfo::isBundle(MCB)); |
| 205 | |
| 206 | *RelaxTarget = nullptr; |
| 207 | MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction( |
| 208 | MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE)); |
| 209 | // If we cannot resolve the fixup value, it requires relaxation. |
| 210 | if (!Resolved) { |
| 211 | switch ((unsigned)Fixup.getKind()) { |
| 212 | case fixup_Hexagon_B22_PCREL: |
| 213 | // GetFixupCount assumes B22 won't relax |
| 214 | // Fallthrough |
| 215 | default: |
| 216 | return false; |
| 217 | break; |
| 218 | case fixup_Hexagon_B13_PCREL: |
| 219 | case fixup_Hexagon_B15_PCREL: |
| 220 | case fixup_Hexagon_B9_PCREL: |
| 221 | case fixup_Hexagon_B7_PCREL: { |
| 222 | if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) { |
| 223 | ++relaxedCnt; |
| 224 | *RelaxTarget = &MCI; |
| 225 | return true; |
| 226 | } else { |
| 227 | return false; |
| 228 | } |
| 229 | break; |
| 230 | } |
| 231 | } |
| 232 | } |
| 233 | bool Relaxable = isInstRelaxable(MCI); |
| 234 | if (Relaxable == false) |
| 235 | return false; |
| 236 | |
| 237 | MCFixupKind Kind = Fixup.getKind(); |
| 238 | int64_t sValue = Value; |
| 239 | int64_t maxValue; |
| 240 | |
| 241 | switch ((unsigned)Kind) { |
| 242 | case fixup_Hexagon_B7_PCREL: |
| 243 | maxValue = 1 << 8; |
| 244 | break; |
| 245 | case fixup_Hexagon_B9_PCREL: |
| 246 | maxValue = 1 << 10; |
| 247 | break; |
| 248 | case fixup_Hexagon_B15_PCREL: |
| 249 | maxValue = 1 << 16; |
| 250 | break; |
| 251 | case fixup_Hexagon_B22_PCREL: |
| 252 | maxValue = 1 << 23; |
| 253 | break; |
| 254 | default: |
| 255 | maxValue = INT64_MAX; |
| 256 | break; |
| 257 | } |
| 258 | |
| 259 | bool isFarAway = -maxValue > sValue || sValue > maxValue - 1; |
| 260 | |
| 261 | if (isFarAway) { |
| 262 | if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) { |
| 263 | ++relaxedCnt; |
| 264 | *RelaxTarget = &MCI; |
| 265 | return true; |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | return false; |
| 270 | } |
| 271 | |
| 272 | /// Simple predicate for targets where !Resolved implies requiring relaxation |
| 273 | bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, |
| 274 | const MCRelaxableFragment *DF, |
| 275 | const MCAsmLayout &Layout) const override { |
| 276 | llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 277 | } |
| 278 | |
Colin LeMahieu | 8bb168b | 2015-11-13 01:12:25 +0000 | [diff] [blame] | 279 | void relaxInstruction(MCInst const & Inst, |
| 280 | MCInst & Res) const override { |
| 281 | assert(HexagonMCInstrInfo::isBundle(Inst) && |
| 282 | "Hexagon relaxInstruction only works on bundles"); |
| 283 | |
Colin LeMahieu | f0af6e5 | 2015-11-13 17:42:46 +0000 | [diff] [blame^] | 284 | Res = HexagonMCInstrInfo::createBundle(); |
Colin LeMahieu | 8bb168b | 2015-11-13 01:12:25 +0000 | [diff] [blame] | 285 | // Copy the results into the bundle. |
| 286 | bool Update = false; |
| 287 | for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) { |
| 288 | MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst()); |
| 289 | |
| 290 | // if immediate extender needed, add it in |
| 291 | if (*RelaxTarget == &CrntHMI) { |
| 292 | Update = true; |
| 293 | assert((HexagonMCInstrInfo::bundleSize(Res) < HEXAGON_PACKET_SIZE) && |
| 294 | "No room to insert extender for relaxation"); |
| 295 | |
| 296 | MCInst *HMIx = |
| 297 | new MCInst(HexagonMCInstrInfo::deriveExtender( |
| 298 | *MCII, CrntHMI, |
| 299 | HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI))); |
| 300 | |
| 301 | Res.addOperand(MCOperand::createInst(HMIx)); |
| 302 | *RelaxTarget = nullptr; |
| 303 | } |
| 304 | // now copy over the original instruction(the one we may have extended) |
| 305 | Res.addOperand(MCOperand::createInst(I.getInst())); |
| 306 | } |
| 307 | (void)Update; |
| 308 | assert(Update && "Didn't find relaxation target"); |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 309 | } |
| 310 | |
Colin LeMahieu | 1e9d1d7 | 2015-06-10 16:52:32 +0000 | [diff] [blame] | 311 | bool writeNopData(uint64_t Count, |
| 312 | MCObjectWriter * OW) const override { |
| 313 | static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP. |
| 314 | ParseIn = 0x00004000, // In packet parse-bits. |
| 315 | ParseEnd = 0x0000c000; // End of packet parse-bits. |
| 316 | |
| 317 | while(Count % HEXAGON_INSTR_SIZE) { |
| 318 | DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" << |
| 319 | Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n"); |
| 320 | --Count; |
| 321 | OW->write8(0); |
| 322 | } |
| 323 | |
| 324 | while(Count) { |
| 325 | Count -= HEXAGON_INSTR_SIZE; |
| 326 | // Close the packet whenever a multiple of the maximum packet size remains |
| 327 | uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))? |
| 328 | ParseIn: ParseEnd; |
| 329 | OW->write32(Nopcode | ParseBits); |
| 330 | } |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 331 | return true; |
| 332 | } |
| 333 | }; |
| 334 | } // end anonymous namespace |
| 335 | |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 336 | namespace llvm { |
| 337 | MCAsmBackend *createHexagonAsmBackend(Target const &T, |
| 338 | MCRegisterInfo const & /*MRI*/, |
Daniel Sanders | 50f1723 | 2015-09-15 16:17:27 +0000 | [diff] [blame] | 339 | const Triple &TT, StringRef CPU) { |
Daniel Sanders | 418caf5 | 2015-06-10 10:35:34 +0000 | [diff] [blame] | 340 | uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); |
Colin LeMahieu | a675077 | 2015-06-03 17:34:16 +0000 | [diff] [blame] | 341 | return new HexagonAsmBackend(T, OSABI, CPU); |
Colin LeMahieu | 2c76920 | 2014-11-06 17:05:51 +0000 | [diff] [blame] | 342 | } |
| 343 | } |