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gerrit-public.fairphone.software / toolchain / llvm-project / f7a02c17628e825082e845f865a3ac4616cb5e01 / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: e80ef7176c214fc5073c5f909f805f48a11f5e41 [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
37#include <cctype>
38using namespace llvm;
39
40/// InitLibcallNames - Set default libcall names.
41///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]42static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]43 Names[RTLIB::SHL_I16] = "__ashlhi3";
44 Names[RTLIB::SHL_I32] = "__ashlsi3";
45 Names[RTLIB::SHL_I64] = "__ashldi3";
46 Names[RTLIB::SHL_I128] = "__ashlti3";
47 Names[RTLIB::SRL_I16] = "__lshrhi3";
48 Names[RTLIB::SRL_I32] = "__lshrsi3";
49 Names[RTLIB::SRL_I64] = "__lshrdi3";
50 Names[RTLIB::SRL_I128] = "__lshrti3";
51 Names[RTLIB::SRA_I16] = "__ashrhi3";
52 Names[RTLIB::SRA_I32] = "__ashrsi3";
53 Names[RTLIB::SRA_I64] = "__ashrdi3";
54 Names[RTLIB::SRA_I128] = "__ashrti3";
55 Names[RTLIB::MUL_I8] = "__mulqi3";
56 Names[RTLIB::MUL_I16] = "__mulhi3";
57 Names[RTLIB::MUL_I32] = "__mulsi3";
58 Names[RTLIB::MUL_I64] = "__muldi3";
59 Names[RTLIB::MUL_I128] = "__multi3";
60 Names[RTLIB::MULO_I32] = "__mulosi4";
61 Names[RTLIB::MULO_I64] = "__mulodi4";
62 Names[RTLIB::MULO_I128] = "__muloti4";
63 Names[RTLIB::SDIV_I8] = "__divqi3";
64 Names[RTLIB::SDIV_I16] = "__divhi3";
65 Names[RTLIB::SDIV_I32] = "__divsi3";
66 Names[RTLIB::SDIV_I64] = "__divdi3";
67 Names[RTLIB::SDIV_I128] = "__divti3";
68 Names[RTLIB::UDIV_I8] = "__udivqi3";
69 Names[RTLIB::UDIV_I16] = "__udivhi3";
70 Names[RTLIB::UDIV_I32] = "__udivsi3";
71 Names[RTLIB::UDIV_I64] = "__udivdi3";
72 Names[RTLIB::UDIV_I128] = "__udivti3";
73 Names[RTLIB::SREM_I8] = "__modqi3";
74 Names[RTLIB::SREM_I16] = "__modhi3";
75 Names[RTLIB::SREM_I32] = "__modsi3";
76 Names[RTLIB::SREM_I64] = "__moddi3";
77 Names[RTLIB::SREM_I128] = "__modti3";
78 Names[RTLIB::UREM_I8] = "__umodqi3";
79 Names[RTLIB::UREM_I16] = "__umodhi3";
80 Names[RTLIB::UREM_I32] = "__umodsi3";
81 Names[RTLIB::UREM_I64] = "__umoddi3";
82 Names[RTLIB::UREM_I128] = "__umodti3";
83
84 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]85 Names[RTLIB::SDIVREM_I8] = nullptr;
86 Names[RTLIB::SDIVREM_I16] = nullptr;
87 Names[RTLIB::SDIVREM_I32] = nullptr;
88 Names[RTLIB::SDIVREM_I64] = nullptr;
89 Names[RTLIB::SDIVREM_I128] = nullptr;
90 Names[RTLIB::UDIVREM_I8] = nullptr;
91 Names[RTLIB::UDIVREM_I16] = nullptr;
92 Names[RTLIB::UDIVREM_I32] = nullptr;
93 Names[RTLIB::UDIVREM_I64] = nullptr;
94 Names[RTLIB::UDIVREM_I128] = nullptr;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]95
96 Names[RTLIB::NEG_I32] = "__negsi2";
97 Names[RTLIB::NEG_I64] = "__negdi2";
98 Names[RTLIB::ADD_F32] = "__addsf3";
99 Names[RTLIB::ADD_F64] = "__adddf3";
100 Names[RTLIB::ADD_F80] = "__addxf3";
101 Names[RTLIB::ADD_F128] = "__addtf3";
102 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
103 Names[RTLIB::SUB_F32] = "__subsf3";
104 Names[RTLIB::SUB_F64] = "__subdf3";
105 Names[RTLIB::SUB_F80] = "__subxf3";
106 Names[RTLIB::SUB_F128] = "__subtf3";
107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
108 Names[RTLIB::MUL_F32] = "__mulsf3";
109 Names[RTLIB::MUL_F64] = "__muldf3";
110 Names[RTLIB::MUL_F80] = "__mulxf3";
111 Names[RTLIB::MUL_F128] = "__multf3";
112 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
113 Names[RTLIB::DIV_F32] = "__divsf3";
114 Names[RTLIB::DIV_F64] = "__divdf3";
115 Names[RTLIB::DIV_F80] = "__divxf3";
116 Names[RTLIB::DIV_F128] = "__divtf3";
117 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
118 Names[RTLIB::REM_F32] = "fmodf";
119 Names[RTLIB::REM_F64] = "fmod";
120 Names[RTLIB::REM_F80] = "fmodl";
121 Names[RTLIB::REM_F128] = "fmodl";
122 Names[RTLIB::REM_PPCF128] = "fmodl";
123 Names[RTLIB::FMA_F32] = "fmaf";
124 Names[RTLIB::FMA_F64] = "fma";
125 Names[RTLIB::FMA_F80] = "fmal";
126 Names[RTLIB::FMA_F128] = "fmal";
127 Names[RTLIB::FMA_PPCF128] = "fmal";
128 Names[RTLIB::POWI_F32] = "__powisf2";
129 Names[RTLIB::POWI_F64] = "__powidf2";
130 Names[RTLIB::POWI_F80] = "__powixf2";
131 Names[RTLIB::POWI_F128] = "__powitf2";
132 Names[RTLIB::POWI_PPCF128] = "__powitf2";
133 Names[RTLIB::SQRT_F32] = "sqrtf";
134 Names[RTLIB::SQRT_F64] = "sqrt";
135 Names[RTLIB::SQRT_F80] = "sqrtl";
136 Names[RTLIB::SQRT_F128] = "sqrtl";
137 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
138 Names[RTLIB::LOG_F32] = "logf";
139 Names[RTLIB::LOG_F64] = "log";
140 Names[RTLIB::LOG_F80] = "logl";
141 Names[RTLIB::LOG_F128] = "logl";
142 Names[RTLIB::LOG_PPCF128] = "logl";
143 Names[RTLIB::LOG2_F32] = "log2f";
144 Names[RTLIB::LOG2_F64] = "log2";
145 Names[RTLIB::LOG2_F80] = "log2l";
146 Names[RTLIB::LOG2_F128] = "log2l";
147 Names[RTLIB::LOG2_PPCF128] = "log2l";
148 Names[RTLIB::LOG10_F32] = "log10f";
149 Names[RTLIB::LOG10_F64] = "log10";
150 Names[RTLIB::LOG10_F80] = "log10l";
151 Names[RTLIB::LOG10_F128] = "log10l";
152 Names[RTLIB::LOG10_PPCF128] = "log10l";
153 Names[RTLIB::EXP_F32] = "expf";
154 Names[RTLIB::EXP_F64] = "exp";
155 Names[RTLIB::EXP_F80] = "expl";
156 Names[RTLIB::EXP_F128] = "expl";
157 Names[RTLIB::EXP_PPCF128] = "expl";
158 Names[RTLIB::EXP2_F32] = "exp2f";
159 Names[RTLIB::EXP2_F64] = "exp2";
160 Names[RTLIB::EXP2_F80] = "exp2l";
161 Names[RTLIB::EXP2_F128] = "exp2l";
162 Names[RTLIB::EXP2_PPCF128] = "exp2l";
163 Names[RTLIB::SIN_F32] = "sinf";
164 Names[RTLIB::SIN_F64] = "sin";
165 Names[RTLIB::SIN_F80] = "sinl";
166 Names[RTLIB::SIN_F128] = "sinl";
167 Names[RTLIB::SIN_PPCF128] = "sinl";
168 Names[RTLIB::COS_F32] = "cosf";
169 Names[RTLIB::COS_F64] = "cos";
170 Names[RTLIB::COS_F80] = "cosl";
171 Names[RTLIB::COS_F128] = "cosl";
172 Names[RTLIB::COS_PPCF128] = "cosl";
173 Names[RTLIB::POW_F32] = "powf";
174 Names[RTLIB::POW_F64] = "pow";
175 Names[RTLIB::POW_F80] = "powl";
176 Names[RTLIB::POW_F128] = "powl";
177 Names[RTLIB::POW_PPCF128] = "powl";
178 Names[RTLIB::CEIL_F32] = "ceilf";
179 Names[RTLIB::CEIL_F64] = "ceil";
180 Names[RTLIB::CEIL_F80] = "ceill";
181 Names[RTLIB::CEIL_F128] = "ceill";
182 Names[RTLIB::CEIL_PPCF128] = "ceill";
183 Names[RTLIB::TRUNC_F32] = "truncf";
184 Names[RTLIB::TRUNC_F64] = "trunc";
185 Names[RTLIB::TRUNC_F80] = "truncl";
186 Names[RTLIB::TRUNC_F128] = "truncl";
187 Names[RTLIB::TRUNC_PPCF128] = "truncl";
188 Names[RTLIB::RINT_F32] = "rintf";
189 Names[RTLIB::RINT_F64] = "rint";
190 Names[RTLIB::RINT_F80] = "rintl";
191 Names[RTLIB::RINT_F128] = "rintl";
192 Names[RTLIB::RINT_PPCF128] = "rintl";
193 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
194 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
195 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
196 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
197 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]198 Names[RTLIB::ROUND_F32] = "roundf";
199 Names[RTLIB::ROUND_F64] = "round";
200 Names[RTLIB::ROUND_F80] = "roundl";
201 Names[RTLIB::ROUND_F128] = "roundl";
202 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]203 Names[RTLIB::FLOOR_F32] = "floorf";
204 Names[RTLIB::FLOOR_F64] = "floor";
205 Names[RTLIB::FLOOR_F80] = "floorl";
206 Names[RTLIB::FLOOR_F128] = "floorl";
207 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]208 Names[RTLIB::ROUND_F32] = "roundf";
209 Names[RTLIB::ROUND_F64] = "round";
210 Names[RTLIB::ROUND_F80] = "roundl";
211 Names[RTLIB::ROUND_F128] = "roundl";
212 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]213 Names[RTLIB::COPYSIGN_F32] = "copysignf";
214 Names[RTLIB::COPYSIGN_F64] = "copysign";
215 Names[RTLIB::COPYSIGN_F80] = "copysignl";
216 Names[RTLIB::COPYSIGN_F128] = "copysignl";
217 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
218 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
219 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
220 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
221 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
222 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]223 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
224 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
225 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
226 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]227 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
228 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
229 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
230 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
231 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
232 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
233 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
234 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
235 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
236 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
237 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
238 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
239 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
240 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
241 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
242 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
243 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
244 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
245 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
246 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
247 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
248 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
249 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
250 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
251 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
252 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
253 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
254 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
255 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
256 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
257 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
258 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
259 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
260 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
261 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
262 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
263 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
264 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
265 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
266 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
267 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
268 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
269 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
270 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
271 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
272 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
273 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
274 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
275 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
276 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
277 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
278 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
279 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
280 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
281 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
282 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
283 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
284 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
285 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
286 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
287 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
288 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
289 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
290 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
291 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
292 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
293 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
294 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
295 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
296 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
297 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
298 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
299 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
300 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
301 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
302 Names[RTLIB::OEQ_F32] = "__eqsf2";
303 Names[RTLIB::OEQ_F64] = "__eqdf2";
304 Names[RTLIB::OEQ_F128] = "__eqtf2";
305 Names[RTLIB::UNE_F32] = "__nesf2";
306 Names[RTLIB::UNE_F64] = "__nedf2";
307 Names[RTLIB::UNE_F128] = "__netf2";
308 Names[RTLIB::OGE_F32] = "__gesf2";
309 Names[RTLIB::OGE_F64] = "__gedf2";
310 Names[RTLIB::OGE_F128] = "__getf2";
311 Names[RTLIB::OLT_F32] = "__ltsf2";
312 Names[RTLIB::OLT_F64] = "__ltdf2";
313 Names[RTLIB::OLT_F128] = "__lttf2";
314 Names[RTLIB::OLE_F32] = "__lesf2";
315 Names[RTLIB::OLE_F64] = "__ledf2";
316 Names[RTLIB::OLE_F128] = "__letf2";
317 Names[RTLIB::OGT_F32] = "__gtsf2";
318 Names[RTLIB::OGT_F64] = "__gtdf2";
319 Names[RTLIB::OGT_F128] = "__gttf2";
320 Names[RTLIB::UO_F32] = "__unordsf2";
321 Names[RTLIB::UO_F64] = "__unorddf2";
322 Names[RTLIB::UO_F128] = "__unordtf2";
323 Names[RTLIB::O_F32] = "__unordsf2";
324 Names[RTLIB::O_F64] = "__unorddf2";
325 Names[RTLIB::O_F128] = "__unordtf2";
326 Names[RTLIB::MEMCPY] = "memcpy";
327 Names[RTLIB::MEMMOVE] = "memmove";
328 Names[RTLIB::MEMSET] = "memset";
329 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
330 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
331 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
332 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
333 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]334 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]335 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
336 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
337 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
338 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]339 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]340 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
341 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
342 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
343 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]344 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]345 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
346 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
347 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
348 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]349 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]350 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
351 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
352 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
353 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]354 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]355 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
356 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
357 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
358 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]359 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]360 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
361 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
362 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
363 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]364 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]365 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
366 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
367 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
368 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]369 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]370 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
371 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
372 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
373 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
374 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
375 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
376 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
377 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
378 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
379 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
380 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
381 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
382 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
383 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
384 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
385 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
386 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
387 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
388 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
389 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000[diff] [blame]390
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]391 if (TT.getEnvironment() == Triple::GNU) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]392 Names[RTLIB::SINCOS_F32] = "sincosf";
393 Names[RTLIB::SINCOS_F64] = "sincos";
394 Names[RTLIB::SINCOS_F80] = "sincosl";
395 Names[RTLIB::SINCOS_F128] = "sincosl";
396 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
397 } else {
398 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]399 Names[RTLIB::SINCOS_F32] = nullptr;
400 Names[RTLIB::SINCOS_F64] = nullptr;
401 Names[RTLIB::SINCOS_F80] = nullptr;
402 Names[RTLIB::SINCOS_F128] = nullptr;
403 Names[RTLIB::SINCOS_PPCF128] = nullptr;
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]404 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]405
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]406 if (TT.getOS() != Triple::OpenBSD) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]407 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
408 } else {
409 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]410 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr;
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]411 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]412}
413
414/// InitLibcallCallingConvs - Set default libcall CallingConvs.
415///
416static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
417 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
418 CCs[i] = CallingConv::C;
419 }
420}
421
422/// getFPEXT - Return the FPEXT_*_* value for the given types, or
423/// UNKNOWN_LIBCALL if there is none.
424RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame^]425 if (OpVT == MVT::f16) {
426 if (RetVT == MVT::f32)
427 return FPEXT_F16_F32;
428 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]429 if (RetVT == MVT::f64)
430 return FPEXT_F32_F64;
431 if (RetVT == MVT::f128)
432 return FPEXT_F32_F128;
433 } else if (OpVT == MVT::f64) {
434 if (RetVT == MVT::f128)
435 return FPEXT_F64_F128;
436 }
437
438 return UNKNOWN_LIBCALL;
439}
440
441/// getFPROUND - Return the FPROUND_*_* value for the given types, or
442/// UNKNOWN_LIBCALL if there is none.
443RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]444 if (RetVT == MVT::f16) {
445 if (OpVT == MVT::f32)
446 return FPROUND_F32_F16;
447 if (OpVT == MVT::f64)
448 return FPROUND_F64_F16;
449 if (OpVT == MVT::f80)
450 return FPROUND_F80_F16;
451 if (OpVT == MVT::f128)
452 return FPROUND_F128_F16;
453 if (OpVT == MVT::ppcf128)
454 return FPROUND_PPCF128_F16;
455 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]456 if (OpVT == MVT::f64)
457 return FPROUND_F64_F32;
458 if (OpVT == MVT::f80)
459 return FPROUND_F80_F32;
460 if (OpVT == MVT::f128)
461 return FPROUND_F128_F32;
462 if (OpVT == MVT::ppcf128)
463 return FPROUND_PPCF128_F32;
464 } else if (RetVT == MVT::f64) {
465 if (OpVT == MVT::f80)
466 return FPROUND_F80_F64;
467 if (OpVT == MVT::f128)
468 return FPROUND_F128_F64;
469 if (OpVT == MVT::ppcf128)
470 return FPROUND_PPCF128_F64;
471 }
472
473 return UNKNOWN_LIBCALL;
474}
475
476/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
477/// UNKNOWN_LIBCALL if there is none.
478RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
479 if (OpVT == MVT::f32) {
480 if (RetVT == MVT::i8)
481 return FPTOSINT_F32_I8;
482 if (RetVT == MVT::i16)
483 return FPTOSINT_F32_I16;
484 if (RetVT == MVT::i32)
485 return FPTOSINT_F32_I32;
486 if (RetVT == MVT::i64)
487 return FPTOSINT_F32_I64;
488 if (RetVT == MVT::i128)
489 return FPTOSINT_F32_I128;
490 } else if (OpVT == MVT::f64) {
491 if (RetVT == MVT::i8)
492 return FPTOSINT_F64_I8;
493 if (RetVT == MVT::i16)
494 return FPTOSINT_F64_I16;
495 if (RetVT == MVT::i32)
496 return FPTOSINT_F64_I32;
497 if (RetVT == MVT::i64)
498 return FPTOSINT_F64_I64;
499 if (RetVT == MVT::i128)
500 return FPTOSINT_F64_I128;
501 } else if (OpVT == MVT::f80) {
502 if (RetVT == MVT::i32)
503 return FPTOSINT_F80_I32;
504 if (RetVT == MVT::i64)
505 return FPTOSINT_F80_I64;
506 if (RetVT == MVT::i128)
507 return FPTOSINT_F80_I128;
508 } else if (OpVT == MVT::f128) {
509 if (RetVT == MVT::i32)
510 return FPTOSINT_F128_I32;
511 if (RetVT == MVT::i64)
512 return FPTOSINT_F128_I64;
513 if (RetVT == MVT::i128)
514 return FPTOSINT_F128_I128;
515 } else if (OpVT == MVT::ppcf128) {
516 if (RetVT == MVT::i32)
517 return FPTOSINT_PPCF128_I32;
518 if (RetVT == MVT::i64)
519 return FPTOSINT_PPCF128_I64;
520 if (RetVT == MVT::i128)
521 return FPTOSINT_PPCF128_I128;
522 }
523 return UNKNOWN_LIBCALL;
524}
525
526/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
527/// UNKNOWN_LIBCALL if there is none.
528RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
529 if (OpVT == MVT::f32) {
530 if (RetVT == MVT::i8)
531 return FPTOUINT_F32_I8;
532 if (RetVT == MVT::i16)
533 return FPTOUINT_F32_I16;
534 if (RetVT == MVT::i32)
535 return FPTOUINT_F32_I32;
536 if (RetVT == MVT::i64)
537 return FPTOUINT_F32_I64;
538 if (RetVT == MVT::i128)
539 return FPTOUINT_F32_I128;
540 } else if (OpVT == MVT::f64) {
541 if (RetVT == MVT::i8)
542 return FPTOUINT_F64_I8;
543 if (RetVT == MVT::i16)
544 return FPTOUINT_F64_I16;
545 if (RetVT == MVT::i32)
546 return FPTOUINT_F64_I32;
547 if (RetVT == MVT::i64)
548 return FPTOUINT_F64_I64;
549 if (RetVT == MVT::i128)
550 return FPTOUINT_F64_I128;
551 } else if (OpVT == MVT::f80) {
552 if (RetVT == MVT::i32)
553 return FPTOUINT_F80_I32;
554 if (RetVT == MVT::i64)
555 return FPTOUINT_F80_I64;
556 if (RetVT == MVT::i128)
557 return FPTOUINT_F80_I128;
558 } else if (OpVT == MVT::f128) {
559 if (RetVT == MVT::i32)
560 return FPTOUINT_F128_I32;
561 if (RetVT == MVT::i64)
562 return FPTOUINT_F128_I64;
563 if (RetVT == MVT::i128)
564 return FPTOUINT_F128_I128;
565 } else if (OpVT == MVT::ppcf128) {
566 if (RetVT == MVT::i32)
567 return FPTOUINT_PPCF128_I32;
568 if (RetVT == MVT::i64)
569 return FPTOUINT_PPCF128_I64;
570 if (RetVT == MVT::i128)
571 return FPTOUINT_PPCF128_I128;
572 }
573 return UNKNOWN_LIBCALL;
574}
575
576/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
577/// UNKNOWN_LIBCALL if there is none.
578RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
579 if (OpVT == MVT::i32) {
580 if (RetVT == MVT::f32)
581 return SINTTOFP_I32_F32;
582 if (RetVT == MVT::f64)
583 return SINTTOFP_I32_F64;
584 if (RetVT == MVT::f80)
585 return SINTTOFP_I32_F80;
586 if (RetVT == MVT::f128)
587 return SINTTOFP_I32_F128;
588 if (RetVT == MVT::ppcf128)
589 return SINTTOFP_I32_PPCF128;
590 } else if (OpVT == MVT::i64) {
591 if (RetVT == MVT::f32)
592 return SINTTOFP_I64_F32;
593 if (RetVT == MVT::f64)
594 return SINTTOFP_I64_F64;
595 if (RetVT == MVT::f80)
596 return SINTTOFP_I64_F80;
597 if (RetVT == MVT::f128)
598 return SINTTOFP_I64_F128;
599 if (RetVT == MVT::ppcf128)
600 return SINTTOFP_I64_PPCF128;
601 } else if (OpVT == MVT::i128) {
602 if (RetVT == MVT::f32)
603 return SINTTOFP_I128_F32;
604 if (RetVT == MVT::f64)
605 return SINTTOFP_I128_F64;
606 if (RetVT == MVT::f80)
607 return SINTTOFP_I128_F80;
608 if (RetVT == MVT::f128)
609 return SINTTOFP_I128_F128;
610 if (RetVT == MVT::ppcf128)
611 return SINTTOFP_I128_PPCF128;
612 }
613 return UNKNOWN_LIBCALL;
614}
615
616/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
617/// UNKNOWN_LIBCALL if there is none.
618RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
619 if (OpVT == MVT::i32) {
620 if (RetVT == MVT::f32)
621 return UINTTOFP_I32_F32;
622 if (RetVT == MVT::f64)
623 return UINTTOFP_I32_F64;
624 if (RetVT == MVT::f80)
625 return UINTTOFP_I32_F80;
626 if (RetVT == MVT::f128)
627 return UINTTOFP_I32_F128;
628 if (RetVT == MVT::ppcf128)
629 return UINTTOFP_I32_PPCF128;
630 } else if (OpVT == MVT::i64) {
631 if (RetVT == MVT::f32)
632 return UINTTOFP_I64_F32;
633 if (RetVT == MVT::f64)
634 return UINTTOFP_I64_F64;
635 if (RetVT == MVT::f80)
636 return UINTTOFP_I64_F80;
637 if (RetVT == MVT::f128)
638 return UINTTOFP_I64_F128;
639 if (RetVT == MVT::ppcf128)
640 return UINTTOFP_I64_PPCF128;
641 } else if (OpVT == MVT::i128) {
642 if (RetVT == MVT::f32)
643 return UINTTOFP_I128_F32;
644 if (RetVT == MVT::f64)
645 return UINTTOFP_I128_F64;
646 if (RetVT == MVT::f80)
647 return UINTTOFP_I128_F80;
648 if (RetVT == MVT::f128)
649 return UINTTOFP_I128_F128;
650 if (RetVT == MVT::ppcf128)
651 return UINTTOFP_I128_PPCF128;
652 }
653 return UNKNOWN_LIBCALL;
654}
655
656/// InitCmpLibcallCCs - Set default comparison libcall CC.
657///
658static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
659 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
660 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
661 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
662 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
663 CCs[RTLIB::UNE_F32] = ISD::SETNE;
664 CCs[RTLIB::UNE_F64] = ISD::SETNE;
665 CCs[RTLIB::UNE_F128] = ISD::SETNE;
666 CCs[RTLIB::OGE_F32] = ISD::SETGE;
667 CCs[RTLIB::OGE_F64] = ISD::SETGE;
668 CCs[RTLIB::OGE_F128] = ISD::SETGE;
669 CCs[RTLIB::OLT_F32] = ISD::SETLT;
670 CCs[RTLIB::OLT_F64] = ISD::SETLT;
671 CCs[RTLIB::OLT_F128] = ISD::SETLT;
672 CCs[RTLIB::OLE_F32] = ISD::SETLE;
673 CCs[RTLIB::OLE_F64] = ISD::SETLE;
674 CCs[RTLIB::OLE_F128] = ISD::SETLE;
675 CCs[RTLIB::OGT_F32] = ISD::SETGT;
676 CCs[RTLIB::OGT_F64] = ISD::SETGT;
677 CCs[RTLIB::OGT_F128] = ISD::SETGT;
678 CCs[RTLIB::UO_F32] = ISD::SETNE;
679 CCs[RTLIB::UO_F64] = ISD::SETNE;
680 CCs[RTLIB::UO_F128] = ISD::SETNE;
681 CCs[RTLIB::O_F32] = ISD::SETEQ;
682 CCs[RTLIB::O_F64] = ISD::SETEQ;
683 CCs[RTLIB::O_F128] = ISD::SETEQ;
684}
685
686/// NOTE: The constructor takes ownership of TLOF.
687TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
688 const TargetLoweringObjectFile *tlof)
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]689 : TM(tm), DL(TM.getDataLayout()), TLOF(*tlof) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]690 initActions();
691
692 // Perform these initializations only once.
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]693 IsLittleEndian = DL->isLittleEndian();
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]694 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
695 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
696 = MaxStoresPerMemmoveOptSize = 4;
697 UseUnderscoreSetJmp = false;
698 UseUnderscoreLongJmp = false;
699 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]700 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]701 HasExtractBitsInsn = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]702 IntDivIsCheap = false;
703 Pow2DivIsCheap = false;
704 JumpIsExpensive = false;
705 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]706 MaskAndBranchFoldingIsLegal = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]707 StackPointerRegisterToSaveRestore = 0;
708 ExceptionPointerRegister = 0;
709 ExceptionSelectorRegister = 0;
710 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]711 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]712 BooleanVectorContents = UndefinedBooleanContent;
713 SchedPreferenceInfo = Sched::ILP;
714 JumpBufSize = 0;
715 JumpBufAlignment = 0;
716 MinFunctionAlignment = 0;
717 PrefFunctionAlignment = 0;
718 PrefLoopAlignment = 0;
719 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]720 InsertFencesForAtomic = false;
721 SupportJumpTables = true;
722 MinimumJumpTableEntries = 4;
723
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]724 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple()));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]725 InitCmpLibcallCCs(CmpLibcallCCs);
726 InitLibcallCallingConvs(LibcallCallingConvs);
727}
728
729TargetLoweringBase::~TargetLoweringBase() {
730 delete &TLOF;
731}
732
733void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]734 // All operations default to being supported.
735 memset(OpActions, 0, sizeof(OpActions));
736 memset(LoadExtActions, 0, sizeof(LoadExtActions));
737 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
738 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
739 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]740 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
741 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]742
743 // Set default actions for various operations.
744 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
745 // Default all indexed load / store to expand.
746 for (unsigned IM = (unsigned)ISD::PRE_INC;
747 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
748 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
749 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
750 }
751
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]752 // Most backends expect to see the node which just returns the value loaded.
753 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
754 (MVT::SimpleValueType)VT, Expand);
755
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]756 // These operations default to expand.
757 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]759
760 // These library functions default to expand.
761 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]762
763 // These operations default to expand for vector types.
764 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]765 VT <= MVT::LAST_VECTOR_VALUETYPE) {
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]766 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
Chandler Carruth0b666e02014-07-10 12:32:32 +0000[diff] [blame]767 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG,
768 (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG,
770 (MVT::SimpleValueType)VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]771 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG,
772 (MVT::SimpleValueType)VT, Expand);
773 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]774 }
775
776 // Most targets ignore the @llvm.prefetch intrinsic.
777 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
778
779 // ConstantFP nodes default to expand. Targets can either change this to
780 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
781 // to optimize expansions for certain constants.
782 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
783 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
784 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
785 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
786 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
787
788 // These library functions default to expand.
789 setOperationAction(ISD::FLOG , MVT::f16, Expand);
790 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
791 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
792 setOperationAction(ISD::FEXP , MVT::f16, Expand);
793 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
794 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
795 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
796 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
797 setOperationAction(ISD::FRINT, MVT::f16, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]799 setOperationAction(ISD::FROUND, MVT::f16, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]800 setOperationAction(ISD::FLOG , MVT::f32, Expand);
801 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
802 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
803 setOperationAction(ISD::FEXP , MVT::f32, Expand);
804 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
805 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
806 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
807 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
808 setOperationAction(ISD::FRINT, MVT::f32, Expand);
809 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]810 setOperationAction(ISD::FROUND, MVT::f32, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]811 setOperationAction(ISD::FLOG , MVT::f64, Expand);
812 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
813 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
814 setOperationAction(ISD::FEXP , MVT::f64, Expand);
815 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
816 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
817 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
818 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
819 setOperationAction(ISD::FRINT, MVT::f64, Expand);
820 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]821 setOperationAction(ISD::FROUND, MVT::f64, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]822 setOperationAction(ISD::FLOG , MVT::f128, Expand);
823 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
824 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
825 setOperationAction(ISD::FEXP , MVT::f128, Expand);
826 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
827 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
828 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
829 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
830 setOperationAction(ISD::FRINT, MVT::f128, Expand);
831 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]832 setOperationAction(ISD::FROUND, MVT::f128, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]833
834 // Default ISD::TRAP to expand (which turns it into abort).
835 setOperationAction(ISD::TRAP, MVT::Other, Expand);
836
837 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
838 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
839 //
840 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]841}
842
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]843MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
844 return MVT::getIntegerVT(getPointerSizeInBits(AS));
845}
846
847unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]848 return DL->getPointerSizeInBits(AS);
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]849}
850
851unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
852 assert(Ty->isPointerTy());
853 return getPointerSizeInBits(Ty->getPointerAddressSpace());
854}
855
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]856MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]857 return MVT::getIntegerVT(8*DL->getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]858}
859
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]860EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
861 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
862 if (LHSTy.isVector())
863 return LHSTy;
864 return getScalarShiftAmountTy(LHSTy);
865}
866
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]867/// canOpTrap - Returns true if the operation can trap for the value type.
868/// VT must be a legal type.
869bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
870 assert(isTypeLegal(VT));
871 switch (Op) {
872 default:
873 return false;
874 case ISD::FDIV:
875 case ISD::FREM:
876 case ISD::SDIV:
877 case ISD::UDIV:
878 case ISD::SREM:
879 case ISD::UREM:
880 return true;
881 }
882}
883
884
885static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
886 unsigned &NumIntermediates,
887 MVT &RegisterVT,
888 TargetLoweringBase *TLI) {
889 // Figure out the right, legal destination reg to copy into.
890 unsigned NumElts = VT.getVectorNumElements();
891 MVT EltTy = VT.getVectorElementType();
892
893 unsigned NumVectorRegs = 1;
894
895 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
896 // could break down into LHS/RHS like LegalizeDAG does.
897 if (!isPowerOf2_32(NumElts)) {
898 NumVectorRegs = NumElts;
899 NumElts = 1;
900 }
901
902 // Divide the input until we get to a supported size. This will always
903 // end with a scalar if the target doesn't support vectors.
904 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
905 NumElts >>= 1;
906 NumVectorRegs <<= 1;
907 }
908
909 NumIntermediates = NumVectorRegs;
910
911 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
912 if (!TLI->isTypeLegal(NewVT))
913 NewVT = EltTy;
914 IntermediateVT = NewVT;
915
916 unsigned NewVTSize = NewVT.getSizeInBits();
917
918 // Convert sizes such as i33 to i64.
919 if (!isPowerOf2_32(NewVTSize))
920 NewVTSize = NextPowerOf2(NewVTSize);
921
922 MVT DestVT = TLI->getRegisterType(NewVT);
923 RegisterVT = DestVT;
924 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
925 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
926
927 // Otherwise, promotion or legal types use the same number of registers as
928 // the vector decimated to the appropriate level.
929 return NumVectorRegs;
930}
931
932/// isLegalRC - Return true if the value types that can be represented by the
933/// specified register class are all legal.
934bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
935 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
936 I != E; ++I) {
937 if (isTypeLegal(*I))
938 return true;
939 }
940 return false;
941}
942
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]943/// Replace/modify any TargetFrameIndex operands with a targte-dependent
944/// sequence of memory operands that is recognized by PrologEpilogInserter.
945MachineBasicBlock*
946TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
947 MachineBasicBlock *MBB) const {
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]948 MachineFunction &MF = *MI->getParent()->getParent();
949
950 // MI changes inside this loop as we grow operands.
951 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
952 MachineOperand &MO = MI->getOperand(OperIdx);
953 if (!MO.isFI())
954 continue;
955
956 // foldMemoryOperand builds a new MI after replacing a single FI operand
957 // with the canonical set of five x86 addressing-mode operands.
958 int FI = MO.getIndex();
959 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
960
961 // Copy operands before the frame-index.
962 for (unsigned i = 0; i < OperIdx; ++i)
963 MIB.addOperand(MI->getOperand(i));
964 // Add frame index operands: direct-mem-ref tag, #FI, offset.
965 MIB.addImm(StackMaps::DirectMemRefOp);
966 MIB.addOperand(MI->getOperand(OperIdx));
967 MIB.addImm(0);
968 // Copy the operands after the frame index.
969 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
970 MIB.addOperand(MI->getOperand(i));
971
972 // Inherit previous memory operands.
973 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
974 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
975
976 // Add a new memory operand for this FI.
977 const MachineFrameInfo &MFI = *MF.getFrameInfo();
978 assert(MFI.getObjectOffset(FI) != -1);
979 MachineMemOperand *MMO =
980 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
981 MachineMemOperand::MOLoad,
982 TM.getDataLayout()->getPointerSize(),
983 MFI.getObjectAlignment(FI));
984 MIB->addMemOperand(MF, MMO);
985
986 // Replace the instruction and update the operand index.
987 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
988 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
989 MI->eraseFromParent();
990 MI = MIB;
991 }
992 return MBB;
993}
994
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]995/// findRepresentativeClass - Return the largest legal super-reg register class
996/// of the register class for the specified type and its associated "cost".
997std::pair<const TargetRegisterClass*, uint8_t>
998TargetLoweringBase::findRepresentativeClass(MVT VT) const {
999 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1000 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1001 if (!RC)
1002 return std::make_pair(RC, 0);
1003
1004 // Compute the set of all super-register classes.
1005 BitVector SuperRegRC(TRI->getNumRegClasses());
1006 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1007 SuperRegRC.setBitsInMask(RCI.getMask());
1008
1009 // Find the first legal register class with the largest spill size.
1010 const TargetRegisterClass *BestRC = RC;
1011 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1012 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1013 // We want the largest possible spill size.
1014 if (SuperRC->getSize() <= BestRC->getSize())
1015 continue;
1016 if (!isLegalRC(SuperRC))
1017 continue;
1018 BestRC = SuperRC;
1019 }
1020 return std::make_pair(BestRC, 1);
1021}
1022
1023/// computeRegisterProperties - Once all of the register classes are added,
1024/// this allows us to compute derived properties we expose.
1025void TargetLoweringBase::computeRegisterProperties() {
1026 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
1027 "Too many value types for ValueTypeActions to hold!");
1028
1029 // Everything defaults to needing one register.
1030 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1031 NumRegistersForVT[i] = 1;
1032 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1033 }
1034 // ...except isVoid, which doesn't need any registers.
1035 NumRegistersForVT[MVT::isVoid] = 0;
1036
1037 // Find the largest integer register class.
1038 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1039 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1040 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1041
1042 // Every integer value type larger than this largest register takes twice as
1043 // many registers to represent as the previous ValueType.
1044 for (unsigned ExpandedReg = LargestIntReg + 1;
1045 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1046 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1047 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1048 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1049 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1050 TypeExpandInteger);
1051 }
1052
1053 // Inspect all of the ValueType's smaller than the largest integer
1054 // register to see which ones need promotion.
1055 unsigned LegalIntReg = LargestIntReg;
1056 for (unsigned IntReg = LargestIntReg - 1;
1057 IntReg >= (unsigned)MVT::i1; --IntReg) {
1058 MVT IVT = (MVT::SimpleValueType)IntReg;
1059 if (isTypeLegal(IVT)) {
1060 LegalIntReg = IntReg;
1061 } else {
1062 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1063 (const MVT::SimpleValueType)LegalIntReg;
1064 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1065 }
1066 }
1067
1068 // ppcf128 type is really two f64's.
1069 if (!isTypeLegal(MVT::ppcf128)) {
1070 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1071 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1072 TransformToType[MVT::ppcf128] = MVT::f64;
1073 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1074 }
1075
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1076 // Decide how to handle f128. If the target does not have native f128 support,
1077 // expand it to i128 and we will be generating soft float library calls.
1078 if (!isTypeLegal(MVT::f128)) {
1079 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1080 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1081 TransformToType[MVT::f128] = MVT::i128;
1082 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1083 }
1084
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1085 // Decide how to handle f64. If the target does not have native f64 support,
1086 // expand it to i64 and we will be generating soft float library calls.
1087 if (!isTypeLegal(MVT::f64)) {
1088 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1089 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1090 TransformToType[MVT::f64] = MVT::i64;
1091 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1092 }
1093
1094 // Decide how to handle f32. If the target does not have native support for
1095 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1096 if (!isTypeLegal(MVT::f32)) {
1097 if (isTypeLegal(MVT::f64)) {
1098 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1099 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1100 TransformToType[MVT::f32] = MVT::f64;
1101 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1102 } else {
1103 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1104 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1105 TransformToType[MVT::f32] = MVT::i32;
1106 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1107 }
1108 }
1109
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1110 if (!isTypeLegal(MVT::f16)) {
1111 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1112 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1113 TransformToType[MVT::f16] = MVT::i16;
1114 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat);
1115 }
1116
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1117 // Loop over all of the vector value types to see which need transformations.
1118 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1119 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1120 MVT VT = (MVT::SimpleValueType) i;
1121 if (isTypeLegal(VT))
1122 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1123
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1124 MVT EltVT = VT.getVectorElementType();
1125 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1126 bool IsLegalWiderType = false;
1127 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1128 switch (PreferredAction) {
1129 case TypePromoteInteger: {
1130 // Try to promote the elements of integer vectors. If no legal
1131 // promotion was found, fall through to the widen-vector method.
1132 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1133 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1134 // Promote vectors of integers to vectors with the same number
1135 // of elements, with a wider element type.
1136 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1137 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1138 && SVT.getScalarType().isInteger()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1139 TransformToType[i] = SVT;
1140 RegisterTypeForVT[i] = SVT;
1141 NumRegistersForVT[i] = 1;
1142 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1143 IsLegalWiderType = true;
1144 break;
1145 }
1146 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1147 if (IsLegalWiderType)
1148 break;
1149 }
1150 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1151 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1152 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1153 MVT SVT = (MVT::SimpleValueType) nVT;
1154 if (SVT.getVectorElementType() == EltVT
1155 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1156 TransformToType[i] = SVT;
1157 RegisterTypeForVT[i] = SVT;
1158 NumRegistersForVT[i] = 1;
1159 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1160 IsLegalWiderType = true;
1161 break;
1162 }
1163 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1164 if (IsLegalWiderType)
1165 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1166 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1167 case TypeSplitVector:
1168 case TypeScalarizeVector: {
1169 MVT IntermediateVT;
1170 MVT RegisterVT;
1171 unsigned NumIntermediates;
1172 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1173 NumIntermediates, RegisterVT, this);
1174 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1175
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1176 MVT NVT = VT.getPow2VectorType();
1177 if (NVT == VT) {
1178 // Type is already a power of 2. The default action is to split.
1179 TransformToType[i] = MVT::Other;
1180 if (PreferredAction == TypeScalarizeVector)
1181 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1182 else
1183 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1184 } else {
1185 TransformToType[i] = NVT;
1186 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1187 }
1188 break;
1189 }
1190 default:
1191 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1192 }
1193 }
1194
1195 // Determine the 'representative' register class for each value type.
1196 // An representative register class is the largest (meaning one which is
1197 // not a sub-register class / subreg register class) legal register class for
1198 // a group of value types. For example, on i386, i8, i16, and i32
1199 // representative would be GR32; while on x86_64 it's GR64.
1200 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1201 const TargetRegisterClass* RRC;
1202 uint8_t Cost;
Benjamin Kramerd6f1f842014-03-02 13:30:33 +0000[diff] [blame]1203 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1204 RepRegClassForVT[i] = RRC;
1205 RepRegClassCostForVT[i] = Cost;
1206 }
1207}
1208
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]1209EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1210 assert(!VT.isVector() && "No default SetCC type for vectors!");
1211 return getPointerTy(0).SimpleTy;
1212}
1213
1214MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1215 return MVT::i32; // return the default value
1216}
1217
1218/// getVectorTypeBreakdown - Vector types are broken down into some number of
1219/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1220/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1221/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1222///
1223/// This method returns the number of registers needed, and the VT for each
1224/// register. It also returns the VT and quantity of the intermediate values
1225/// before they are promoted/expanded.
1226///
1227unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1228 EVT &IntermediateVT,
1229 unsigned &NumIntermediates,
1230 MVT &RegisterVT) const {
1231 unsigned NumElts = VT.getVectorNumElements();
1232
1233 // If there is a wider vector type with the same element type as this one,
1234 // or a promoted vector type that has the same number of elements which
1235 // are wider, then we should convert to that legal vector type.
1236 // This handles things like <2 x float> -> <4 x float> and
1237 // <4 x i1> -> <4 x i32>.
1238 LegalizeTypeAction TA = getTypeAction(Context, VT);
1239 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1240 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1241 if (isTypeLegal(RegisterEVT)) {
1242 IntermediateVT = RegisterEVT;
1243 RegisterVT = RegisterEVT.getSimpleVT();
1244 NumIntermediates = 1;
1245 return 1;
1246 }
1247 }
1248
1249 // Figure out the right, legal destination reg to copy into.
1250 EVT EltTy = VT.getVectorElementType();
1251
1252 unsigned NumVectorRegs = 1;
1253
1254 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1255 // could break down into LHS/RHS like LegalizeDAG does.
1256 if (!isPowerOf2_32(NumElts)) {
1257 NumVectorRegs = NumElts;
1258 NumElts = 1;
1259 }
1260
1261 // Divide the input until we get to a supported size. This will always
1262 // end with a scalar if the target doesn't support vectors.
1263 while (NumElts > 1 && !isTypeLegal(
1264 EVT::getVectorVT(Context, EltTy, NumElts))) {
1265 NumElts >>= 1;
1266 NumVectorRegs <<= 1;
1267 }
1268
1269 NumIntermediates = NumVectorRegs;
1270
1271 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1272 if (!isTypeLegal(NewVT))
1273 NewVT = EltTy;
1274 IntermediateVT = NewVT;
1275
1276 MVT DestVT = getRegisterType(Context, NewVT);
1277 RegisterVT = DestVT;
1278 unsigned NewVTSize = NewVT.getSizeInBits();
1279
1280 // Convert sizes such as i33 to i64.
1281 if (!isPowerOf2_32(NewVTSize))
1282 NewVTSize = NextPowerOf2(NewVTSize);
1283
1284 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1285 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1286
1287 // Otherwise, promotion or legal types use the same number of registers as
1288 // the vector decimated to the appropriate level.
1289 return NumVectorRegs;
1290}
1291
1292/// Get the EVTs and ArgFlags collections that represent the legalized return
1293/// type of the given function. This does not require a DAG or a return value,
1294/// and is suitable for use before any DAGs for the function are constructed.
1295/// TODO: Move this out of TargetLowering.cpp.
1296void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1297 SmallVectorImpl<ISD::OutputArg> &Outs,
1298 const TargetLowering &TLI) {
1299 SmallVector<EVT, 4> ValueVTs;
1300 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1301 unsigned NumValues = ValueVTs.size();
1302 if (NumValues == 0) return;
1303
1304 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1305 EVT VT = ValueVTs[j];
1306 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1307
1308 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1309 ExtendKind = ISD::SIGN_EXTEND;
1310 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1311 ExtendKind = ISD::ZERO_EXTEND;
1312
1313 // FIXME: C calling convention requires the return type to be promoted to
1314 // at least 32-bit. But this is not necessary for non-C calling
1315 // conventions. The frontend should mark functions whose return values
1316 // require promoting with signext or zeroext attributes.
1317 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1318 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1319 if (VT.bitsLT(MinVT))
1320 VT = MinVT;
1321 }
1322
1323 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1324 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1325
1326 // 'inreg' on function refers to return value
1327 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1328 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1329 Flags.setInReg();
1330
1331 // Propagate extension type if any
1332 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1333 Flags.setSExt();
1334 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1335 Flags.setZExt();
1336
1337 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1338 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1339 }
1340}
1341
1342/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1343/// function arguments in the caller parameter area. This is the actual
1344/// alignment, not its logarithm.
1345unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]1346 return DL->getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1347}
1348
1349//===----------------------------------------------------------------------===//
1350// TargetTransformInfo Helpers
1351//===----------------------------------------------------------------------===//
1352
1353int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1354 enum InstructionOpcodes {
1355#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1356#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1357#include "llvm/IR/Instruction.def"
1358 };
1359 switch (static_cast<InstructionOpcodes>(Opcode)) {
1360 case Ret: return 0;
1361 case Br: return 0;
1362 case Switch: return 0;
1363 case IndirectBr: return 0;
1364 case Invoke: return 0;
1365 case Resume: return 0;
1366 case Unreachable: return 0;
1367 case Add: return ISD::ADD;
1368 case FAdd: return ISD::FADD;
1369 case Sub: return ISD::SUB;
1370 case FSub: return ISD::FSUB;
1371 case Mul: return ISD::MUL;
1372 case FMul: return ISD::FMUL;
1373 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1374 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1375 case FDiv: return ISD::FDIV;
1376 case URem: return ISD::UREM;
1377 case SRem: return ISD::SREM;
1378 case FRem: return ISD::FREM;
1379 case Shl: return ISD::SHL;
1380 case LShr: return ISD::SRL;
1381 case AShr: return ISD::SRA;
1382 case And: return ISD::AND;
1383 case Or: return ISD::OR;
1384 case Xor: return ISD::XOR;
1385 case Alloca: return 0;
1386 case Load: return ISD::LOAD;
1387 case Store: return ISD::STORE;
1388 case GetElementPtr: return 0;
1389 case Fence: return 0;
1390 case AtomicCmpXchg: return 0;
1391 case AtomicRMW: return 0;
1392 case Trunc: return ISD::TRUNCATE;
1393 case ZExt: return ISD::ZERO_EXTEND;
1394 case SExt: return ISD::SIGN_EXTEND;
1395 case FPToUI: return ISD::FP_TO_UINT;
1396 case FPToSI: return ISD::FP_TO_SINT;
1397 case UIToFP: return ISD::UINT_TO_FP;
1398 case SIToFP: return ISD::SINT_TO_FP;
1399 case FPTrunc: return ISD::FP_ROUND;
1400 case FPExt: return ISD::FP_EXTEND;
1401 case PtrToInt: return ISD::BITCAST;
1402 case IntToPtr: return ISD::BITCAST;
1403 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1404 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1405 case ICmp: return ISD::SETCC;
1406 case FCmp: return ISD::SETCC;
1407 case PHI: return 0;
1408 case Call: return 0;
1409 case Select: return ISD::SELECT;
1410 case UserOp1: return 0;
1411 case UserOp2: return 0;
1412 case VAArg: return 0;
1413 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1414 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1415 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1416 case ExtractValue: return ISD::MERGE_VALUES;
1417 case InsertValue: return ISD::MERGE_VALUES;
1418 case LandingPad: return 0;
1419 }
1420
1421 llvm_unreachable("Unknown instruction type encountered!");
1422}
1423
1424std::pair<unsigned, MVT>
1425TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1426 LLVMContext &C = Ty->getContext();
1427 EVT MTy = getValueType(Ty);
1428
1429 unsigned Cost = 1;
1430 // We keep legalizing the type until we find a legal kind. We assume that
1431 // the only operation that costs anything is the split. After splitting
1432 // we need to handle two types.
1433 while (true) {
1434 LegalizeKind LK = getTypeConversion(C, MTy);
1435
1436 if (LK.first == TypeLegal)
1437 return std::make_pair(Cost, MTy.getSimpleVT());
1438
1439 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1440 Cost *= 2;
1441
1442 // Keep legalizing the type.
1443 MTy = LK.second;
1444 }
1445}
1446
1447//===----------------------------------------------------------------------===//
1448// Loop Strength Reduction hooks
1449//===----------------------------------------------------------------------===//
1450
1451/// isLegalAddressingMode - Return true if the addressing mode represented
1452/// by AM is legal for this target, for a load/store of the specified type.
1453bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1454 Type *Ty) const {
1455 // The default implementation of this implements a conservative RISCy, r+r and
1456 // r+i addr mode.
1457
1458 // Allows a sign-extended 16-bit immediate field.
1459 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1460 return false;
1461
1462 // No global is ever allowed as a base.
1463 if (AM.BaseGV)
1464 return false;
1465
1466 // Only support r+r,
1467 switch (AM.Scale) {
1468 case 0: // "r+i" or just "i", depending on HasBaseReg.
1469 break;
1470 case 1:
1471 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1472 return false;
1473 // Otherwise we have r+r or r+i.
1474 break;
1475 case 2:
1476 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1477 return false;
1478 // Allow 2*r as r+r.
1479 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1480 default: // Don't allow n * r
1481 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1482 }
1483
1484 return true;
1485}