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Evan Cheng54b68e32011-07-01 20:45:01 +00001//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCSubtargetInfo.h"
Evan Cheng54b68e32011-07-01 20:45:01 +000011#include "llvm/ADT/StringRef.h"
Evan Chengc5e6d2f2011-07-11 03:57:24 +000012#include "llvm/ADT/Triple.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000013#include "llvm/MC/MCInstrItineraries.h"
14#include "llvm/MC/SubtargetFeature.h"
Evan Cheng54b68e32011-07-01 20:45:01 +000015#include "llvm/Support/raw_ostream.h"
16#include <algorithm>
17
18using namespace llvm;
19
Craig Topper0e6c5b62012-10-03 06:47:18 +000020/// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
Andrew Trickba7b9212012-09-18 05:33:15 +000021/// with feature string). Recompute feature bits and scheduling model.
22void
23MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
24 SubtargetFeatures Features(FS);
Eric Christopherdc5072d2014-05-06 20:23:04 +000025 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
Craig Toppera8442342013-09-18 05:54:09 +000026 InitCPUSchedModel(CPU);
27}
28
29void
30MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
Andrew Trickba7b9212012-09-18 05:33:15 +000031 if (!CPU.empty())
Duncan P. N. Exon Smithf862f872015-07-10 22:13:43 +000032 CPUSchedModel = &getSchedModelForCPU(CPU);
Andrew Trickba7b9212012-09-18 05:33:15 +000033 else
Duncan P. N. Exon Smithf862f872015-07-10 22:13:43 +000034 CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
Andrew Trickba7b9212012-09-18 05:33:15 +000035}
36
Daniel Sandersa73f1fd2015-06-10 12:11:26 +000037void MCSubtargetInfo::InitMCSubtargetInfo(
38 const Triple &TT, StringRef C, StringRef FS,
39 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
40 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
41 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
42 const InstrStage *IS, const unsigned *OC, const unsigned *FP) {
Evan Chengc5e6d2f2011-07-11 03:57:24 +000043 TargetTriple = TT;
Eric Christopher6e4ed492015-01-26 17:33:30 +000044 CPU = C;
Evan Cheng1a72add62011-07-07 07:07:08 +000045 ProcFeatures = PF;
46 ProcDesc = PD;
Andrew Trickac36af42012-09-14 20:26:41 +000047 ProcSchedModels = ProcSched;
Andrew Trickab722bd2012-09-18 03:18:56 +000048 WriteProcResTable = WPR;
49 WriteLatencyTable = WL;
50 ReadAdvanceTable = RA;
51
Evan Cheng1a72add62011-07-07 07:07:08 +000052 Stages = IS;
53 OperandCycles = OC;
Andrew Trick030e2f82012-07-07 03:59:48 +000054 ForwardingPaths = FP;
Evan Cheng1a72add62011-07-07 07:07:08 +000055
Andrew Trickba7b9212012-09-18 05:33:15 +000056 InitMCProcessorInfo(CPU, FS);
Evan Cheng1a72add62011-07-07 07:07:08 +000057}
58
Evan Cheng91111d22011-07-09 05:47:46 +000059/// ToggleFeature - Toggle a feature and returns the re-computed feature
60/// bits. This version does not change the implied bits.
Michael Kupersteindb0712f2015-05-26 10:47:10 +000061FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
62 FeatureBits.flip(FB);
63 return FeatureBits;
64}
65
66FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
Evan Cheng91111d22011-07-09 05:47:46 +000067 FeatureBits ^= FB;
68 return FeatureBits;
69}
70
71/// ToggleFeature - Toggle a feature and returns the re-computed feature
72/// bits. This version will also change all implied bits.
Michael Kupersteindb0712f2015-05-26 10:47:10 +000073FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
Evan Cheng91111d22011-07-09 05:47:46 +000074 SubtargetFeatures Features;
Eric Christopherdc5072d2014-05-06 20:23:04 +000075 FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
Evan Cheng91111d22011-07-09 05:47:46 +000076 return FeatureBits;
77}
78
John Brawnd03d2292015-06-05 13:29:24 +000079FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
80 SubtargetFeatures Features;
81 FeatureBits = Features.ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
82 return FeatureBits;
83}
Evan Cheng91111d22011-07-09 05:47:46 +000084
Duncan P. N. Exon Smithf862f872015-07-10 22:13:43 +000085const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
Andrew Trickac36af42012-09-14 20:26:41 +000086 assert(ProcSchedModels && "Processor machine model not available!");
Evan Cheng54b68e32011-07-01 20:45:01 +000087
Eric Christopherdc5072d2014-05-06 20:23:04 +000088 unsigned NumProcs = ProcDesc.size();
Evan Cheng54b68e32011-07-01 20:45:01 +000089#ifndef NDEBUG
90 for (size_t i = 1; i < NumProcs; i++) {
Andrew Trickac36af42012-09-14 20:26:41 +000091 assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
Andrew Trick87255e32012-07-07 04:00:00 +000092 "Processor machine model table is not sorted");
Evan Cheng54b68e32011-07-01 20:45:01 +000093 }
94#endif
95
96 // Find entry
Artyom Skroboveab75152014-01-25 16:56:18 +000097 const SubtargetInfoKV *Found =
98 std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
99 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
Craig Topper768ccc42015-04-02 04:27:50 +0000100 if (CPU != "help") // Don't error if the user asked for help.
101 errs() << "'" << CPU
102 << "' is not a recognized processor for this target"
103 << " (ignoring processor)\n";
Pete Cooper11759452014-09-02 17:43:54 +0000104 return MCSchedModel::GetDefaultSchedModel();
Artyom Skroboveab75152014-01-25 16:56:18 +0000105 }
Andrew Trick87255e32012-07-07 04:00:00 +0000106 assert(Found->Value && "Missing processor SchedModel value");
Pete Cooper11759452014-09-02 17:43:54 +0000107 return *(const MCSchedModel *)Found->Value;
Andrew Trick87255e32012-07-07 04:00:00 +0000108}
Evan Cheng54b68e32011-07-01 20:45:01 +0000109
Andrew Trick87255e32012-07-07 04:00:00 +0000110InstrItineraryData
111MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
Pete Cooper11759452014-09-02 17:43:54 +0000112 const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
Andrew Trick87255e32012-07-07 04:00:00 +0000113 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
Evan Cheng54b68e32011-07-01 20:45:01 +0000114}
Andrew Trickd2a19da2012-09-14 20:26:46 +0000115
116/// Initialize an InstrItineraryData instance.
117void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
Duncan P. N. Exon Smithf862f872015-07-10 22:13:43 +0000118 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
119 ForwardingPaths);
Andrew Trickd2a19da2012-09-14 20:26:46 +0000120}