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gerrit-public.fairphone.software / toolchain / llvm-project / f8fff213d5e700ec8aa4c556f0751cb4b35991b1 / . / llvm / lib / Target / Mips / Mips64InstrInfo.td
blob: 346cf1e911edfadb64e8fecc38bc107b335751d1 [file] [log] [blame]
Akira Hatanaka7d7ee0c2011-09-24 01:40:18 +0000[diff] [blame]1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips64 instructions.
11//
12//===----------------------------------------------------------------------===//
Akira Hatanakac1179672011-09-28 17:50:27 +0000[diff] [blame]13
14//===----------------------------------------------------------------------===//
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]15// Mips Operand, Complex Patterns and Transformations Definitions.
16//===----------------------------------------------------------------------===//
17
18// Instruction operand types
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]19def shamt_64 : Operand<i64>;
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]20
21// Unsigned Operand
22def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
24}
25
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]26// Transformation Function - get Imm - 32.
27def Subtract32 : SDNodeXForm<imm, [{
Akira Hatanaka4a04a562011-12-07 20:10:24 +0000[diff] [blame]28 return getImm(N, (unsigned)N->getZExtValue() - 32);
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]29}]>;
30
Akira Hatanaka2a232d82011-12-19 19:44:09 +0000[diff] [blame]31// shamt must fit in 6 bits.
32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]33
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]34//===----------------------------------------------------------------------===//
Akira Hatanaka36036412011-09-29 20:37:56 +0000[diff] [blame]35// Instructions specific format
36//===----------------------------------------------------------------------===//
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]37let DecoderNamespace = "Mips64" in {
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]38
Akira Hatanakab1527b72012-12-20 04:20:09 +0000[diff] [blame]39multiclass Atomic2Ops64<PatFrag Op> {
Craig Toppera8c5ec02013-01-07 05:45:56 +0000[diff] [blame]40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
41 Requires<[NotN64, HasStdEnc]>;
42 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
43 Requires<[IsN64, HasStdEnc]> {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]44 let isCodeGenOnly = 1;
45 }
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]46}
47
Akira Hatanakab1527b72012-12-20 04:20:09 +0000[diff] [blame]48multiclass AtomicCmpSwap64<PatFrag Op> {
Craig Toppera8c5ec02013-01-07 05:45:56 +0000[diff] [blame]49 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
50 Requires<[NotN64, HasStdEnc]>;
51 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
52 Requires<[IsN64, HasStdEnc]> {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]53 let isCodeGenOnly = 1;
54 }
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]55}
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]56}
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]57let usesCustomInserter = 1, Predicates = [HasStdEnc],
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]58 DecoderNamespace = "Mips64" in {
Akira Hatanakab1527b72012-12-20 04:20:09 +0000[diff] [blame]59 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
60 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
61 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
62 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
63 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
64 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
65 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
66 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]67}
68
Akira Hatanaka42543192013-04-30 23:22:09 +0000[diff] [blame]69/// Pseudo instructions for loading and storing accumulator registers.
Akira Hatanakac8d85022013-03-30 00:54:52 +0000[diff] [blame]70let isPseudo = 1 in {
71 defm LOAD_AC128 : LoadM<"load_ac128", ACRegs128>;
72 defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>;
73}
74
Akira Hatanaka36036412011-09-29 20:37:56 +0000[diff] [blame]75//===----------------------------------------------------------------------===//
76// Instruction definition
77//===----------------------------------------------------------------------===//
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]78let DecoderNamespace = "Mips64" in {
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]79/// Arithmetic Instructions (ALU Immediate)
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]80def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]81def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, IIArith,
82 immSExt16, add>,
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000[diff] [blame]83 ADDI_FM<0x19>, IsAsCheapAsAMove;
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]84def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
85 and>,
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000[diff] [blame]86 ADDI_FM<0xc>;
Akira Hatanakae7f1acc2012-12-20 04:27:52 +0000[diff] [blame]87def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
88 SLTI_FM<0xa>;
89def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
90 SLTI_FM<0xb>;
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]91def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
92 or>,
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000[diff] [blame]93 ADDI_FM<0xd>;
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]94def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, IILogic, immZExt16,
95 xor>,
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000[diff] [blame]96 ADDI_FM<0xe>;
Akira Hatanakae738efc2012-12-21 22:46:07 +0000[diff] [blame]97def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]98
Akira Hatanaka36036412011-09-29 20:37:56 +0000[diff] [blame]99/// Arithmetic Instructions (3-Operand, R-Type)
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]100def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]101def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIArith, add>,
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]102 ADD_FM<0, 0x2d>;
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]103def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIArith, sub>,
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]104 ADD_FM<0, 0x2f>;
Akira Hatanakae7f1acc2012-12-20 04:27:52 +0000[diff] [blame]105def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
106def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]107def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIArith, and>, ADD_FM<0, 0x24>;
108def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIArith, or>, ADD_FM<0, 0x25>;
109def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIArith, xor>, ADD_FM<0, 0x26>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]110def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]111
112/// Shift Instructions
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]113def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
Akira Hatanakaf412e752013-01-04 19:25:46 +0000[diff] [blame]114 SRA_FM<0x38, 0>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]115def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
Akira Hatanakaf412e752013-01-04 19:25:46 +0000[diff] [blame]116 SRA_FM<0x3a, 0>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]117def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
Akira Hatanakaf412e752013-01-04 19:25:46 +0000[diff] [blame]118 SRA_FM<0x3b, 0>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]119def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>;
120def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>;
121def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>;
122def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>;
123def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>;
124def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]125}
Akira Hatanaka7ba8a8d2011-09-30 18:51:46 +0000[diff] [blame]126// Rotate Instructions
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]127let Predicates = [HasMips64r2, HasStdEnc],
Akira Hatanakacdf4fd82012-05-22 03:10:09 +0000[diff] [blame]128 DecoderNamespace = "Mips64" in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]129 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]130 SRA_FM<0x3a, 1>;
131 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>,
132 SRLV_FM<0x16, 1>;
Akira Hatanaka7ba8a8d2011-09-30 18:51:46 +0000[diff] [blame]133}
134
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]135let DecoderNamespace = "Mips64" in {
Akira Hatanakabe68f3c2011-10-11 00:27:28 +0000[diff] [blame]136/// Load and Store Instructions
Jia Liuf54f60f2012-02-28 07:46:26 +0000[diff] [blame]137/// aligned
Akira Hatanakab34ad782013-07-02 00:00:02 +0000[diff] [blame]138defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8, IILoad>, LW_FM<0x20>;
139defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8, IILoad>, LW_FM<0x24>;
140defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16, IILoad>, LW_FM<0x21>;
141defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16, IILoad>, LW_FM<0x25>;
142defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32, IILoad>, LW_FM<0x23>;
143defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32, IILoad>, LW_FM<0x27>;
144defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8, IIStore>, LW_FM<0x28>;
145defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16, IIStore>, LW_FM<0x29>;
146defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32, IIStore>, LW_FM<0x2b>;
147defm LD : LoadM<"ld", CPU64Regs, load, IILoad>, LW_FM<0x37>;
148defm SD : StoreM<"sd", CPU64Regs, store, IIStore>, LW_FM<0x3f>;
Akira Hatanakabe68f3c2011-10-11 00:27:28 +0000[diff] [blame]149
Akira Hatanakaf11571d2012-06-02 00:04:19 +0000[diff] [blame]150/// load/store left/right
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]151defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
152defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
153defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
154defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
155
Akira Hatanakae1826d72012-12-21 23:01:24 +0000[diff] [blame]156defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
157defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
158defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
159defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
Akira Hatanakaf11571d2012-06-02 00:04:19 +0000[diff] [blame]160
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]161/// Load-linked, Store-conditional
Akira Hatanakae1826d72012-12-21 23:01:24 +0000[diff] [blame]162let Predicates = [NotN64, HasStdEnc] in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]163 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>;
164 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]165}
Akira Hatanakae1826d72012-12-21 23:01:24 +0000[diff] [blame]166
167let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]168 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>;
169 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]170}
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]171
Akira Hatanaka4b6ac982011-10-11 18:49:17 +0000[diff] [blame]172/// Jump and Branch Instructions
Akira Hatanakaa1580422012-12-21 23:03:50 +0000[diff] [blame]173def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
Jack Carter51785c42013-05-16 19:40:19 +0000[diff] [blame]174def BEQ64 : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>;
175def BNE64 : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>;
176def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>;
177def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>;
178def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>;
179def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]180}
181let DecoderNamespace = "Mips64" in
Akira Hatanakaa1580422012-12-21 23:03:50 +0000[diff] [blame]182def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
Akira Hatanaka061d1ea2013-02-07 19:48:00 +0000[diff] [blame]183def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>;
Akira Hatanakaa1580422012-12-21 23:03:50 +0000[diff] [blame]184def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
Akira Hatanakab89a4bf2012-01-04 03:02:47 +0000[diff] [blame]185
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]186let DecoderNamespace = "Mips64" in {
Akira Hatanakaa279d9b2011-10-03 20:01:11 +0000[diff] [blame]187/// Multiply and Divide Instructions.
Akira Hatanaka1baf2ea2013-07-12 22:43:20 +0000[diff] [blame]188def DMULT : Mult<"dmult", IIImult, CPU64RegsOpnd, [HI64, LO64]>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]189 MULT_FM<0, 0x1c>;
Akira Hatanaka1baf2ea2013-07-12 22:43:20 +0000[diff] [blame]190def DMULTu : Mult<"dmultu", IIImult, CPU64RegsOpnd, [HI64, LO64]>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]191 MULT_FM<0, 0x1d>;
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]192def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult,
Akira Hatanaka1baf2ea2013-07-12 22:43:20 +0000[diff] [blame]193 IIImult>;
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]194def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu,
Akira Hatanaka1baf2ea2013-07-12 22:43:20 +0000[diff] [blame]195 IIImult>;
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]196def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
197def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
198def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem,
Akira Hatanaka1cb02422013-05-20 18:07:43 +0000[diff] [blame]199 IIIdiv, 0, 1, 1>;
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]200def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU,
Akira Hatanaka1cb02422013-05-20 18:07:43 +0000[diff] [blame]201 IIIdiv, 0, 1, 1>;
Akira Hatanakaa279d9b2011-10-03 20:01:11 +0000[diff] [blame]202
Akira Hatanakab14c6e42012-12-21 22:39:17 +0000[diff] [blame]203def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
204def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
205def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
206def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
Akira Hatanakacdcc7452011-10-03 19:28:44 +0000[diff] [blame]207
Akira Hatanaka9f7ec152012-01-24 21:41:09 +0000[diff] [blame]208/// Sign Ext In Register Instructions.
Akira Hatanaka6ac2fc42012-12-21 23:21:32 +0000[diff] [blame]209def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>;
210def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>;
Akira Hatanaka9f7ec152012-01-24 21:41:09 +0000[diff] [blame]211
Akira Hatanaka48a72ca2011-10-03 21:16:50 +0000[diff] [blame]212/// Count Leading
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]213def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>;
214def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>;
Akira Hatanaka48a72ca2011-10-03 21:16:50 +0000[diff] [blame]215
Akira Hatanaka4706ac92011-12-20 23:56:43 +0000[diff] [blame]216/// Double Word Swap Bytes/HalfWords
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]217def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>;
218def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>;
Akira Hatanaka4706ac92011-12-20 23:56:43 +0000[diff] [blame]219
Akira Hatanaka6ac2fc42012-12-21 23:21:32 +0000[diff] [blame]220def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>;
221
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]222}
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]223let DecoderNamespace = "Mips64" in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]224def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM;
Akira Hatanaka4350c182011-12-07 23:31:26 +0000[diff] [blame]225
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]226def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>;
Jack Cartercd6b0e12012-08-28 20:07:41 +0000[diff] [blame]227let Pattern = []<dag> in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]228 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>;
229 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>;
Jack Cartercd6b0e12012-08-28 20:07:41 +0000[diff] [blame]230}
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]231def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>;
Jack Carterb3f3b172012-08-31 18:06:48 +0000[diff] [blame]232let Pattern = []<dag> in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]233 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>;
234 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>;
Jack Carterb3f3b172012-08-31 18:06:48 +0000[diff] [blame]235}
Akira Hatanaka20cee2e2011-12-05 21:26:34 +0000[diff] [blame]236
Jack Carterf4946cf2012-08-07 00:35:22 +0000[diff] [blame]237let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
Jack Carter120a30a2012-08-09 19:43:18 +0000[diff] [blame]238 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]239 "dsll\t$rd, $rt, 32", [], IIArith>;
Jack Carterf4946cf2012-08-07 00:35:22 +0000[diff] [blame]240 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]241 "sll\t$rd, $rt, 0", [], IIArith>;
Jack Carterf4946cf2012-08-07 00:35:22 +0000[diff] [blame]242 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
Akira Hatanakaf8fff212013-07-31 00:55:34 +0000[diff] [blame^]243 "sll\t$rd, $rt, 0", [], IIArith>;
Jack Carterf4946cf2012-08-07 00:35:22 +0000[diff] [blame]244}
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]245}
Akira Hatanaka7ba8a8d2011-09-30 18:51:46 +0000[diff] [blame]246//===----------------------------------------------------------------------===//
247// Arbitrary patterns that map to one or more instructions
248//===----------------------------------------------------------------------===//
249
Akira Hatanakaf93b3f42011-11-14 19:06:14 +0000[diff] [blame]250// extended loads
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]251let Predicates = [NotN64, HasStdEnc] in {
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]252 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
253 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
Akira Hatanaka3e7ba762012-09-15 01:52:08 +0000[diff] [blame]254 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
255 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
Akira Hatanakaf93b3f42011-11-14 19:06:14 +0000[diff] [blame]256}
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]257let Predicates = [IsN64, HasStdEnc] in {
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]258 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
259 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
Akira Hatanaka3e7ba762012-09-15 01:52:08 +0000[diff] [blame]260 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
261 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
Akira Hatanakaf93b3f42011-11-14 19:06:14 +0000[diff] [blame]262}
Akira Hatanaka09b23eb2011-10-11 00:55:05 +0000[diff] [blame]263
264// hi/lo relocs
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]265def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
266def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
267def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
268def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
269def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
Akira Hatanakabb6e74a2012-11-21 20:40:38 +0000[diff] [blame]270def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
Akira Hatanaka7b8547c2011-11-16 22:39:56 +0000[diff] [blame]271
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]272def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
273def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
274def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
275def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
276def : MipsPat<(MipsLo tglobaltlsaddr:$in),
277 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
Akira Hatanakabb6e74a2012-11-21 20:40:38 +0000[diff] [blame]278def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
Akira Hatanaka7b8547c2011-11-16 22:39:56 +0000[diff] [blame]279
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]280def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
281 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
282def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
283 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
284def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
285 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
286def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
287 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
288def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
289 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
Akira Hatanakaf75add62011-10-11 18:53:46 +0000[diff] [blame]290
Akira Hatanakab049aef2012-02-24 22:34:47 +0000[diff] [blame]291def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
292def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
293def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
294def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
295def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
296def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
Akira Hatanakab2e05cb2011-12-07 22:11:43 +0000[diff] [blame]297
Akira Hatanaka7148bce2011-10-11 19:09:09 +0000[diff] [blame]298defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
299 ZERO_64>;
300
Akira Hatanaka68710312013-05-21 17:13:47 +0000[diff] [blame]301def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
302 (BLEZ64 i64:$lhs, bb:$dst)>;
303def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
304 (BGEZ64 i64:$lhs, bb:$dst)>;
305
Akira Hatanakaf75add62011-10-11 18:53:46 +0000[diff] [blame]306// setcc patterns
Akira Hatanaka453ac882011-10-11 21:48:01 +0000[diff] [blame]307defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
Akira Hatanaka46a79942011-10-11 21:40:01 +0000[diff] [blame]308defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
309defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
310defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
311defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
Akira Hatanakad5c13292011-11-07 18:57:41 +0000[diff] [blame]312
313// truncate
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]314def : MipsPat<(i32 (trunc CPU64Regs:$src)),
315 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]316 Requires<[IsN64, HasStdEnc]>;
Jia Liuf54f60f2012-02-28 07:46:26 +0000[diff] [blame]317
Akira Hatanakaae378af2011-12-07 23:14:41 +0000[diff] [blame]318// 32-to-64-bit extension
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]319def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
320def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
321def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
Akira Hatanaka4e210692011-12-20 22:06:20 +0000[diff] [blame]322
Akira Hatanaka494fdf12011-12-20 22:40:40 +0000[diff] [blame]323// Sign extend in register
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]324def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
325 (SLL64_64 CPU64Regs:$src)>;
Akira Hatanaka494fdf12011-12-20 22:40:40 +0000[diff] [blame]326
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]327// bswap MipsPattern
328def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
David Chisnall37051252012-10-09 16:27:43 +0000[diff] [blame]329
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]330// mflo/hi patterns.
331def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
332 (EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
333
David Chisnall37051252012-10-09 16:27:43 +0000[diff] [blame]334//===----------------------------------------------------------------------===//
335// Instruction aliases
336//===----------------------------------------------------------------------===//
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]337def : InstAlias<"move $dst, $src",
338 (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
339 Requires<[HasMips64]>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]340def : InstAlias<"and $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]341 (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
342 1>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]343 Requires<[HasMips64]>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]344def : InstAlias<"slt $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]345 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]346 Requires<[HasMips64]>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]347def : InstAlias<"xor $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]348 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
349 1>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]350 Requires<[HasMips64]>;
351def : InstAlias<"not $rt, $rs",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]352 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]353 Requires<[HasMips64]>;
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]354def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>;
Akira Hatanaka061d1ea2013-02-07 19:48:00 +0000[diff] [blame]355def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>,
356 Requires<[HasMips64]>;
Jack Cartere1d85d52013-03-28 23:02:21 +0000[diff] [blame]357def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>,
358 Requires<[HasMips64]>;
359def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>,
360 Requires<[HasMips64]>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]361def : InstAlias<"daddu $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]362 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
363 1>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]364def : InstAlias<"dadd $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]365 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
366 1>;
Jack Carter311246c62013-03-28 23:45:13 +0000[diff] [blame]367def : InstAlias<"or $rs, $rt, $imm",
368 (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
369 1>, Requires<[HasMips64]>;
Jack Carter51785c42013-05-16 19:40:19 +0000[diff] [blame]370def : InstAlias<"bnez $rs,$offset",
371 (BNE64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
372 Requires<[HasMips64]>;
373def : InstAlias<"beqz $rs,$offset",
374 (BEQ64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
375 Requires<[HasMips64]>;
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]376
Jack Carter51785c42013-05-16 19:40:19 +0000[diff] [blame]377/// Move between CPU and coprocessor registers
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]378let DecoderNamespace = "Mips64" in {
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]379def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
380 (ins CPU64RegsOpnd:$rd, uimm16:$sel),
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000[diff] [blame]381 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]382def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
383 (ins CPU64RegsOpnd:$rt),
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000[diff] [blame]384 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]385def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
386 (ins CPU64RegsOpnd:$rd, uimm16:$sel),
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000[diff] [blame]387 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]388def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
389 (ins CPU64RegsOpnd:$rt),
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000[diff] [blame]390 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]391}
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]392
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]393// Two operand (implicit 0 selector) versions:
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000[diff] [blame]394def : InstAlias<"dmfc0 $rt, $rd",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]395 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000[diff] [blame]396def : InstAlias<"dmtc0 $rt, $rd",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]397 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000[diff] [blame]398def : InstAlias<"dmfc2 $rt, $rd",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]399 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000[diff] [blame]400def : InstAlias<"dmtc2 $rt, $rd",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]401 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]402